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7 |
akhachat |
// Timing with undefined `DS1621_STANDARD ( more than 100kHz)
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// for Opencores users:
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// Delays are system bus specific. Adapt them to your system bus timing.
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// Tasks are acceptable by both 24LC16B and DS1621S devices.
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// "write/read" are the tasks from the bus interface
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// (create your own interface or change the write read just to be the tasks).
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// "data" is the value returned by the interface task.
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// Format: Bit 2, 1, 0
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// WP SCL SDA
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// if EEPROM
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// is present
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//
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task iic__stop();
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#500 write( 3'b000 );
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#1100 write( 3'b010 );
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#900 write( 3'b011 );
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endtask
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task iic_ctlop( bit [3:0] EE_or_DS, bit [2:0] blk_adr, bit op, output bit ACK );
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#1150 write( 3'b011 );
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#650 write( 3'b010 );
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#650 write( 3'b000 );
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#650 write( {2'b00, EE_or_DS[3]} );
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#650 write( {2'b01, EE_or_DS[3]} );
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#650 write( {2'b00, EE_or_DS[3]} );
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#650 write( {2'b00, EE_or_DS[2]} );
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#650 write( {2'b01, EE_or_DS[2]} );
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#650 write( {2'b00, EE_or_DS[2]} );
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#650 write( {2'b00, EE_or_DS[1]} );
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#650 write( {2'b01, EE_or_DS[1]} );
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#650 write( {2'b00, EE_or_DS[1]} );
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#650 write( {2'b00, EE_or_DS[0]} );
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#650 write( {2'b01, EE_or_DS[0]} );
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#650 write( {2'b00, EE_or_DS[0]} );
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#650 write( {2'b00, blk_adr[2]} );
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#650 write( {2'b01, blk_adr[2]} );
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#650 write( {2'b00, blk_adr[2]} );
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#650 write( {2'b00, blk_adr[1]} );
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#650 write( {2'b01, blk_adr[1]} );
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#650 write( {2'b00, blk_adr[1]} );
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#650 write( {2'b00, blk_adr[0]} );
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#650 write( {2'b01, blk_adr[0]} );
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#650 write( {2'b00, blk_adr[0]} );
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#650 write( {2'b00, op} );
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#650 write( {2'b01, op} );
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#650 write( 3'b001 ); // ACK check
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#1250 write( 3'b011 ); //
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#650 read( ACK );
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#650 write( 3'b000 ); // ACK end with SCL=0 & SDA=0 (hold time is 0 for devices on IIC)
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#650 write( 3'b001 );
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endtask
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task iic_write( bit stop, bit [7:0] data, output bit ACK );
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#750 write( {2'b00, data[7]} );
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#650 write( {2'b01, data[7]} );
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#650 write( {2'b00, data[7]} );
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#650 write( {2'b00, data[6]} );
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#650 write( {2'b01, data[6]} );
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#650 write( {2'b00, data[6]} );
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#650 write( {2'b00, data[5]} );
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#650 write( {2'b01, data[5]} );
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#650 write( {2'b00, data[5]} );
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#650 write( {2'b00, data[4]} );
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#650 write( {2'b01, data[4]} );
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#650 write( {2'b00, data[4]} );
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#650 write( {2'b00, data[3]} );
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#650 write( {2'b01, data[3]} );
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#650 write( {2'b00, data[3]} );
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#650 write( {2'b00, data[2]} );
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#650 write( {2'b01, data[2]} );
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#650 write( {2'b00, data[2]} );
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#650 write( {2'b00, data[1]} );
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#650 write( {2'b01, data[1]} );
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#650 write( {2'b00, data[1]} );
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#650 write( {2'b00, data[0]} );
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#650 write( {2'b01, data[0]} );
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#650 write( {2'b00, data[0]} );
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#650 write( 3'b001 ); // ACK check
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#650 write( 3'b011 ); //
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#650 read( ACK );
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#650 write( 3'b000 ); // ACK end with SCL=0 & SDA=0 (hold time is 0 for devices on IIC)
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if ( stop ) iic__stop;
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else
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#650 write( 3'b001 );
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endtask
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task iic__read( bit stop, output bit [7:0] data );
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bit data_bit;
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#1250 write( 3'b011 );
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| 92 |
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#650 read( data_bit ); data = {data[6:0], data_bit};
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write( 3'b001 );
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#1250 write( 3'b011 );
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#650 read( data_bit ); data = {data[6:0], data_bit};
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write( 3'b001 );
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| 97 |
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#1250 write( 3'b011 );
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#650 read( data_bit ); data = {data[6:0], data_bit};
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write( 3'b001 );
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#1250 write( 3'b011 );
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#650 read( data_bit ); data = {data[6:0], data_bit};
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write( 3'b001 );
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| 103 |
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#1250 write( 3'b011 );
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#650 read( data_bit ); data = {data[6:0], data_bit};
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write( 3'b001 );
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#1250 write( 3'b011 );
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#650 read( data_bit ); data = {data[6:0], data_bit};
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write( 3'b001 );
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#1250 write( 3'b011 );
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| 110 |
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#650 read( data_bit ); data = {data[6:0], data_bit};
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| 111 |
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write( 3'b001 );
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| 112 |
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#1250 write( 3'b011 );
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#650 read( data_bit ); data = {data[6:0], data_bit};
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if ( stop ) begin
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#650 write( 3'b001 ); // NO ACK
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| 116 |
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#1250 write( 3'b011 );
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iic__stop;
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| 118 |
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end
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| 119 |
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else begin
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| 120 |
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#650 write( 3'b000 ); // ACK
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| 121 |
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#1250 write( 3'b010 );
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| 122 |
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#650 write( 3'b000 );
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| 123 |
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#650 write( 3'b001 );
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| 124 |
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end
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| 125 |
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endtask
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