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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [fpga/] [memctrl-1/] [src/] [toplevel/] [memtest.ucf] - Blame information for rev 318

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Line No. Rev Author Line
1 318 hellwig 
#
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# memtest.ucf -- user constraints for XSA-3S1000 + XST-3 board
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#
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#
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# clock and reset
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#
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NET "clk_in"            PERIOD = 10.0ns HIGH 40%;
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NET "clk_in"            LOC = "t9";
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NET "rst_inout_n"       LOC = "d15";
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#
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# SDRAM
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#
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NET "sdram_clk"         LOC = "e10";
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NET "sdram_fb"          LOC = "n8";
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NET "sdram_cke"         LOC = "d7";
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NET "sdram_cs_n"        LOC = "b8";
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NET "sdram_ras_n"       LOC = "a9";
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NET "sdram_cas_n"       LOC = "a10";
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NET "sdram_we_n"        LOC = "b10";
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NET "sdram_ba<1>"  LOC = "c7";
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NET "sdram_ba<0>"  LOC = "a7";
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NET "sdram_a<12>"   LOC = "c6";
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NET "sdram_a<11>"   LOC = "c5";
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NET "sdram_a<10>"   LOC = "b6";
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NET "sdram_a<9>"   LOC = "a3";
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NET "sdram_a<8>"   LOC = "c2";
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NET "sdram_a<7>"   LOC = "d3";
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NET "sdram_a<6>"   LOC = "e4";
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NET "sdram_a<5>"   LOC = "c1";
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NET "sdram_a<4>"   LOC = "e3";
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NET "sdram_a<3>"   LOC = "e6";
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NET "sdram_a<2>"   LOC = "b4";
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NET "sdram_a<1>"   LOC = "a4";
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NET "sdram_a<0>"   LOC = "b5";
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NET "sdram_udqm"        LOC = "d9";
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NET "sdram_ldqm"        LOC = "c10";
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NET "sdram_dq<15>"  LOC = "f13";
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NET "sdram_dq<14>"  LOC = "f12";
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NET "sdram_dq<13>"  LOC = "c16";
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NET "sdram_dq<12>"  LOC = "d14";
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NET "sdram_dq<11>"  LOC = "b14";
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NET "sdram_dq<10>"  LOC = "c12";
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NET "sdram_dq<9>"  LOC = "b12";
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NET "sdram_dq<8>"  LOC = "b11";
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NET "sdram_dq<7>"  LOC = "d10";
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NET "sdram_dq<6>"  LOC = "c11";
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NET "sdram_dq<5>"  LOC = "a12";
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NET "sdram_dq<4>"  LOC = "d11";
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NET "sdram_dq<3>"  LOC = "b13";
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NET "sdram_dq<2>"  LOC = "a14";
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NET "sdram_dq<1>"  LOC = "d12";
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NET "sdram_dq<0>"  LOC = "c15";
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#
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# 7 segment LED
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#
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NET "ssl<6>"               LOC = "r10";
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NET "ssl<5>"               LOC = "t7";
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NET "ssl<4>"               LOC = "p10";
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NET "ssl<3>"               LOC = "r7";
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NET "ssl<2>"               LOC = "n6";
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NET "ssl<1>"               LOC = "m11";
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NET "ssl<0>"               LOC = "m6";

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