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[/] [edge/] [trunk/] [HW/] [Verilog/] [Coprocessor0.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////
//                                                              //
//  Coprocessor0 for Edge core                                  //
//                                                              //
//  This file is part of the Edge project                       //
//  http://www.opencores.org/project,edge                       //
//                                                              //
//  Description                                                 //
//  Coprocessor0 in MIPS is the control unit mainly respobsible //
//  for handling interrupts.                                    //
//                                                              //
//  Author(s):                                                  //
//      - Hesham AL-Matary, heshamelmatary@gmail.com            //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2014 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
/* Coprocessor 0 instructions definitions */
`define EXCEPTION       1 /* Take exception, save EPC and Cause */
`define READ_REG        2 /* Read one of Coprocessor0 registers mfc0, lwc0 */
`define WRITE_REG       3 /* Write to Coprocessor0 Registers */
 
/* Clock definitions */
`define SYSCLK    50000000 //25MHz
`define MS_LIMIT  `SYSCLK / 1000 // 1MS counter limit
 
module Coprocessor0
#
(
  parameter N=32,
  parameter M=5
)
(
  input clk,
  input [N-1:0] EPC,
  input [N-1:0] Cause,
  input [1:0] instruction,
  input [M-1:0] ra, /* Read address */
  input [M-1:0] wa, /* Write address */
  input [N-1:0] WriteData,
  input IO_TimerIntReset, /* reset timer from software */
 
  output[N-1:0] ReadData,
  output TimerIntMatch
);
 
/********* Coprocessor0 currently supported registers *******
* 0
* 1
* 2
* 3
* 4
* 5
* 6
* 7
* 8
* 9     Counter
* 10
* 11    Compare
* 12    Status
* 13    Cause
* 14    EPC
* 15
* 16
* 17
* 18
* 19
* 20
* 21
* 22
*************************************************************/
reg[N-1:0] rf [(2**M)-1:0];
 
reg TimerMatch = 0; /* Count = Compare */
 
assign TimerIntMatch = TimerMatch;
 
reg[31:0] ClockCycleCount = 0;
reg[63:0] Counter = 0;
integer i = 0;
 
initial
begin
  for(i=0; i<32; i=i+1)
    rf[i] = 0;
end
 
always @(posedge clk)
begin
 
 
        case (instruction)
    `EXCEPTION:
    begin
      rf[13] = Cause;
      rf[14] = EPC;
    end
    `WRITE_REG:
      rf[wa] = WriteData;
   endcase
 
  /* Timer operations */
    Counter = Counter + 1;
 
    if(Counter == `MS_LIMIT) // 1MS passed
    begin
      rf[9] = rf[9] + 1;
      Counter = 0;
    end
 
    if(rf[9] == rf[11])
      TimerMatch = 1;
 
    if(IO_TimerIntReset)
    begin
      rf[9] = 0;
      TimerMatch = 0;
      Counter = 0;
    end
  /* Timer operation */
 
end
 
assign ReadData = rf[ra];
 
endmodule

Line No.	Rev	Author	Line
1	2	heshamelma	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Coprocessor0 for Edge core //`
4			`// //`
5			`// This file is part of the Edge project //`
6			`// http://www.opencores.org/project,edge //`
7			`// //`
8			`// Description //`
9			`// Coprocessor0 in MIPS is the control unit mainly respobsible //`
10			`// for handling interrupts. //`
11			`// //`
12			`// Author(s): //`
13			`// - Hesham AL-Matary, heshamelmatary@gmail.com //`
14			`// //`
15			`//////////////////////////////////////////////////////////////////`
16			`// //`
17			`// Copyright (C) 2014 Authors and OPENCORES.ORG //`
18			`// //`
19			`// This source file may be used and distributed without //`
20			`// restriction provided that this copyright statement is not //`
21			`// removed from the file and that any derivative work contains //`
22			`// the original copyright notice and the associated disclaimer. //`
23			`// //`
24			`// This source file is free software; you can redistribute it //`
25			`// and/or modify it under the terms of the GNU Lesser General //`
26			`// Public License as published by the Free Software Foundation; //`
27			`// either version 2.1 of the License, or (at your option) any //`
28			`// later version. //`
29			`// //`
30			`// This source is distributed in the hope that it will be //`
31			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
32			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
33			`// PURPOSE. See the GNU Lesser General Public License for more //`
34			`// details. //`
35			`// //`
36			`// You should have received a copy of the GNU Lesser General //`
37			`// Public License along with this source; if not, download it //`
38			`// from http://www.opencores.org/lgpl.shtml //`
39			`// //`
40			`//////////////////////////////////////////////////////////////////`
41
42			`/* Coprocessor 0 instructions definitions */`
43			`define EXCEPTION 1 /* Take exception, save EPC and Cause */
44			`define READ_REG 2 /* Read one of Coprocessor0 registers mfc0, lwc0 */
45			`define WRITE_REG 3 /* Write to Coprocessor0 Registers */
46
47			`/* Clock definitions */`
48			`define SYSCLK 50000000 //25MHz
49			`define MS_LIMIT `SYSCLK / 1000 // 1MS counter limit
50
51			`module Coprocessor0`
52			`#`
53			`(`
54			`parameter N=32,`
55			`parameter M=5`
56			`)`
57			`(`
58			`input clk,`
59			`input [N-1:0] EPC,`
60			`input [N-1:0] Cause,`
61			`input [1:0] instruction,`
62			`input [M-1:0] ra, /* Read address */`
63			`input [M-1:0] wa, /* Write address */`
64			`input [N-1:0] WriteData,`
65			`input IO_TimerIntReset, /* reset timer from software */`
66
67			`output[N-1:0] ReadData,`
68			`output TimerIntMatch`
69			`);`
70
71			`/******* Coprocessor0 currently supported registers *****`
72			`* 0`
73			`* 1`
74			`* 2`
75			`* 3`
76			`* 4`
77			`* 5`
78			`* 6`
79			`* 7`
80			`* 8`
81			`* 9 Counter`
82			`* 10`
83			`* 11 Compare`
84			`* 12 Status`
85			`* 13 Cause`
86			`* 14 EPC`
87			`* 15`
88			`* 16`
89			`* 17`
90			`* 18`
91			`* 19`
92			`* 20`
93			`* 21`
94			`* 22`
95			`*************************************************************/`
96			`reg[N-1:0] rf [(2**M)-1:0];`
97
98			`reg TimerMatch = 0; /* Count = Compare */`
99
100			`assign TimerIntMatch = TimerMatch;`
101
102			`reg[31:0] ClockCycleCount = 0;`
103			`reg[63:0] Counter = 0;`
104			`integer i = 0;`
105
106			`initial`
107			`begin`
108			`for(i=0; i<32; i=i+1)`
109			`rf[i] = 0;`
110			`end`
111
112			`always @(posedge clk)`
113			`begin`
114
115
116			`case (instruction)`
117			`EXCEPTION:
118			`begin`
119			`rf[13] = Cause;`
120			`rf[14] = EPC;`
121			`end`
122			`WRITE_REG:
123			`rf[wa] = WriteData;`
124			`endcase`
125
126			`/* Timer operations */`
127			`Counter = Counter + 1;`
128
129			if(Counter == `MS_LIMIT) // 1MS passed
130			`begin`
131			`rf[9] = rf[9] + 1;`
132			`Counter = 0;`
133			`end`
134
135			`if(rf[9] == rf[11])`
136			`TimerMatch = 1;`
137
138			`if(IO_TimerIntReset)`
139			`begin`
140			`rf[9] = 0;`
141			`TimerMatch = 0;`
142			`Counter = 0;`
143			`end`
144			`/* Timer operation */`
145
146			`end`
147
148			`assign ReadData = rf[ra];`
149
150			`endmodule`

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[/] [edge/] [trunk/] [HW/] [Verilog/] [Coprocessor0.v] - Blame information for rev 2