| 1 |
2 |
heshamelma |
//////////////////////////////////////////////////////////////////
|
| 2 |
|
|
// //
|
| 3 |
|
|
// Arithmetic and logic unit (ALU) for Edge core //
|
| 4 |
|
|
// //
|
| 5 |
|
|
// This file is part of the Edge project //
|
| 6 |
|
|
// http://www.opencores.org/project,edge //
|
| 7 |
|
|
// //
|
| 8 |
|
|
// Description //
|
| 9 |
|
|
// ALU supports add, sub, and, or and mul functions. //
|
| 10 |
|
|
// Also it outputs zero and sign flags. //
|
| 11 |
|
|
// //
|
| 12 |
|
|
// Author(s): //
|
| 13 |
|
|
// - Hesham AL-Matary, heshamelmatary@gmail.com //
|
| 14 |
|
|
// //
|
| 15 |
|
|
//////////////////////////////////////////////////////////////////
|
| 16 |
|
|
// //
|
| 17 |
|
|
// Copyright (C) 2014 Authors and OPENCORES.ORG //
|
| 18 |
|
|
// //
|
| 19 |
|
|
// This source file may be used and distributed without //
|
| 20 |
|
|
// restriction provided that this copyright statement is not //
|
| 21 |
|
|
// removed from the file and that any derivative work contains //
|
| 22 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 23 |
|
|
// //
|
| 24 |
|
|
// This source file is free software; you can redistribute it //
|
| 25 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 26 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 27 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 28 |
|
|
// later version. //
|
| 29 |
|
|
// //
|
| 30 |
|
|
// This source is distributed in the hope that it will be //
|
| 31 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 32 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 33 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 34 |
|
|
// details. //
|
| 35 |
|
|
// //
|
| 36 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 37 |
|
|
// Public License along with this source; if not, download it //
|
| 38 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 39 |
|
|
// //
|
| 40 |
|
|
//////////////////////////////////////////////////////////////////
|
| 41 |
|
|
|
| 42 |
|
|
module alu
|
| 43 |
|
|
#
|
| 44 |
|
|
(
|
| 45 |
|
|
parameter N=32
|
| 46 |
|
|
)
|
| 47 |
|
|
(
|
| 48 |
|
|
input [N-1:0] a, b,
|
| 49 |
|
|
input [3:0] f,
|
| 50 |
|
|
output reg[N-1:0] y,
|
| 51 |
|
|
output zero,
|
| 52 |
|
|
output sign
|
| 53 |
|
|
);
|
| 54 |
|
|
|
| 55 |
|
|
wire [N-1:0] b_mux2_out;
|
| 56 |
|
|
wire [N-1:0] adder_out, tmp;
|
| 57 |
|
|
wire cout;
|
| 58 |
|
|
|
| 59 |
|
|
// first level mux
|
| 60 |
|
|
mux2 mux2_out(b, ~b, f[2], b_mux2_out);
|
| 61 |
|
|
|
| 62 |
|
|
// Adder output
|
| 63 |
|
|
adder adder(a, b_mux2_out, f[2], cout, adder_out);
|
| 64 |
|
|
|
| 65 |
|
|
always @*
|
| 66 |
|
|
begin
|
| 67 |
|
|
if(f[3] == 0)
|
| 68 |
|
|
begin
|
| 69 |
|
|
case(f[1:0])
|
| 70 |
|
|
0: y = a & b_mux2_out;
|
| 71 |
|
|
1: y = a | b_mux2_out;
|
| 72 |
|
|
2: y = adder_out;
|
| 73 |
|
|
3: y = f[2] ? ((adder_out[N-1] == 1'b1) ? 1 : 0) :
|
| 74 |
|
|
(a ^ b_mux2_out);
|
| 75 |
|
|
default : y = 0;
|
| 76 |
|
|
endcase
|
| 77 |
|
|
end
|
| 78 |
|
|
else // f[3] == 1
|
| 79 |
|
|
begin
|
| 80 |
|
|
case(f[2:0])
|
| 81 |
|
|
3'b000: y = a * b;
|
| 82 |
|
|
default : y = 0;
|
| 83 |
|
|
endcase
|
| 84 |
|
|
end
|
| 85 |
|
|
end
|
| 86 |
|
|
|
| 87 |
|
|
assign zero = (y == 0) ? 1'b1:1'b0;
|
| 88 |
|
|
assign sign = y[N-1];
|
| 89 |
|
|
|
| 90 |
|
|
endmodule
|
| 91 |
|
|
|
