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heshamelma |
//////////////////////////////////////////////////////////////////
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// //
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// Clock manager for Edge core //
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// //
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// This file is part of the Edge project //
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// http://www.opencores.org/project,edge //
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// //
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// Description //
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// The clock manager depends on counter concept to output the //
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// desired clock frequency. //
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// //
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// Author(s): //
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// - Hesham AL-Matary, heshamelmatary@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2014 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module clock_manager
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#
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(
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parameter SYSCLK = 100000000, // 100 MHz for atlys board
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parameter CLK_OUT = 100000000, // desizred clock output
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parameter DIV=1,
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parameter MUL=1
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)
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(
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input clk_in,
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output clk_out
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);
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reg[31:0] counter = 0;
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reg clk_buffer = 0;
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always @(posedge clk_in)
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begin
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if(counter == 32'd0)
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clk_buffer = ~clk_buffer;
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counter = counter + 1;
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if (counter == (SYSCLK/CLK_OUT)/2)
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counter = 31'd0;
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end
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assign clk_out = clk_buffer;
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endmodule
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