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//////////////////////////////////////////////////////////////////

//                                                              //

//  Edge core                                                   //

//                                                              //

//  This file is part of the Edge project                       //

//  http://www.opencores.org/project,edge                       //

//                                                              //

//  Description                                                 //

//  The main top module for Edge core. It contains the whole    //

//  data path and pipeline stuff.

//                                                              //

//  Author(s):                                                  //

//      - Hesham AL-Matary, heshamelmatary@gmail.com            //

//                                                              //

//////////////////////////////////////////////////////////////////

//                                                              //

// Copyright (C) 2014 Authors and OPENCORES.ORG                 //

//                                                              //

// This source file may be used and distributed without         //

// restriction provided that this copyright statement is not    //

// removed from the file and that any derivative work contains  //

// the original copyright notice and the associated disclaimer. //

//                                                              //

// This source file is free software; you can redistribute it   //

// and/or modify it under the terms of the GNU Lesser General   //

// Public License as published by the Free Software Foundation; //

// either version 2.1 of the License, or (at your option) any   //

// later version.                                               //

//                                                              //

// This source is distributed in the hope that it will be       //

// useful, but WITHOUT ANY WARRANTY; without even the implied   //

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //

// PURPOSE.  See the GNU Lesser General Public License for more //

// details.                                                     //

//                                                              //

// You should have received a copy of the GNU Lesser General    //

// Public License along with this source; if not, download it   //

// from http://www.opencores.org/lgpl.shtml                     //

//                                                              //

//////////////////////////////////////////////////////////////////

`define BLTZ_OPCODE     6'b000001 // 1

`define BGEZ_OPCODE     6'b000001 // 1

`define JMP_OPCODE      6'b000010 // 2

`define JAL_OPCODE      6'b000011 // 3

`define BEQ_OPCODE      6'b000100 // 4

`define BNE_OPCODE      6'b000101 // 5

`define BLEZ_OPCODE     6'b000110 // 6

`define BGTZ_OPCODE     6'b000111 // 7

module Edge_Core

#

(

  parameter N=32, M=5

)

(

  input clk,

  input reset,

  /* Instruction Memory */

  output[N-1:0] pc_toIMemory,

  input[N-1:0] instr_fromIMemory,

  /* Data Memory */

  output[N-1:0] Address_toDMemory,

  output[N-1:0] WriteData_toDMemory,

  output MemWrite_toDMemory, /* Write Enable signal to data memory */

  input[N-1:0] RD_fromDMemory, /* Data rereived from data memory */

  output[1:0] MemRefSize, /* Zero Byte, Half word, or Word reference */

  input StallDataMemory, // Stall signal from data memory (Technology dependent)

  /* Interrupts */

  output CP0_TimerIntMatch,

  input IO_TimerIntReset

);

/******************************* PC Wires **************************************

*

*

*

*******************************************************************************/

wire pc_en;

wire PC_STALL_HAZARD;

wire[N-1:0] pc_current;

wire[N-1:0] pc_next;

wire[2:0] PCSrcM; /* PC src signal (from PCplus4 or from branch) */

wire PC_RESET;

wire PC_RESET_HAZARD;

/******************************* IF/ID Wires ***********************************

*

*

*

*******************************************************************************/

wire IF_ID_EN;

wire IF_ID_EN_GLOBAL;

wire IF_ID_STALL_HAZARD;

wire IF_ID_RESET; /* Final reset value */

wire IF_ID_RESET_GLOBAL; /* Blobal reset from the processor */

wire IF_ID_RESET_HAZARD; /* Reset due to hazard unit (flush) */

wire IF_ID_RESET_INT; /* Reset due to interrupt taken */

reg IF_ID_RESET_FINAL;

wire[N-1:0] IR_in;

wire[N-1:0] IR_out;

wire[N-1:0] PCplus4F;

/* Coprocessor0 and exceptions signals */

wire undefinedExD;

wire breakExD;

wire divbyZeroExD;

wire syscallExD;

wire[M-1:0] CP0_waD;

wire[M-1:0] CP0_raD;

wire[1:0] CP0_InstD;

wire[N-1:0] CP0_doutD;

wire[N-1:0] CP0_dinD;

wire mfc0D; /* Signal to MUX to choose register value from Coprocessor 0 */

wire[M-1:0] ra1D;

wire[1:0] MemRefSizeD;

/******************************** ID/EX Wires **********************************

*

*

*******************************************************************************/

wire ID_EX_EN;

wire ID_EX_RESET;

wire ID_EX_RESET_GLOBAL;

wire ID_EX_RESET_HAZARD;

wire ID_EX_RESET_INT;

wire ID_EX_RESET_FINAL;

wire ID_EX_STALL_HAZARD;

wire[M-1:0] read_reg1_in;

wire[M-1:0] read_reg2_in;

wire[M-1:0] write_reg1_in;

wire[N-1:0] read_value1_in;

wire[N-1:0] read_value2_in;

wire[M-1:0] Rt_in;

wire[M-1:0] Rd_in;

wire[N-1:0] SignImm_in;

wire[N-1:0] PCplus4D;

wire linkD;

wire RegWriteD;

wire[1:0] WBResultSelectD;

wire MemWriteD;

wire BranchD;

wire JumpD;

wire JumpRD;

wire[3:0] ALUControlD;

wire ALUSrcBD;

wire RegDstD;

wire ALUCompD;

wire[1:0] Shift_typeD;

wire ShiftAmtVarD;

wire Shifter_or_ALUD;

wire[1:0] MulDivRFD; /* Control Signal input to mux to choose between mul, div,

rf wires */

wire hiEND, loEND; /* Enable load signal for lo and hi registers */

wire [5:0] opcodeD;

wire[N-1:0] IR_D;

wire[N-1:0] PC_D;

wire isExW;

wire[N-1:0] rd2D; /* input of value2 to ID/EX register */

wire[M-1:0] read_reg1_out;

wire[M-1:0] read_reg2_out;

wire[M-1:0] write_reg1_out;

wire[N-1:0] read_value1_out;

wire[N-1:0] read_value2_out;

wire[M-1:0] Rs_out;

wire[M-1:0] Rt_out;

wire[M-1:0] Rd_out;

wire[N-1:0] SignImm_out;

/******************************* EX/MEM Wires **********************************

*

*

*******************************************************************************/

wire EX_MEM_EN;

wire EX_MEM_RESET;

wire EX_MEM_RESET_GLOBAL;

wire EX_MEM_RESET_INT;

wire EX_MEM_STALL_HAZARD;

wire[N-1:0] ALUoutE;

wire[N-1:0] PCBranchE;

wire[M-1:0] WriteRegE;

wire RegWriteE;

wire[1:0] WBResultSelectE;

wire MemWriteE;

wire BranchE;

wire JumpE;

wire JumpRE;

wire[3:0] ALUControlE;

wire ALUSrcBE;

wire RegDstE;

wire[N-1:0] SrcAE;

wire[N-1:0] SrcBE;

wire[N-1:0] IR_E;

wire[1:0] ForwardAE, ForwardBE; /* Forward signals coming from hazard unit */

wire[N-1:0] mux_ForwardDataAE, mux_ForwardDataBE;

wire[N-1:0] ALUoutEE;

wire UpperImmD;

wire UpperImmE;

wire ALUCompE;

wire[1:0] Shift_typeE;

wire ShiftAmtVarE;

wire Shifter_or_ALUE;

wire[N-1:0] Shift_ResultE;

wire[N-1:0] EX_Result;

wire[1:0] MulDivRFE; /* Control Signal input to mux to choose between mul, div,

rf wires */

wire hiENE, loENE; /* Enable load signal for lo and hi registers */

wire [5:0] opcodeE;

wire [N-1:0] JTA_E; /* Jump target address */

wire linkE;

wire[N-1:0] PCplus4E;

wire[1:0] MemRefSizeE;

wire zeroE;

wire SignE;

/* Coprocessor0 and exceptions signals */

wire undefinedExE;

wire breakExE;

wire divbyZeroExE;

wire syscallExE;

wire[M-1:0] CP0_waE;

wire[M-1:0] CP0_raE;

wire[1:0] CP0_InstE;

wire[N-1:0] CP0_doutE;

wire[N-1:0] CP0_dinE;

wire[N-1:0] shifted_imm_2;

wire[N-1:0] ALUoutCompE;

wire[4:0] ShiftAmtE;

/* Output wires from Mul/Div units */

wire[N-1:0] hiIn, loIn, hiE, loE;

wire[N-1:0] hiMulE, loMulE, hiDivE, loDivE;

/********************************** MEM/WB Wires *******************************

*

*

*******************************************************************************/

wire zeroM;

wire SignM;

wire[N-1:0] ALUoutM;

wire[N-1:0] WriteDataM;

wire[N-1:0] PCBranchM;

wire[M-1:0] WriteRegM;

wire RegWriteM;

wire[1:0] WBResultSelectM;

wire MemWriteM;

wire BranchM;

wire JumpM;

wire JumpRM;

wire[N-1:0] ReadDataM;

wire[N-1:0] hiM, loM;

wire [5:0] opcodeM;

wire [N-1:0] JTA_M; /* Jump target address */

wire[N-1:0] PCplus4M;

wire linkM;

/* Coprocessor0 and exceptions signals */

wire undefinedExM;

wire breakExM;

wire divbyZeroM;

wire syscallExM;

wire[M-1:0] CP0_waM;

wire[M-1:0] CP0_raM;

wire[1:0] CP0_InstM;

wire[N-1:0] CP0_doutM;

wire[N-1:0] CP0_dinM;

wire[1:0] MemRefSizeM;

/****************************** WB Wires ***************************************

*

*

*******************************************************************************/

wire MEM_WB_EN;

wire MEM_WB_STALL_HAZARD;

wire[N-1:0] ReadDataW;

wire[N-1:0] ALUoutW;

wire[M-1:0] WriteRegW;

wire RegWriteW;

wire[1:0] WBResultSelectW;

wire[N-1:0] hiW, loW;

wire[N-1:0] PCplus4W;

wire[N-1:0] ResultW; /* Result to be written in RF */

wire linkW;

wire[N-1:0] ResultWWW;

wire[M-1:0] WriteRegWW;

/* Coprocessor0 and exceptions signals */

wire undefinedExW;

wire breakExW;

wire divbyZeroExW;

wire syscallExW;

wire[M-1:0] CP0_waW;

wire[M-1:0] CP0_raW;

wire[1:0] CP0_InstW;

wire[N-1:0] CP0_doutW;

wire[N-1:0] CP0_dinW;

wire[N-1:0] ImmSigned, ImmUSigned;

wire ImmSorU;

/* output of the 3-way mux (lw, lb, lh) */

wire[N-1:0] ResultWW, ResultSHW, ResultSB, ResultUHW, ResultUB;

/* Selection bits for ResultWW mux (comes from decoder) */

wire[2:0] bhwD, bhwE, bhwM, bhwW;

/****************************** Coprocessor0 Wires *****************************

*

*

*******************************************************************************/

wire[1:0] CP0_Inst;

wire[N-1:0] CP0_Cause;

wire[N-1:0] CP0_EPC;

wire[M-1:0] CP0_wa, CP0_ra;

wire[N-1:0] CP0_wd;

wire[N-1:0] CP0_rd;

wire[N-1:0] PC_W;

wire CP0_TimerIntMatch;

/****************************** Data path **************************************

*

*

*******************************************************************************/

/* Hazard Control Unit */

hazard_unit hazard_unit

(

  .CLK(clk),

  .rsE(Rs_out), .rtE(Rt_out),

  .rsD(IR_out[25:21]), .rtD(IR_out[20:16]),

  .DestRegE(WriteRegE),

  .DestRegM(WriteRegM), .DestRegW(WriteRegWW),

  .RegWriteE(RegWriteE),

  .RegWriteM(RegWriteM), .RegWriteW(RegWriteW),

  .loadE((WBResultSelectE)== 2'b01),

  .PCSrcM(PCSrcM),

  .MemWriteD(MemWriteD),

  .MemWriteE(MemWriteE),

  .StallF(PC_STALL_HAZARD),

  .StallD(IF_ID_STALL_HAZARD),

  .StallE(ID_EX_STALL_HAZARD),

  .StallM(EX_MEM_STALL_HAZARD),

  .StallW(MEM_WB_STALL_HAZARD),

  .FlushF(PC_RESET_HAZARD),

  .FlushD(IF_ID_RESET_HAZARD),

  .FlushE(ID_EX_RESET_HAZARD),

  .FlushM(EX_MEM_RESET_HAZARD),

  .ForwardAE(ForwardAE),

  .ForwardBE(ForwardBE),

  .StallDataMemory(StallDataMemory)

);

assign pc_en = (PCSrcM == 3'b000)?

                ((~PC_STALL_HAZARD) & (~StallDataMemory))

                :

                1'b1 ;

assign IF_ID_RESET_GLOBAL = reset;

assign IF_ID_RESET_INT = 1'b0;

assign ID_EX_RESET_GLOBAL = reset;

assign ID_EX_RESET_INT = 1'b0;

assign EX_MEM_RESET_GLOBAL = reset;

assign EX_MEM_RESET_INT = 1'b0;

assign IF_ID_EN = (~IF_ID_STALL_HAZARD) & (~StallDataMemory);

assign ID_EX_EN = (~ID_EX_STALL_HAZARD) & (~StallDataMemory);

assign EX_MEM_EN = /*(~EX_MEM_STALL_HAZARD) &*/ (~StallDataMemory);

assign MEM_WB_EN = /*(~MEM_WB_STALL_HAZARD)*/ 1'b1;

assign PC_RESET = (reset);

assign IF_ID_RESET =

  (IF_ID_RESET_GLOBAL |

   IF_ID_RESET_HAZARD |

   IF_ID_RESET_INT

  ) ?

    1'b1

  :

    1'b0;

assign ID_EX_RESET =

  (ID_EX_RESET_GLOBAL |

   ID_EX_RESET_HAZARD |

   ID_EX_RESET_INT

   ) ?

    1'b1

   :

    1'b0;

assign EX_MEM_RESET =

  (EX_MEM_RESET_GLOBAL |

   EX_MEM_RESET_HAZARD |

   EX_MEM_RESET_INT

   ) ?

    1'b1

   :

    1'b0;

assign MemRefSize = MemRefSizeM;

assign PC_W = PCplus4W - 4;

/* Excepetion detection and CP0 interaction */

assign isExW =

  (undefinedExW ||

   breakExW     ||

   divbyZeroExW ||

   syscallExW

   ) ?

    1'b1

   :

    1'b0;

assign CP0_Cause =

  (undefinedExW) ?

    32'h00000028

  :

    (breakExW | divbyZeroExW)?

      32'h00000024

    :

      (syscallExW)  ?

        32'h00000020

      :

        32'h00000000;

assign CP0_EPC = PC_W;

assign CP0_Inst = (isExW)? 2'd1 : CP0_InstW;

assign CP0_ra = IR_out[15:11];

assign CP0_waD = IR_out[15:11];

assign CP0_wa = CP0_waW;

assign CP0_InstD = (mtc0D)? 2'd3 : 2'd0;

assign CP0_din = CP0_dinW;

assign CP0_dinW = ResultWWW;

/* Coprocessor 0 */

Coprocessor0 cp0

(

  .clk(clk),

  .EPC(CP0_EPC),

  .Cause(CP0_Cause),

  .instruction(CP0_Inst),

  .ra(CP0_ra),

  .wa(CP0_wa),

  .WriteData(CP0_dinW),

  .IO_TimerIntReset(IO_TimerIntReset),

  .ReadData(CP0_rd),

  .TimerIntMatch(CP0_TimerIntMatch)

);

/* Mux signal to determine PC source at from memory pipleline stage */

assign PCSrcM =

  ((BranchM == 1'b0 && JumpM == 1'b0 && JumpRM == 1'b0)?

      ((isExW)? 3'b100 : 3'b000) /* Check for excpetions */

    : /* not a branch or jump */

      ((JumpM) ?

      /* Jump type */

        3'b010

      :

        ((JumpRM) ?

        /* Jump Register */

          3'b011

        :

          ((BranchM) ?

          /* Branch type */

            ((opcodeM == `BLTZ_OPCODE && SignM)?

            ((Rt_out == 5'd0)? 3'b001 : 3'b000) :

            (opcodeE == `BGEZ_OPCODE && SignM == 1'b0)?

            ((Rt_out == 5'd1)? 3'b001 : 3'b000) :

            (opcodeM == `BEQ_OPCODE && zeroM)? 3'b001 :

            (opcodeM == `BNE_OPCODE && zeroM == 1'b0)? 3'b001 :

            (opcodeM == `BLEZ_OPCODE && (SignM == 1 || zeroM == 0))? 3'b001 :

            (opcodeM == `BGTZ_OPCODE && SignM == 0 && zeroM == 0)? 3'b001 :

            3'b000)

            :3'b000))));

assign pc_next =

  (reset == 1)? 32'd0          :

  (PCSrcM === 0)? PCplus4F     :

  (PCSrcM === 1)? PCBranchM    :

  (PCSrcM === 2)? JTA_M        :

  (PCSrcM === 3)? ALUoutM      :

  (PCSrcM === 4)? 32'h80000180 : PCplus4F;

assign pc_toIMemory = pc_current;

/* PC + 4 adder at fetch pipeline stage */

adder pcplus4

(

  .in1(pc_current),

  .in2(32'd4),

  .cin(1'b0),

  .out(PCplus4F)

);

/****************************** PC Register ************************************

*

*

*******************************************************************************/

register pc

(

  .clk(clk),

  .reset(PC_RESET),

  .en(pc_en),

  .d(pc_next),

  .q(pc_current)

);

/****************************** IF/ID Register *********************************

*

*

*******************************************************************************/

if_id_pipereg IF_ID_REG

(

  .clk(clk),

  .reset(IF_ID_RESET),

  .en(IF_ID_EN),

  .IR_in(instr_fromIMemory),

  .IR_out(IR_out),

  .PCplus4_in(PCplus4F),

  .PCplus4_out(PCplus4D),

  .PC_in(pc_current),

  .PC_out(PC_D)

);

/* Decode or controller */

controller ctrl

(

  .opcode(IR_out[31:26]),

  .func(IR_out[5:0]),

  .Instruction(IR_out),

  .RegWrite(RegWriteD),

  .WBResultSelect(WBResultSelectD),

  .MemWrite(MemWriteD),

  .Branch(BranchD),

  .Jump(JumpD),

  .JumpR(JumpRD),

  .ALUControl(ALUControlD),

  .ALUSrcB(ALUSrcBD),

  .RegDst(RegDstD),

  .UpperImm_out(UpperImmD),

  .BHW(bhwD),

  .ImmSorU_out(ImmSorU),

  .ALUComp_out(ALUCompD),

  .ShiftAmtVar_out(ShiftAmtVarD),

  .Shift_type_out(Shift_typeD),

  .Shifter_or_ALU_out(Shifter_or_ALUD),

  .MulDivRF(MulDivRFD),

  .hiEN(hiEND),

  .loEN(loEND),

  .link(linkD),

  .undefinedEx(undefinedExD),

  .syscallEx(syscallExD),

  .breakEx(breakExD),

  .mfc0(mfc0D),

  .mtc0(mtc0D),

  .MemRefSize(MemRefSizeD)

);

/* Check divide by Zero Exception */

assign divbyZeroExD =

  (IR_out[31:26] == 0 &&

  (IR_out[5:0] == 26  || IR_out[5:0] == 27)

  ) ?

    1'b1

  :

    1'b0;

/* mux to choose between lb, lh and lw signed extended */

sign_extend #(32, 8)

s_extend_byte

(

  .in(ResultW[7:0]),

  .out(ResultSB)

);

sign_extend #(32, 16)

s_extend_halfWord

(

  .in(ResultW[15:0]),

  .out(ResultSHW)

);

/* zero extend for lbu, lhu */

zero_extend #(32, 8)

z_extend_byte

(

  .in(ResultW[7:0]),

  .out(ResultUB)

);

zero_extend #(32, 16)

z_extend_halfWord

(

.in(ResultW[15:0]),

.out(ResultUHW)

);

/* bhw -> [S|U] byte or halfword or word */

mux_WBResult WBResult

(

  .Word(ResultW),

  .SByte(ResultSB),

  .SHWord(ResultSHW),

  .UByte(ResultUB),

  .UHWord(ResultUHW),

  .s(bhwW),

  .WBResult(ResultWW)

);

assign WriteRegWW = (linkW)? 5'd31 : WriteRegW;

assign ResultWWW = (linkW)? PCplus4W : ResultWW;

/* Workaroud for mtc0 instruction */

assign ra1D = (mtc0D)? 5'd0 : IR_out[25:21];