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heshamelma |
//////////////////////////////////////////////////////////////////
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// //
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// IF/ID pipeline register //
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// //
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// This file is part of the Edge project //
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// http://www.opencores.org/project,edge //
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// //
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// Description //
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// Pipeline register lies between fetch and decode stages //
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// //
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// Author(s): //
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// - Hesham AL-Matary, heshamelmatary@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2014 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module if_id_pipereg
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#
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(
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parameter N=32, /* most registers sizes */
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parameter M=5
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) /* regfile address */
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(
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input clk,
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input reset,
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input en,
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input [N-1:0] IR_in,
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input [N-1:0] PCplus4_in,
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input [N-1:0] PC_in,
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output [N-1:0] IR_out,
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output [N-1:0] PC_out,
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output [N-1:0] PCplus4_out
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);
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register IR
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(
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.clk(clk), .reset(reset), .en(en),
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.d(IR_in),
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.q(IR_out)
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);
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register PC_4
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(
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.clk(clk), .reset(reset), .en(en),
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.d(PCplus4_in),
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.q(PCplus4_out)
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);
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register PC
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(
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.clk(clk), .reset(reset), .en(en),
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.d(PC_in),
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.q(PC_out)
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);
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endmodule
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