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[/] [edge/] [trunk/] [HW/] [Verilog/] [shift_unit.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////
//                                                              //
//  Shift unit for Edge core                                    //       
//                                                              //
//  This file is part of the Edge project                       //
//  http://www.opencores.org/project,edge                       //
//                                                              //
//  Description                                                 //
//  Shift unit handling different types of shifts : right, left,//
//  arithmetic and logical.                                     //
//                                                              //
//  Author(s):                                                  //
//      - Hesham AL-Matary, heshamelmatary@gmail.com            //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2014 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
`define SLL             2'b00
`define SRL     2'b01
`define SRA             2'b10
 
module shift_unit
#(parameter N=32)
(
  input[N-1:0] in,
  input[4:0] shamt,
  input[1:0] shift_type,
 
  output reg[N-1:0] out
);
 
wire[N-1:0] sl_result, srl_result, sra_result;
 
shifter_left sl
(
  .in(in),
  .shamt(shamt),
  .out(sl_result)
);
 
shifter_right_logical
srl
(
  .in(in),
  .shamt(shamt),
  .out(srl_result)
);
 
shifter_right_arithmetic sra
(
  .in(in),
  .shamt(shamt),
  .out(sra_result)
);
 
always @(*)
  case (shift_type)
    `SLL: out <= sl_result;
    `SRL: out <= srl_result;
    `SRA: out <= sra_result;
    default: out <= in;
  endcase
 
endmodule

Line No.	Rev	Author	Line
1	2	heshamelma	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Shift unit for Edge core //`
4			`// //`
5			`// This file is part of the Edge project //`
6			`// http://www.opencores.org/project,edge //`
7			`// //`
8			`// Description //`
9			`// Shift unit handling different types of shifts : right, left,//`
10			`// arithmetic and logical. //`
11			`// //`
12			`// Author(s): //`
13			`// - Hesham AL-Matary, heshamelmatary@gmail.com //`
14			`// //`
15			`//////////////////////////////////////////////////////////////////`
16			`// //`
17			`// Copyright (C) 2014 Authors and OPENCORES.ORG //`
18			`// //`
19			`// This source file may be used and distributed without //`
20			`// restriction provided that this copyright statement is not //`
21			`// removed from the file and that any derivative work contains //`
22			`// the original copyright notice and the associated disclaimer. //`
23			`// //`
24			`// This source file is free software; you can redistribute it //`
25			`// and/or modify it under the terms of the GNU Lesser General //`
26			`// Public License as published by the Free Software Foundation; //`
27			`// either version 2.1 of the License, or (at your option) any //`
28			`// later version. //`
29			`// //`
30			`// This source is distributed in the hope that it will be //`
31			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
32			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
33			`// PURPOSE. See the GNU Lesser General Public License for more //`
34			`// details. //`
35			`// //`
36			`// You should have received a copy of the GNU Lesser General //`
37			`// Public License along with this source; if not, download it //`
38			`// from http://www.opencores.org/lgpl.shtml //`
39			`// //`
40			`//////////////////////////////////////////////////////////////////`
41
42			`define SLL 2'b00
43			`define SRL 2'b01
44			`define SRA 2'b10
45
46			`module shift_unit`
47			`#(parameter N=32)`
48			`(`
49			`input[N-1:0] in,`
50			`input[4:0] shamt,`
51			`input[1:0] shift_type,`
52
53			`output reg[N-1:0] out`
54			`);`
55
56			`wire[N-1:0] sl_result, srl_result, sra_result;`
57
58			`shifter_left sl`
59			`(`
60			`.in(in),`
61			`.shamt(shamt),`
62			`.out(sl_result)`
63			`);`
64
65			`shifter_right_logical`
66			`srl`
67			`(`
68			`.in(in),`
69			`.shamt(shamt),`
70			`.out(srl_result)`
71			`);`
72
73			`shifter_right_arithmetic sra`
74			`(`
75			`.in(in),`
76			`.shamt(shamt),`
77			`.out(sra_result)`
78			`);`
79
80			`always @(*)`
81			`case (shift_type)`
82			`SLL: out <= sl_result;
83			`SRL: out <= srl_result;
84			`SRA: out <= sra_result;
85			`default: out <= in;`
86			`endcase`
87
88			`endmodule`

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[/] [edge/] [trunk/] [HW/] [Verilog/] [shift_unit.v] - Blame information for rev 2