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[/] [epc_rfid_transponder/] [trunk/] [memctrl.vhd] - Blame information for rev 3

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-------------------------------------------------------------------------------
--     Politecnico di Torino                                              
--     Dipartimento di Automatica e Informatica             
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------     
--
--     Title          : Memory Controller
--
--     File name      : MemCtrl.vhd 
--
--     Description    : Flash memory controller.  
--
--     Authors        : Erwing Sanchez <erwing.sanchez@polito.it>
--                             
-------------------------------------------------------------------------------            
-------------------------------------------------------------------------------
--      EPC Memory Map
--
--               _______________________  
--              |                       | RESERVED MEMORY (Bank 00)
--              |                       |
--              |_______________________|
--              |                       | EPC MEMORY (Bank 01)
--              |                       |
--              |_______________________|
--              |                       | TID MEMORY (Bank 10)
--              |                       |
--              |_______________________|
--              |                       | USER MEMORY (Bank 11)
--              |                       |
--              |_______________________|
--
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
 
 
entity Mem_ctrl is
  generic (
    WordsRSV :     integer := 8;
    WordsEPC :     integer := 16;
    WordsTID :     integer := 8;
    WordsUSR :     integer := 256;
    --Address are loaded in two steps, so only half of address pins are needed.
    AddrRSV  :     integer := 2;        -- 1/2address pins 
    AddrEPC  :     integer := 3;        -- 1/2address pins
    AddrTID  :     integer := 2;        -- 1/2address pins
    AddrUSR  :     integer := 5;        -- 1/2address pins    
    Data     :     integer := 16);
  port (
    clk      : in  std_logic;
    rst_n    : in  std_logic;
    BANK     : in  std_logic_vector(1 downto 0);
    WR       : in  std_logic;           -- Write signal
    RD       : in  std_logic;           -- Read signal
    ADR      : in  std_logic_vector((2*AddrUSR)-1 downto 0);
    DTI      : in  std_logic_vector(Data-1 downto 0);
    DTO      : out std_logic_vector(Data-1 downto 0);
    RB       : out std_logic            -- Ready/nBusy signal(unbuffered!)
    );
end Mem_ctrl;
 
 
architecture Mem_Ctrl_arch of Mem_ctrl is
 
 
  component Flash_MeM_EPC
    generic (
      Words : integer;
      Addr  : integer;
      Data  : integer);
    port (
      A  : in  std_logic_vector(Addr-1 downto 0);
      D  : in  std_logic_vector(Data-1 downto 0);
      Q  : out std_logic_vector(Data-1 downto 0);
      G  : in  std_logic;
      W  : in  std_logic;
      RC : in  std_logic;
      st : out std_logic);
  end component;
 
  component Flash_MeM_TID
    generic (
      Words : integer;
      Addr  : integer;
      Data  : integer);
    port (
      A  : in  std_logic_vector(Addr-1 downto 0);
      D  : in  std_logic_vector(Data-1 downto 0);
      Q  : out std_logic_vector(Data-1 downto 0);
      G  : in  std_logic;
      W  : in  std_logic;
      RC : in  std_logic;
      st : out std_logic);
  end component;
 
  component Flash_MeM_USR
    generic (
      Words : integer;
      Addr  : integer;
      Data  : integer);
    port (
      A  : in  std_logic_vector(Addr-1 downto 0);
      D  : in  std_logic_vector(Data-1 downto 0);
      Q  : out std_logic_vector(Data-1 downto 0);
      G  : in  std_logic;
      W  : in  std_logic;
      RC : in  std_logic;
      st : out std_logic);
  end component;
 
  component Flash_MeM_RSV
    generic (
      Words : integer;
      Addr  : integer;
      Data  : integer);
    port (
      A  : in  std_logic_vector(Addr-1 downto 0);
      D  : in  std_logic_vector(Data-1 downto 0);
      Q  : out std_logic_vector(Data-1 downto 0);
      G  : in  std_logic;
      W  : in  std_logic;
      RC : in  std_logic;
      st : out std_logic);
  end component;
 
 
  -- Contants
  constant WriteCommand                   : std_logic_vector(Data-1 downto 0) := conv_std_logic_vector(64, Data);  --"01000000" Flash Write Code
  -- FSM
  type MemCtrl_t is (st_idle, st_read_LoadAddr1, st_read_LoadAddr2, st_read_LoadOutput, st_read_read, st_write_LoadAddr1, st_write_LoadAddr2, st_write_write);
  signal   StMCtrl, NextStMCtrl           : MemCtrl_t;
  -- Memory signals
  signal   A_RSV                          : std_logic_vector(AddrRSV-1 downto 0);
  signal   A_EPC                          : std_logic_vector(AddrEPC-1 downto 0);
  signal   A_TID                          : std_logic_vector(AddrTID-1 downto 0);
  signal   A_USR                          : std_logic_vector(AddrUSR-1 downto 0);
  signal   D                              : std_logic_vector(Data-1 downto 0);
  signal   Q                              : std_logic_vector(Data-1 downto 0);
  signal   G, G_i                         : std_logic;
  signal   W, W_i                         : std_logic;
  signal   RC, RC_i                       : std_logic;
  signal   st                             : std_logic;
  signal   W_RSV, W_EPC, W_TID, W_USR     : std_logic;
  signal   G_RSV, G_EPC, G_TID, G_USR     : std_logic;
  signal   Q_RSV, Q_EPC, Q_TID, Q_USR     : std_logic_vector(Data-1 downto 0);
  signal   RC_RSV, RC_EPC, RC_TID, RC_USR : std_logic;
  -- Internal regs
  signal   DTI_r                          : std_logic_vector(Data-1 downto 0);
  signal   DTO_r                          : std_logic_vector(Data-1 downto 0);
  signal   ADR_r                          : std_logic_vector((2*AddrUSR)-1 downto 0);
  signal   BNK_r                          : std_logic_vector(1 downto 0);
  signal   ADR_ce, DTI_ce, DTO_ce, BNK_ce : std_logic;
  -- Internal Flags & other signals
  signal   AddrMux                        : std_logic;
  signal   WRCmdFlag, WRCmdFlag_i         : std_logic;
 
begin  -- Mem_Ctrl_arch
 
 
  SYNC_MEMCTRL : process (clk, rst_n)
  begin  -- process SYNC
    if rst_n = '0' then                 -- asynchronous reset (active low)
      StMCtrl <= st_idle;
      RC      <= '1';                   -- 1 -> 0 : Load LSB address
      G       <= '1';                   -- 0: enable
      W       <= '0';
      WRCmdFlag <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      StMCtrl <= NextStMCtrl;
      RC      <= RC_i;
      G       <= G_i;
      W       <= W_i;
      WRCmdFlag <= WRCmdFlag_i;
    end if;
  end process SYNC_MEMCTRL;
 
  NEXTST_MEMCTRL : process (StMCtrl, WR, RD, ADR, DTI)
  begin  -- process NEXTST
 
    NextStMCtrl <= StMCtrl;
 
    case StMCtrl is
      when st_idle            =>
        if WR = '1' then
          NextStMCtrl <= st_write_LoadAddr1;
        elsif RD = '1' then
          NextStMCtrl <= st_read_LoadAddr1;
        end if;
      when st_read_LoadAddr1  =>
        NextStMCtrl   <= st_read_LoadAddr2;
      when st_read_LoadAddr2  =>
        NextStMCtrl   <= st_read_read;
      when st_read_read       =>
        NextStMCtrl   <= st_read_LoadOutput;
      when st_read_LoadOutput =>
        NextStMCtrl   <= st_idle;
 
      when st_write_LoadAddr1 =>
        NextStMCtrl <= st_write_LoadAddr2;
      when st_write_LoadAddr2 =>
        NextStMCtrl <= st_write_write;
      when st_write_write     =>
        NextStMCtrl <= st_idle;
 
      when others => null;
    end case;
 
  end process NEXTST_MEMCTRL;
 
 
  OUTPUT_MEMCTRL : process (StMCtrl, WR, RD)
  begin  -- process OUTPUT_MEMCTRL
 
    RB        <= '0';
    ADR_ce    <= '0';
    DTI_ce    <= '0';
    DTO_ce    <= '0';
    BNK_ce    <= '0';
    AddrMux   <= '0';
    WRCmdFlag_i <= '0';
    -- Memory signals
    RC_i      <= '1';
    G_i       <= '1';
    W_i       <= '0';
 
    case StMCtrl is
      when st_idle =>
        RB       <= '1';
        if WR = '1' then
          ADR_ce <= '1';                -- load address
          DTI_ce <= '1';                -- load data
          BNK_ce <= '1';                -- load Bank
          RB     <= '0';
        elsif RD = '1' then
          ADR_ce <= '1';                -- load address
          BNK_ce <= '1';                -- load Bank
          RB     <= '0';
        end if;
 
      when st_read_LoadAddr1 =>
        RC_i <= '0';                    -- Load Address LSB
 
      when st_read_LoadAddr2 =>
        AddrMux <= '1';                 -- Load Address MSB
 
      when st_read_read =>
        G_i <= '0';                     -- Read Command
 
      when st_read_LoadOutput =>
        DTO_ce <= '1';                  -- Load output register
 
      when st_write_LoadAddr1 =>
        RC_i      <= '0';               -- Load Address LSB
        WRCmdFlag_i <= '1';               -- Load Write Command code
        W_i       <= '1';
 
      when st_write_LoadAddr2 =>
        AddrMux <= '1';                 -- Load Address MSB
 
      when st_write_write =>
        W_i <= '1';                     -- Write Data
 
      when others => null;
    end case;
  end process OUTPUT_MEMCTRL;
 
 
 
  INTREGS : process (clk, rst_n)
  begin  -- process INTREGS
    if rst_n = '0' then                 -- asynchronous reset (active low)
      ADR_r   <= (others => '0');
      DTI_r   <= (others => '0');
      DTO_r   <= (others => '0');
      BNK_r   <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if ADR_ce = '1' then
        ADR_r <= ADR;
      end if;
      if DTI_ce = '1' then
        DTI_r <= DTI;
      end if;
      if DTO_ce = '1' then
        DTO_r <= Q;
      end if;
      if BNK_ce = '1' then
        BNK_r <= BANK;
      end if;
    end if;
  end process INTREGS;
 
 
  DTO <= DTO_r;
 
 
-------------------------------------------------------------------------------
-- ADDRESS MUX
-------------------------------------------------------------------------------
 
  A_RSV <= ADR_r(AddrRSV-1 downto 0) when AddrMux = '0' else
           ADR_r((2*AddrRSV)-1 downto AddrRSV);
 
  A_EPC <= ADR_r(AddrEPC-1 downto 0) when AddrMux = '0' else
           ADR_r((2*AddrEPC)-1 downto AddrEPC);
 
  A_TID <= ADR_r(AddrTID-1 downto 0) when AddrMux = '0' else
           ADR_r((2*AddrTID)-1 downto AddrTID);
 
  A_USR <= ADR_r(AddrUSR-1 downto 0) when AddrMux = '0' else
           ADR_r((2*AddrUSR)-1 downto AddrUSR);
 
 
-------------------------------------------------------------------------------
-- DATA IN MUX
-------------------------------------------------------------------------------
 
  D <= WriteCommand when WRCmdFlag = '1' else
       DTI_r;
 
-------------------------------------------------------------------------------
-- CONTROL SIGNALS MUXs
-------------------------------------------------------------------------------
 
  W_RSV <= W when BNK_r = "00" else
           '0';
  W_EPC <= W when BNK_r = "01" else
           '0';
  W_TID <= W when BNK_r = "10" else
           '0';
  W_USR <= W when BNK_r = "11" else
           '0';
 
 
  G_RSV <= G when BNK_r = "00" else
           '1';
  G_EPC <= G when BNK_r = "01" else
           '1';
  G_TID <= G when BNK_r = "10" else
           '1';
  G_USR <= G when BNK_r = "11" else
           '1';
 
  RC_RSV <= RC when BNK_r = "00" else
            '1';
  RC_EPC <= RC when BNK_r = "01" else
            '1';
  RC_TID <= RC when BNK_r = "10" else
            '1';
  RC_USR <= RC when BNK_r = "11" else
            '1';
 
  Q <= Q_RSV when BNK_r = "00" else
       Q_EPC when BNK_r = "01" else
       Q_TID when BNK_r = "10" else
       Q_USR;
 
-------------------------------------------------------------------------------
-- MEMORIES
-------------------------------------------------------------------------------
 
  Flash_MeM_RSV_i : Flash_MeM_RSV
    generic map (
      Words => WordsRSV,
      Addr  => AddrRSV,
      Data  => Data)
    port map (
      A     => A_RSV,
      D     => D,
      Q     => Q_RSV,
      G     => G_RSV,
      W     => W_RSV,
      RC    => RC_RSV,
      st    => st);
 
  Flash_MeM_EPC_i : Flash_MeM_EPC
    generic map (
      Words => WordsEPC,
      Addr  => AddrEPC,
      Data  => Data)
    port map (
      A     => A_EPC,
      D     => D,
      Q     => Q_EPC,
      G     => G_EPC,
      W     => W_EPC,
      RC    => RC_EPC,
      st    => st);
 
  Flash_MeM_TID_i : Flash_MeM_TID
    generic map (
      Words => WordsTID,
      Addr  => AddrTID,
      Data  => Data)
    port map (
      A     => A_TID,
      D     => D,
      Q     => Q_TID,
      G     => G_TID,
      W     => W_TID,
      RC    => RC_TID,
      st    => st);
 
  Flash_MeM_USR_i : Flash_MeM_USR
    generic map (
      Words => WordsUSR,
      Addr  => AddrUSR,
      Data  => Data)
    port map (
      A     => A_USR,
      D     => D,
      Q     => Q_USR,
      G     => G_USR,
      W     => W_USR,
      RC    => RC_USR,
      st    => st);
 
end Mem_Ctrl_arch;

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Subversion Repositories epc_rfid_transponder

[/] [epc_rfid_transponder/] [trunk/] [memctrl.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	erwing	`-------------------------------------------------------------------------------`
2			`-- Politecnico di Torino`
3			`-- Dipartimento di Automatica e Informatica`
4			`-------------------------------------------------------------------------------`
5			`-------------------------------------------------------------------------------`
6			`--`
7			`-- Title : Memory Controller`
8			`--`
9			`-- File name : MemCtrl.vhd`
10			`--`
11			`-- Description : Flash memory controller.`
12			`--`
13	3	erwing	`-- Authors : Erwing Sanchez <erwing.sanchez@polito.it>`
14	2	erwing	`--`
15			`-------------------------------------------------------------------------------`
16			`-------------------------------------------------------------------------------`
17			`-- EPC Memory Map`
18			`--`
19			`-- _______________________`
20			`-- \| \| RESERVED MEMORY (Bank 00)`
21			`-- \| \|`
22			`-- \|_______________________\|`
23			`-- \| \| EPC MEMORY (Bank 01)`
24			`-- \| \|`
25			`-- \|_______________________\|`
26			`-- \| \| TID MEMORY (Bank 10)`
27			`-- \| \|`
28			`-- \|_______________________\|`
29			`-- \| \| USER MEMORY (Bank 11)`
30			`-- \| \|`
31			`-- \|_______________________\|`
32			`--`
33
34
35			`library IEEE;`
36			`use IEEE.STD_LOGIC_1164.all;`
37			`use IEEE.STD_LOGIC_ARITH.all;`
38
39
40			`entity Mem_ctrl is`
41			`generic (`
42			`WordsRSV : integer := 8;`
43			`WordsEPC : integer := 16;`
44			`WordsTID : integer := 8;`
45			`WordsUSR : integer := 256;`
46			`--Address are loaded in two steps, so only half of address pins are needed.`
47			`AddrRSV : integer := 2; -- 1/2address pins`
48			`AddrEPC : integer := 3; -- 1/2address pins`
49			`AddrTID : integer := 2; -- 1/2address pins`
50			`AddrUSR : integer := 5; -- 1/2address pins`
51			`Data : integer := 16);`
52			`port (`
53			`clk : in std_logic;`
54			`rst_n : in std_logic;`
55			`BANK : in std_logic_vector(1 downto 0);`
56			`WR : in std_logic; -- Write signal`
57			`RD : in std_logic; -- Read signal`
58			`ADR : in std_logic_vector((2*AddrUSR)-1 downto 0);`
59			`DTI : in std_logic_vector(Data-1 downto 0);`
60			`DTO : out std_logic_vector(Data-1 downto 0);`
61			`RB : out std_logic -- Ready/nBusy signal(unbuffered!)`
62			`);`
63			`end Mem_ctrl;`
64
65
66			`architecture Mem_Ctrl_arch of Mem_ctrl is`
67
68
69			`component Flash_MeM_EPC`
70			`generic (`
71			`Words : integer;`
72			`Addr : integer;`
73			`Data : integer);`
74			`port (`
75			`A : in std_logic_vector(Addr-1 downto 0);`
76			`D : in std_logic_vector(Data-1 downto 0);`
77			`Q : out std_logic_vector(Data-1 downto 0);`
78			`G : in std_logic;`
79			`W : in std_logic;`
80			`RC : in std_logic;`
81			`st : out std_logic);`
82			`end component;`
83
84			`component Flash_MeM_TID`
85			`generic (`
86			`Words : integer;`
87			`Addr : integer;`
88			`Data : integer);`
89			`port (`
90			`A : in std_logic_vector(Addr-1 downto 0);`
91			`D : in std_logic_vector(Data-1 downto 0);`
92			`Q : out std_logic_vector(Data-1 downto 0);`
93			`G : in std_logic;`
94			`W : in std_logic;`
95			`RC : in std_logic;`
96			`st : out std_logic);`
97			`end component;`
98
99			`component Flash_MeM_USR`
100			`generic (`
101			`Words : integer;`
102			`Addr : integer;`
103			`Data : integer);`
104			`port (`
105			`A : in std_logic_vector(Addr-1 downto 0);`
106			`D : in std_logic_vector(Data-1 downto 0);`
107			`Q : out std_logic_vector(Data-1 downto 0);`
108			`G : in std_logic;`
109			`W : in std_logic;`
110			`RC : in std_logic;`
111			`st : out std_logic);`
112			`end component;`
113
114			`component Flash_MeM_RSV`
115			`generic (`
116			`Words : integer;`
117			`Addr : integer;`
118			`Data : integer);`
119			`port (`
120			`A : in std_logic_vector(Addr-1 downto 0);`
121			`D : in std_logic_vector(Data-1 downto 0);`
122			`Q : out std_logic_vector(Data-1 downto 0);`
123			`G : in std_logic;`
124			`W : in std_logic;`
125			`RC : in std_logic;`
126			`st : out std_logic);`
127			`end component;`
128
129
130			`-- Contants`
131			`constant WriteCommand : std_logic_vector(Data-1 downto 0) := conv_std_logic_vector(64, Data); --"01000000" Flash Write Code`
132			`-- FSM`
133			`type MemCtrl_t is (st_idle, st_read_LoadAddr1, st_read_LoadAddr2, st_read_LoadOutput, st_read_read, st_write_LoadAddr1, st_write_LoadAddr2, st_write_write);`
134			`signal StMCtrl, NextStMCtrl : MemCtrl_t;`
135			`-- Memory signals`
136			`signal A_RSV : std_logic_vector(AddrRSV-1 downto 0);`
137			`signal A_EPC : std_logic_vector(AddrEPC-1 downto 0);`
138			`signal A_TID : std_logic_vector(AddrTID-1 downto 0);`
139			`signal A_USR : std_logic_vector(AddrUSR-1 downto 0);`
140			`signal D : std_logic_vector(Data-1 downto 0);`
141			`signal Q : std_logic_vector(Data-1 downto 0);`
142			`signal G, G_i : std_logic;`
143			`signal W, W_i : std_logic;`
144			`signal RC, RC_i : std_logic;`
145			`signal st : std_logic;`
146			`signal W_RSV, W_EPC, W_TID, W_USR : std_logic;`
147			`signal G_RSV, G_EPC, G_TID, G_USR : std_logic;`
148			`signal Q_RSV, Q_EPC, Q_TID, Q_USR : std_logic_vector(Data-1 downto 0);`
149			`signal RC_RSV, RC_EPC, RC_TID, RC_USR : std_logic;`
150			`-- Internal regs`
151			`signal DTI_r : std_logic_vector(Data-1 downto 0);`
152			`signal DTO_r : std_logic_vector(Data-1 downto 0);`
153			`signal ADR_r : std_logic_vector((2*AddrUSR)-1 downto 0);`
154			`signal BNK_r : std_logic_vector(1 downto 0);`
155			`signal ADR_ce, DTI_ce, DTO_ce, BNK_ce : std_logic;`
156			`-- Internal Flags & other signals`
157			`signal AddrMux : std_logic;`
158			`signal WRCmdFlag, WRCmdFlag_i : std_logic;`
159
160			`begin -- Mem_Ctrl_arch`
161
162
163			`SYNC_MEMCTRL : process (clk, rst_n)`
164			`begin -- process SYNC`
165			`if rst_n = '0' then -- asynchronous reset (active low)`
166			`StMCtrl <= st_idle;`
167			`RC <= '1'; -- 1 -> 0 : Load LSB address`
168			`G <= '1'; -- 0: enable`
169			`W <= '0';`
170			`WRCmdFlag <= '0';`
171			`elsif clk'event and clk = '1' then -- rising clock edge`
172			`StMCtrl <= NextStMCtrl;`
173			`RC <= RC_i;`
174			`G <= G_i;`
175			`W <= W_i;`
176			`WRCmdFlag <= WRCmdFlag_i;`
177			`end if;`
178			`end process SYNC_MEMCTRL;`
179
180			`NEXTST_MEMCTRL : process (StMCtrl, WR, RD, ADR, DTI)`
181			`begin -- process NEXTST`
182
183			`NextStMCtrl <= StMCtrl;`
184
185			`case StMCtrl is`
186			`when st_idle =>`
187			`if WR = '1' then`
188			`NextStMCtrl <= st_write_LoadAddr1;`
189			`elsif RD = '1' then`
190			`NextStMCtrl <= st_read_LoadAddr1;`
191			`end if;`
192			`when st_read_LoadAddr1 =>`
193			`NextStMCtrl <= st_read_LoadAddr2;`
194			`when st_read_LoadAddr2 =>`
195			`NextStMCtrl <= st_read_read;`
196			`when st_read_read =>`
197			`NextStMCtrl <= st_read_LoadOutput;`
198			`when st_read_LoadOutput =>`
199			`NextStMCtrl <= st_idle;`
200
201			`when st_write_LoadAddr1 =>`
202			`NextStMCtrl <= st_write_LoadAddr2;`
203			`when st_write_LoadAddr2 =>`
204			`NextStMCtrl <= st_write_write;`
205			`when st_write_write =>`
206			`NextStMCtrl <= st_idle;`
207
208			`when others => null;`
209			`end case;`
210
211			`end process NEXTST_MEMCTRL;`
212
213
214			`OUTPUT_MEMCTRL : process (StMCtrl, WR, RD)`
215			`begin -- process OUTPUT_MEMCTRL`
216
217			`RB <= '0';`
218			`ADR_ce <= '0';`
219			`DTI_ce <= '0';`
220			`DTO_ce <= '0';`
221			`BNK_ce <= '0';`
222			`AddrMux <= '0';`
223			`WRCmdFlag_i <= '0';`
224			`-- Memory signals`
225			`RC_i <= '1';`
226			`G_i <= '1';`
227			`W_i <= '0';`
228
229			`case StMCtrl is`
230			`when st_idle =>`
231			`RB <= '1';`
232			`if WR = '1' then`
233			`ADR_ce <= '1'; -- load address`
234			`DTI_ce <= '1'; -- load data`
235			`BNK_ce <= '1'; -- load Bank`
236			`RB <= '0';`
237			`elsif RD = '1' then`
238			`ADR_ce <= '1'; -- load address`
239			`BNK_ce <= '1'; -- load Bank`
240			`RB <= '0';`
241			`end if;`
242
243			`when st_read_LoadAddr1 =>`
244			`RC_i <= '0'; -- Load Address LSB`
245
246			`when st_read_LoadAddr2 =>`
247			`AddrMux <= '1'; -- Load Address MSB`
248
249			`when st_read_read =>`
250			`G_i <= '0'; -- Read Command`
251
252			`when st_read_LoadOutput =>`
253			`DTO_ce <= '1'; -- Load output register`
254
255			`when st_write_LoadAddr1 =>`
256			`RC_i <= '0'; -- Load Address LSB`
257			`WRCmdFlag_i <= '1'; -- Load Write Command code`
258			`W_i <= '1';`
259
260			`when st_write_LoadAddr2 =>`
261			`AddrMux <= '1'; -- Load Address MSB`
262
263			`when st_write_write =>`
264			`W_i <= '1'; -- Write Data`
265
266			`when others => null;`
267			`end case;`
268			`end process OUTPUT_MEMCTRL;`
269
270
271
272			`INTREGS : process (clk, rst_n)`
273			`begin -- process INTREGS`
274			`if rst_n = '0' then -- asynchronous reset (active low)`
275			`ADR_r <= (others => '0');`
276			`DTI_r <= (others => '0');`
277			`DTO_r <= (others => '0');`
278			`BNK_r <= (others => '0');`
279			`elsif clk'event and clk = '1' then -- rising clock edge`
280			`if ADR_ce = '1' then`
281			`ADR_r <= ADR;`
282			`end if;`
283			`if DTI_ce = '1' then`
284			`DTI_r <= DTI;`
285			`end if;`
286			`if DTO_ce = '1' then`
287			`DTO_r <= Q;`
288			`end if;`
289			`if BNK_ce = '1' then`
290			`BNK_r <= BANK;`
291			`end if;`
292			`end if;`
293			`end process INTREGS;`
294
295
296			`DTO <= DTO_r;`
297
298
299			`-------------------------------------------------------------------------------`
300			`-- ADDRESS MUX`
301			`-------------------------------------------------------------------------------`
302
303			`A_RSV <= ADR_r(AddrRSV-1 downto 0) when AddrMux = '0' else`
304			`ADR_r((2*AddrRSV)-1 downto AddrRSV);`
305
306			`A_EPC <= ADR_r(AddrEPC-1 downto 0) when AddrMux = '0' else`
307			`ADR_r((2*AddrEPC)-1 downto AddrEPC);`
308
309			`A_TID <= ADR_r(AddrTID-1 downto 0) when AddrMux = '0' else`
310			`ADR_r((2*AddrTID)-1 downto AddrTID);`
311
312			`A_USR <= ADR_r(AddrUSR-1 downto 0) when AddrMux = '0' else`
313			`ADR_r((2*AddrUSR)-1 downto AddrUSR);`
314
315
316			`-------------------------------------------------------------------------------`
317			`-- DATA IN MUX`
318			`-------------------------------------------------------------------------------`
319
320			`D <= WriteCommand when WRCmdFlag = '1' else`
321			`DTI_r;`
322
323			`-------------------------------------------------------------------------------`
324			`-- CONTROL SIGNALS MUXs`
325			`-------------------------------------------------------------------------------`
326
327			`W_RSV <= W when BNK_r = "00" else`
328			`'0';`
329			`W_EPC <= W when BNK_r = "01" else`
330			`'0';`
331			`W_TID <= W when BNK_r = "10" else`
332			`'0';`
333			`W_USR <= W when BNK_r = "11" else`
334			`'0';`
335
336
337			`G_RSV <= G when BNK_r = "00" else`
338			`'1';`
339			`G_EPC <= G when BNK_r = "01" else`
340			`'1';`
341			`G_TID <= G when BNK_r = "10" else`
342			`'1';`
343			`G_USR <= G when BNK_r = "11" else`
344			`'1';`
345
346			`RC_RSV <= RC when BNK_r = "00" else`
347			`'1';`
348			`RC_EPC <= RC when BNK_r = "01" else`
349			`'1';`
350			`RC_TID <= RC when BNK_r = "10" else`
351			`'1';`
352			`RC_USR <= RC when BNK_r = "11" else`
353			`'1';`
354
355			`Q <= Q_RSV when BNK_r = "00" else`
356			`Q_EPC when BNK_r = "01" else`
357			`Q_TID when BNK_r = "10" else`
358			`Q_USR;`
359
360			`-------------------------------------------------------------------------------`
361			`-- MEMORIES`
362			`-------------------------------------------------------------------------------`
363
364			`Flash_MeM_RSV_i : Flash_MeM_RSV`
365			`generic map (`
366			`Words => WordsRSV,`
367			`Addr => AddrRSV,`
368			`Data => Data)`
369			`port map (`
370			`A => A_RSV,`
371			`D => D,`
372			`Q => Q_RSV,`
373			`G => G_RSV,`
374			`W => W_RSV,`
375			`RC => RC_RSV,`
376			`st => st);`
377
378			`Flash_MeM_EPC_i : Flash_MeM_EPC`
379			`generic map (`
380			`Words => WordsEPC,`
381			`Addr => AddrEPC,`
382			`Data => Data)`
383			`port map (`
384			`A => A_EPC,`
385			`D => D,`
386			`Q => Q_EPC,`
387			`G => G_EPC,`
388			`W => W_EPC,`
389			`RC => RC_EPC,`
390			`st => st);`
391
392			`Flash_MeM_TID_i : Flash_MeM_TID`
393			`generic map (`
394			`Words => WordsTID,`
395			`Addr => AddrTID,`
396			`Data => Data)`
397			`port map (`
398			`A => A_TID,`
399			`D => D,`
400			`Q => Q_TID,`
401			`G => G_TID,`
402			`W => W_TID,`
403			`RC => RC_TID,`
404			`st => st);`
405
406			`Flash_MeM_USR_i : Flash_MeM_USR`
407			`generic map (`
408			`Words => WordsUSR,`
409			`Addr => AddrUSR,`
410			`Data => Data)`
411			`port map (`
412			`A => A_USR,`
413			`D => D,`
414			`Q => Q_USR,`
415			`G => G_USR,`
416			`W => W_USR,`
417			`RC => RC_USR,`
418			`st => st);`
419
420			`end Mem_Ctrl_arch;`