OpenCores
URL https://opencores.org/ocsvn/esoc/esoc/trunk
4-`88888888ieee.std_logic_1164.std_logic_vectortor88888aclrclrLL-dataataLL.(rdclkclLL/HrdreqreLL0hwrclkclLL1wrreqreLL2qreLL3rdemptyLL4rdusedwLL5wrfulluLL6(wrusedwLL7Hsub_wire0reLL>hsub_wire1reLL?sub_wire2reLL@sub_wire3reLLAsub_wire4reLLBline__10410line__10510line__10610line__10710line__10810dcfifo_mixed_widths_componentenCyclone IIIintended_device_familyiRAM_BLOCK_TYPE=M9K(lpm_hintintlpm_numwordsrdsON`lpm_showaheadeadcfifolpm_typeypelpm_widthdtlpm_widthutlpm_widthu_ru_rlpm_width_rOFFGoverflow_checkinginrdsync_delaypipeipeOFF{underflow_checkingiON`use_eabON`write_aclr_synchnchwrsync_delaypipeipebdcfifo_mixed_widthsaltera_mf_m workorkieeeeee! synesoc_fifo_2kx64x32xc:/data/temp/ESoC/Sources/altera/esoc_fifo_nkx32x64/esoc_fifo_2kx64x32.vhdvK738 3f9 {734 3f2 {530 42e {{ t468} { 3e8} {0 104}} 53a 42e {{ t490} { 448} {0 105}} 544 42e {{ t4b8} { 428} {0 106}} 54e 42e {{ t4e0} { 3c8} {0 107}} 558 42e {{ t508} { 408} {0 108}} }}

Subversion Repositories esoc

[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [work/] [esoc_fifo_2kx64x32/] [syn.prw] - Blame information for rev 41

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