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[/] [ethernet_tri_mode/] [trunk/] [bench/] [verilog/] [tb_top.v] - Blame information for rev 33

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1 6 maverickis
`timescale 1 ns/100ps
2 5 maverickis
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  tb_top.v                                                    ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Jon Gao (gaojon@yahoo.com)                            ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//                                                                    
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// CVS Revision History                                               
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//                                                                    
42 6 maverickis
// $Log: not supported by cvs2svn $
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// Revision 1.3  2006/01/19 14:07:51  maverickist
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// verification is complete.
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//
46 7 maverickis
// Revision 1.2  2005/12/16 06:44:13  Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
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// no message
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// 
53 5 maverickis
 
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module tb_top (
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);
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//******************************************************************************
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//internal signals                                                              
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//******************************************************************************
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                                //system signals
60 6 maverickis
reg                             Reset                                   ;
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reg                             Clk_125M                                ;
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reg                             Clk_user                                ;
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reg                             Clk_reg                                 ;
64 5 maverickis
                                //user interface 
65 6 maverickis
wire                    Rx_mac_ra                               ;
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wire                    Rx_mac_rd                               ;
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wire    [31:0]   Rx_mac_data                             ;
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wire    [1:0]    Rx_mac_BE                               ;
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wire                    Rx_mac_pa                               ;
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wire                    Rx_mac_sop                              ;
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wire                    Rx_mac_eop                              ;
72 5 maverickis
                                //user interface 
73 6 maverickis
wire                    Tx_mac_wa                       ;
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wire                    Tx_mac_wr                       ;
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wire    [31:0]   Tx_mac_data                     ;
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wire    [1:0]    Tx_mac_BE                               ;//big endian
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wire                    Tx_mac_sop                      ;
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wire                    Tx_mac_eop                              ;
79 5 maverickis
                                //Phy interface          
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                                //Phy interface                 
81 6 maverickis
wire                    Gtx_clk                                 ;//used only in GMII mode
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wire                    Rx_clk                                  ;
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wire                    Tx_clk                                  ;//used only in MII mode
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wire                    Tx_er                                   ;
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wire                    Tx_en                                   ;
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wire    [7:0]    Txd                                             ;
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wire                    Rx_er                                   ;
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wire                    Rx_dv                                   ;
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wire    [7:0]    Rxd                                             ;
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wire                    Crs                                             ;
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wire                    Col                                             ;
92 7 maverickis
wire            CSB                     ;
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wire            WRB                     ;
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wire    [15:0]  CD_in                   ;
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wire    [15:0]  CD_out                  ;
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wire    [7:0]   CA                      ;
97 5 maverickis
                                //Phy int host interface     
98 6 maverickis
wire                    Line_loop_en                    ;
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wire    [2:0]    Speed                                   ;
100 7 maverickis
                                //mii
101 28 maverickis
wire            Mdo                         ;// MII Management Data out
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wire            Mdi                         ;// MII Management Data In
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wire            MdoEn                   ;// MII Management Data out enable
104 6 maverickis
wire            Mdc                             ;// MII Management Data Clock   
105 7 maverickis
wire            CPU_init_end            ;
106 5 maverickis
//******************************************************************************
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//internal signals                                                              
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//******************************************************************************
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110 6 maverickis
initial
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        begin
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                        Reset   =1;
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        #20             Reset   =0;
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        end
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always
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        begin
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        #4              Clk_125M=0;
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        #4              Clk_125M=1;
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        end
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always
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        begin
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        #5              Clk_user=0;
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        #5              Clk_user=1;
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        end
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always
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        begin
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        #10             Clk_reg=0;
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        #10             Clk_reg=1;
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        end
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initial
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        begin
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        $shm_open("tb_top.shm",,900000000,);
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        $shm_probe("AS");
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        end
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141 5 maverickis
MAC_top U_MAC_top(
142 6 maverickis
 //system signals                       (//system signals           ),
143 5 maverickis
.Reset                                          (Reset                                      ),
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.Clk_125M                                       (Clk_125M                                   ),
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.Clk_user                                       (Clk_user                                   ),
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.Clk_reg                                            (Clk_reg                                    ),
147 7 maverickis
.Speed                          (Speed                      ),
148 6 maverickis
 //user interface               (//user interface           ),
149 5 maverickis
.Rx_mac_ra                                      (Rx_mac_ra                                  ),
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.Rx_mac_rd                                      (Rx_mac_rd                                  ),
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.Rx_mac_data                                (Rx_mac_data                                ),
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.Rx_mac_BE                                      (Rx_mac_BE                                  ),
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.Rx_mac_pa                                      (Rx_mac_pa                                  ),
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.Rx_mac_sop                                     (Rx_mac_sop                                 ),
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.Rx_mac_eop                                     (Rx_mac_eop                                 ),
156 6 maverickis
 //user interface               (//user interface           ),
157 5 maverickis
.Tx_mac_wa                              (Tx_mac_wa                          ),
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.Tx_mac_wr                              (Tx_mac_wr                          ),
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.Tx_mac_data                        (Tx_mac_data                        ),
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.Tx_mac_BE                                      (Tx_mac_BE                                  ),
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.Tx_mac_sop                             (Tx_mac_sop                         ),
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.Tx_mac_eop                                     (Tx_mac_eop                                 ),
163 6 maverickis
 //Phy interface                (//Phy interface            ),
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 //Phy interface                            (//Phy interface                    ),
165 5 maverickis
.Gtx_clk                                            (Gtx_clk                                    ),
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.Rx_clk                                         (Rx_clk                                     ),
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.Tx_clk                                         (Tx_clk                                     ),
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.Tx_er                                          (Tx_er                                      ),
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.Tx_en                                          (Tx_en                                      ),
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.Txd                                                (Txd                                                ),
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.Rx_er                                          (Rx_er                                      ),
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.Rx_dv                                          (Rx_dv                                      ),
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.Rxd                                                (Rxd                                                ),
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.Crs                                                (Crs                                                ),
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.Col                                                (Col                                                ),
176 7 maverickis
//host interface
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.CSB                            (CSB                        ),
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.WRB                            (WRB                        ),
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.CD_in                          (CD_in                      ),
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.CD_out                         (CD_out                     ),
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.CA                             (CA                         ),
182 6 maverickis
 //MII interface signals        (//MII interface signals    ),
183 28 maverickis
.Mdi                            (Mdi                        ),
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.Mdo                            (Mdo                        ),
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.MdoEn                          (MdoEn                      ),
186 5 maverickis
.Mdc                                (Mdc                                )
187 6 maverickis
);
188 5 maverickis
 
189 6 maverickis
Phy_sim U_Phy_sim (
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.Gtx_clk                                                (Gtx_clk                                ),
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.Rx_clk                             (Rx_clk                             ),
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.Tx_clk                             (Tx_clk                             ),
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.Tx_er                              (Tx_er                              ),
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.Tx_en                              (Tx_en                              ),
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.Txd                                    (Txd                                ),
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.Rx_er                              (Rx_er                              ),
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.Rx_dv                              (Rx_dv                              ),
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.Rxd                                    (Rxd                                ),
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.Crs                                    (Crs                                ),
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.Col                                    (Col                                ),
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.Speed                              (Speed                              )
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);
203 5 maverickis
 
204 6 maverickis
User_int_sim U_User_int_sim(
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.Reset                                                  (Reset                                          ),
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.Clk_user                                   (Clk_user                           ),
207 7 maverickis
.CPU_init_end                   (CPU_init_end               ),
208 6 maverickis
 //user inputerface             (//user inputerface         ),
209
.Rx_mac_ra                                  (Rx_mac_ra                          ),
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.Rx_mac_rd                                  (Rx_mac_rd                          ),
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.Rx_mac_data                            (Rx_mac_data                        ),
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.Rx_mac_BE                                  (Rx_mac_BE                          ),
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.Rx_mac_pa                                  (Rx_mac_pa                          ),
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.Rx_mac_sop                                 (Rx_mac_sop                         ),
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.Rx_mac_eop                                 (Rx_mac_eop                         ),
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 //user inputerface             (//user inputerface         ),
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.Tx_mac_wa                          (Tx_mac_wa                  ),
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.Tx_mac_wr                          (Tx_mac_wr                  ),
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.Tx_mac_data                    (Tx_mac_data                ),
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.Tx_mac_BE                                  (Tx_mac_BE                          ),
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.Tx_mac_sop                         (Tx_mac_sop                 ),
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.Tx_mac_eop                                 (Tx_mac_eop                         )
223 5 maverickis
);
224 6 maverickis
 
225 7 maverickis
host_sim U_host_sim(
226 6 maverickis
.Reset                                  (Reset                          ),
227
.Clk_reg                                (Clk_reg                        ),
228 7 maverickis
.CSB                            (CSB                        ),
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.WRB                            (WRB                        ),
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.CD_in                          (CD_in                      ),
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.CD_out                         (CD_out                     ),
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.CPU_init_end                   (CPU_init_end               ),
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.CA                             (CA                         )
234
 
235 6 maverickis
);
236 5 maverickis
endmodule

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