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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [reg_int.v] - Blame information for rev 14

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Line No. Rev Author Line
1 7 maverickis 
module Reg_int (
2 
input                   Reset                   ,
3 
input                   Clk_reg                 ,
4 
input                   CSB                     ,
5 
input                   WRB                     ,
6 
input           [15:0]  CD_in                   ,
7 
output   reg    [15:0]  CD_out                  ,
8 
input           [7:0]   CA                      ,
9 
                        //Tx host interface
10 
output          [4:0]   Tx_Hwmark               ,
11 
output          [4:0]   Tx_Lwmark               ,
12 
output                  pause_frame_send_en     ,
13 
output          [15:0]  pause_quanta_set        ,
14 
output                  MAC_tx_add_en           ,
15 
output                  FullDuplex              ,
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output          [3:0]   MaxRetry                ,
17 
output          [5:0]   IFGset                  ,
18 
output          [7:0]   MAC_tx_add_prom_data    ,
19 
output          [2:0]   MAC_tx_add_prom_add     ,
20 
output                  MAC_tx_add_prom_wr      ,
21 
output                  tx_pause_en             ,
22 
output                  xoff_cpu                ,
23 
output                  xon_cpu                 ,
24 
                        //Rx host interface
25 
output                  MAC_rx_add_chk_en       ,
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output          [7:0]   MAC_rx_add_prom_data    ,
27 
output          [2:0]   MAC_rx_add_prom_add     ,
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output                  MAC_rx_add_prom_wr      ,
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output                  broadcast_filter_en     ,
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output          [15:0]  broadcast_bucket_depth              ,
31 
output          [15:0]  broadcast_bucket_interval           ,
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output                  RX_APPEND_CRC           ,
33 
output          [4:0]   Rx_Hwmark           ,
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output          [4:0]   Rx_Lwmark           ,
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output                  CRC_chk_en              ,
36 
output          [5:0]   RX_IFG_SET              ,
37 
output          [15:0]  RX_MAX_LENGTH           ,// 1518
38 
output          [6:0]   RX_MIN_LENGTH           ,// 64
39 
                        //RMON host interface
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output          [5:0]   CPU_rd_addr             ,
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output                  CPU_rd_apply            ,
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input                   CPU_rd_grant            ,
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input           [31:0]  CPU_rd_dout             ,
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                        //Phy int host interface
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output                  Line_loop_en            ,
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output          [2:0]   Speed                   ,
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                        //MII to CPU
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output          [7:0]   Divider                 ,// Divider for the host clock
49 
output          [15:0]  CtrlData                ,// Control Data (to be written to the PHY reg.)
50 
output          [4:0]   Rgad                    ,// Register Address (within the PHY)
51 
output          [4:0]   Fiad                    ,// PHY Address
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output                  NoPre                   ,// No Preamble (no 32-bit preamble)
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output                  WCtrlData               ,// Write Control Data operation
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output                  RStat                   ,// Read Status operation
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output                  ScanStat                ,// Scan Status operation
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input                   Busy                    ,// Busy Signal
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input                   LinkFail                ,// Link Integrity Signal
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input                   Nvalid                  ,// Invalid Status (qualifier for the valid scan result)
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input           [15:0]  Prsd                    ,// Read Status Data (data read from the PHY)
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input                   WCtrlDataStart          ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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input                   RStatStart              ,// This signal resets the RSTAT BIT in the MIIM Command register
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input                   UpdateMIIRX_DATAReg     ,// Updates MII RX_DATA register with read data
63 
);
64 
 
65 
    RegCPUData U_0_000(Tx_Hwmark                ,7'd000,16'h001e,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
66 
    RegCPUData U_0_001(Tx_Lwmark                ,7'd001,16'h0019,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
67 
    RegCPUData U_0_002(pause_frame_send_en      ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
68 
    RegCPUData U_0_003(pause_quanta_set         ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
69 
    RegCPUData U_0_004(IFGset                   ,7'd004,16'h001e,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
70 
    RegCPUData U_0_005(FullDuplex               ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
71 
    RegCPUData U_0_006(MaxRetry                 ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
72 
    RegCPUData U_0_007(MAC_tx_add_en            ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
73 
    RegCPUData U_0_008(MAC_tx_add_prom_data     ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
74 
    RegCPUData U_0_009(MAC_tx_add_prom_add      ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
75 
    RegCPUData U_0_010(MAC_tx_add_prom_wr       ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
76 
    RegCPUData U_0_011(tx_pause_en              ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
77 
    RegCPUData U_0_012(xoff_cpu                 ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
78 
    RegCPUData U_0_013(xon_cpu                  ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
79 
    RegCPUData U_0_014(MAC_rx_add_chk_en        ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
80 
    RegCPUData U_0_015(MAC_rx_add_prom_data     ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
81 
    RegCPUData U_0_016(MAC_rx_add_prom_add      ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
82 
    RegCPUData U_0_017(MAC_rx_add_prom_wr       ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
83 
    RegCPUData U_0_018(broadcast_filter_en      ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
84 
    RegCPUData U_0_019(broadcast_bucket_depth   ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
85 
    RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
86 
    RegCPUData U_0_021(RX_APPEND_CRC            ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
87 
    RegCPUData U_0_022(Rx_Hwmark                ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
88 
    RegCPUData U_0_023(Rx_Lwmark                ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
89 
    RegCPUData U_0_024(CRC_chk_en               ,7'd024,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
90 
    RegCPUData U_0_025(RX_IFG_SET               ,7'd025,16'h001e,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
91 
    RegCPUData U_0_026(RX_MAX_LENGTH            ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
92 
    RegCPUData U_0_027(RX_MIN_LENGTH            ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
93 
    RegCPUData U_0_028(CPU_rd_addr              ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
94 
    RegCPUData U_0_029(CPU_rd_apply             ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
95 
//  RegCPUData U_0_030(CPU_rd_grant             ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
96 14 maverickis 
//  RegCPUData U_0_031(CPU_rd_dout_l            ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
97 
//  RegCPUData U_0_032(CPU_rd_dout_h            ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
98 
    RegCPUData U_0_033(Line_loop_en             ,7'd034,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
99 
    RegCPUData U_0_034(Speed                    ,7'd035,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
100 7 maverickis 
 
101 
always @ (*)
102 
        case (CA[7:1])
103 
                7'd00:    CD_out=Tx_Hwmark                  ;
104 
                7'd01:    CD_out=Tx_Lwmark                  ;
105 
                7'd02:    CD_out=pause_frame_send_en        ;
106 
                7'd03:    CD_out=pause_quanta_set           ;
107 
                7'd04:    CD_out=IFGset                     ;
108 
                7'd05:    CD_out=FullDuplex                 ;
109 
                7'd06:    CD_out=MaxRetry                   ;
110 
                7'd07:    CD_out=MAC_tx_add_en              ;
111 
                7'd08:    CD_out=MAC_tx_add_prom_data       ;
112 
                7'd09:    CD_out=MAC_tx_add_prom_add        ;
113 
                7'd10:    CD_out=MAC_tx_add_prom_wr         ;
114 
                7'd11:    CD_out=tx_pause_en                ;
115 
                7'd12:    CD_out=xoff_cpu                   ;
116 
                7'd13:    CD_out=xon_cpu                    ;
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                7'd14:    CD_out=MAC_rx_add_chk_en          ;
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                7'd15:    CD_out=MAC_rx_add_prom_data       ;
119 
                7'd16:    CD_out=MAC_rx_add_prom_add        ;
120 
                7'd17:    CD_out=MAC_rx_add_prom_wr         ;
121 
                7'd18:    CD_out=broadcast_filter_en        ;
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                7'd19:    CD_out=broadcast_bucket_depth     ;
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                7'd20:    CD_out=broadcast_bucket_interval  ;
124 
                7'd21:    CD_out=RX_APPEND_CRC              ;
125 
                7'd22:    CD_out=Rx_Hwmark                  ;
126 
                7'd23:    CD_out=Rx_Lwmark                  ;
127 
                7'd24:    CD_out=CRC_chk_en                 ;
128 
                7'd25:    CD_out=RX_IFG_SET                 ;
129 
                7'd26:    CD_out=RX_MAX_LENGTH              ;
130 
                7'd27:    CD_out=RX_MIN_LENGTH              ;
131 
                7'd28:    CD_out=CPU_rd_addr                ;
132 
                7'd29:    CD_out=CPU_rd_apply               ;
133 
                7'd30:    CD_out=CPU_rd_grant               ;
134 14 maverickis 
                7'd31:    CD_out=CPU_rd_dout[15:0]          ;
135 
                7'd32:    CD_out=CPU_rd_dout[31:16]         ;
136 
                7'd33:    CD_out=Line_loop_en               ;
137 
                7'd34:    CD_out=Speed                      ;
138 7 maverickis 
                default:    CD_out=0                        ;
139 
        endcase
140 
 
141 
endmodule
142 
 
143 
module RegCPUData(
144 
RegOut,
145 
CA_reg_set,
146 
RegInit,
147 
 
148 
Reset,
149 
Clk,
150 
CWR_pulse,
151 
CCSB,
152 
CA_reg,
153 
CD_in_reg
154 
);
155 
output[15:0]    RegOut;
156 
input[6:0]      CA_reg_set;
157 
input[15:0]     RegInit;
158 
//
159 
input           Reset;
160 
input           Clk;
161 
input           CWR_pulse;
162 
input           CCSB;
163 
input[7:0]      CA_reg;
164 
input[15:0]     CD_in_reg;
165 
//
166 
reg[15:0]       RegOut;
167 
 
168 
always  @(posedge Reset or posedge Clk)
169 
    if(Reset)
170 
        RegOut      <=RegInit;
171 
    else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0])
172 
        RegOut      <=CD_in_reg;
173 
 
174 
endmodule

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