OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_outputcontrol.v] - Blame information for rev 335

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_outputcontrol.v                                         ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 109 mohor
// Revision 1.3  2002/01/23 10:28:16  mohor
45
// Link in the header changed.
46
//
47 37 mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
48
// eth_timescale.v changed to timescale.v This is done because of the
49
// simulation of the few cores in a one joined project.
50
//
51 22 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
52
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
53
// Include files fixed to contain no path.
54
// File names and module names changed ta have a eth_ prologue in the name.
55
// File eth_timescale.v is used to define timescale
56
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
57
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
58
// and Mdo_OE. The bidirectional signal must be created on the top level. This
59
// is done due to the ASIC tools.
60
//
61 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
62
// Directory structure changed. Files checked and joind together.
63
//
64
// Revision 1.3  2001/06/01 22:28:56  mohor
65
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
66
//
67
//
68
 
69 22 mohor
`include "timescale.v"
70 15 mohor
 
71
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
72
 
73
parameter Tp = 1;
74
 
75
input         Clk;                // Host Clock
76
input         Reset;              // General Reset
77
input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
78
input         NoPre;              // No Preamble (no 32-bit preamble)
79
input         InProgress;         // Operation in progress
80
input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
81
input   [6:0] BitCounter;         // Bit Counter
82
input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
83
 
84
output        Mdo;                // MII Management Data Output
85
output        MdoEn;              // MII Management Data Output Enable
86
 
87
wire          SerialEn;
88
 
89
reg           MdoEn_2d;
90
reg           MdoEn_d;
91
reg           MdoEn;
92
 
93
reg           Mdo_2d;
94
reg           Mdo_d;
95
reg           Mdo;                // MII Management Data Output
96
 
97
 
98
 
99
// Generation of the Serial Enable signal (enables the serialization of the data)
100
assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
101 109 mohor
                | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
102 15 mohor
 
103
 
104
// Generation of the MdoEn signal
105
always @ (posedge Clk or posedge Reset)
106
begin
107
  if(Reset)
108
    begin
109
      MdoEn_2d <= #Tp 1'b0;
110
      MdoEn_d <= #Tp 1'b0;
111
      MdoEn <= #Tp 1'b0;
112
    end
113
  else
114
    begin
115
      if(MdcEn_n)
116
        begin
117
          MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
118
          MdoEn_d <= #Tp MdoEn_2d;
119
          MdoEn <= #Tp MdoEn_d;
120
        end
121
    end
122
end
123
 
124
 
125
// Generation of the Mdo signal.
126
always @ (posedge Clk or posedge Reset)
127
begin
128
  if(Reset)
129
    begin
130
      Mdo_2d <= #Tp 1'b0;
131
      Mdo_d <= #Tp 1'b0;
132
      Mdo <= #Tp 1'b0;
133
    end
134
  else
135
    begin
136
      if(MdcEn_n)
137
        begin
138
          Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
139
          Mdo_d <= #Tp ShiftedBit | Mdo_2d;
140
          Mdo <= #Tp Mdo_d;
141
        end
142
    end
143
end
144
 
145
 
146
 
147
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.