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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_rxethmac.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
46 65 mohor
// Revision 1.7  2002/02/15 13:44:28  mohor
47
// RxAbort is an output. No need to have is declared as wire.
48
//
49 62 mohor
// Revision 1.6  2002/02/15 11:17:48  mohor
50
// File format changed.
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//
52 58 mohor
// Revision 1.5  2002/02/14 20:48:43  billditt
53
// Addition  of new module eth_addrcheck.v
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//
55 53 billditt
// Revision 1.4  2002/01/23 10:28:16  mohor
56
// Link in the header changed.
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//
58 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
59
// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
62 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
63
// Few little NCSIM warnings fixed.
64
//
65 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
66
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
68
// File names and module names changed ta have a eth_ prologue in the name.
69
// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
71
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
74
//
75 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
76
// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.1  2001/06/27 21:26:19  mohor
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// Initial release of the RxEthMAC module.
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//
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//
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//
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//
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//
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86 22 mohor
`include "timescale.v"
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88
 
89
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
90 65 mohor
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
91
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
92 58 mohor
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
93 15 mohor
                    );
94
 
95
parameter Tp = 1;
96
 
97
 
98
 
99
input         MRxClk;
100
input         MRxDV;
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input   [3:0] MRxD;
102
input         Transmitting;
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input         HugEn;
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input         DlyCrcEn;
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input  [15:0] MaxFL;
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input         r_IFG;
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input         Reset;
108 53 billditt
input  [47:0] MAC;     //  Station Address  
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input         r_Bro;   //  broadcast disable
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input         r_Pro;   //  promiscuous enable 
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input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
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input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
113 15 mohor
output  [7:0] RxData;
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output        RxValid;
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output        RxStartFrm;
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output        RxEndFrm;
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output [15:0] ByteCnt;
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output        ByteCntEq0;
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output        ByteCntGreat2;
120
output        ByteCntMaxFrame;
121
output        CrcError;
122
output        StateIdle;
123
output        StatePreamble;
124
output        StateSFD;
125
output  [1:0] StateData;
126 53 billditt
output        RxAbort;
127 15 mohor
 
128
reg     [7:0] RxData;
129
reg           RxValid;
130
reg           RxStartFrm;
131
reg           RxEndFrm;
132
reg           Broadcast;
133
reg           Multicast;
134
reg     [8:0] CrcHash;
135
reg           CrcHashGood;
136
reg           DelayData;
137
reg     [3:0] LatchedNibble;
138
reg     [7:0] LatchedByte;
139
reg     [7:0] RxData_d;
140
reg           RxValid_d;
141
reg           RxStartFrm_d;
142
reg           RxEndFrm_d;
143
 
144
wire          MRxDEqD;
145
wire          MRxDEq5;
146
wire          StateDrop;
147
wire          ByteCntEq1;
148 53 billditt
wire          ByteCntEq2;
149
wire          ByteCntEq3;
150
wire          ByteCntEq4;
151
wire          ByteCntEq5;
152 15 mohor
wire          ByteCntEq6;
153 53 billditt
wire          ByteCntEq7;
154 15 mohor
wire          ByteCntSmall7;
155
wire   [31:0] Crc;
156
wire          Enable_Crc;
157
wire          Initialize_Crc;
158
wire    [3:0] Data_Crc;
159
wire          GenerateRxValid;
160
wire          GenerateRxStartFrm;
161
wire          GenerateRxEndFrm;
162
wire          DribbleRxEndFrm;
163
wire    [3:0] DlyCrcCnt;
164
 
165
 
166
assign MRxDEqD = MRxD == 4'hd;
167
assign MRxDEq5 = MRxD == 4'h5;
168
 
169
 
170
// Rx State Machine module
171
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
172
                        .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
173
                        .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
174
                        .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
175
                        .StateSFD(StateSFD), .StateDrop(StateDrop)
176
                       );
177
 
178
 
179
// Rx Counters module
180
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
181
                            .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
182
                            .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
183
                            .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
184
                            .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
185 58 mohor
                            .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
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                            .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
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                            .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
188 15 mohor
                            .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
189
                            .ByteCnt(ByteCnt)
190
                           );
191
 
192 53 billditt
// Rx Address Check
193 15 mohor
 
194 58 mohor
eth_rxaddrcheck rxaddrcheck1
195
              (.MRxClk(MRxClk),         .Reset( Reset),          .RxData(RxData),
196
               .Broadcast (Broadcast),  .r_Bro (r_Bro),          .r_Pro(r_Pro),
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               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
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               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
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               .HASH0(r_HASH0),         .HASH1(r_HASH1),
200
               .CrcHash(CrcHash[5:0]),  .CrcHashGood(CrcHashGood),.StateData(StateData),
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               .Multicast(Multicast),   .MAC(MAC),               .RxAbort(RxAbort),
202
               .RxEndFrm(RxEndFrm)
203
              );
204 15 mohor
 
205 53 billditt
 
206 15 mohor
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
207
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
208
 
209
assign Data_Crc[0] = MRxD[3];
210
assign Data_Crc[1] = MRxD[2];
211
assign Data_Crc[2] = MRxD[1];
212
assign Data_Crc[3] = MRxD[0];
213
 
214
 
215
// Connecting module Crc
216
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
217
               .Crc(Crc), .CrcError(CrcError)
218 58 mohor
              );
219 15 mohor
 
220
 
221
 
222
// Latching CRC for use in the hash table
223
 
224
always @ (posedge MRxClk)
225
begin
226
  CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
227
end
228
 
229
always @ (posedge MRxClk)
230
begin
231
  if(Reset | StateIdle)
232
    CrcHash[8:0] <= #Tp 9'h0;
233
  else
234
  if(StateData[0] & ByteCntEq6)
235
    CrcHash[8:0] <= #Tp Crc[31:23];
236
end
237
 
238
 
239
// Output byte stream
240
always @ (posedge MRxClk or posedge Reset)
241
begin
242
  if(Reset)
243
    begin
244
      RxData_d[7:0]      <= #Tp 8'h0;
245
      DelayData          <= #Tp 1'b0;
246
      LatchedNibble[3:0] <= #Tp 4'h0;
247
      LatchedByte[7:0]   <= #Tp 8'h0;
248
      RxData[7:0]        <= #Tp 8'h0;
249
    end
250
  else
251
    begin
252
      LatchedNibble[3:0] <= #Tp MRxD[3:0];                        // Latched nibble
253
      LatchedByte[7:0]   <= #Tp {MRxD[3:0], LatchedNibble[3:0]};  // Latched byte
254
      DelayData          <= #Tp StateData[0];
255
 
256
      if(GenerateRxValid)
257
        RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}};  // Data goes through only in data state 
258
      else
259
      if(~DelayData)
260
        RxData_d[7:0] <= #Tp 8'h0;                                // Delaying data to be valid for two cycles. Zero when not active.
261
 
262
      RxData[7:0] <= #Tp RxData_d[7:0];                           // Output data byte
263
    end
264
end
265
 
266
 
267
 
268
always @ (posedge MRxClk or posedge Reset)
269
begin
270
  if(Reset)
271
    Broadcast <= #Tp 1'b0;
272
  else
273
    begin
274
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
275
        Broadcast <= #Tp 1'b0;
276
      else
277 18 mohor
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
278 15 mohor
        Broadcast <= #Tp 1'b1;
279 58 mohor
      else
280
      if(RxAbort | RxEndFrm)
281
        Broadcast <= #Tp 1'b0;
282 15 mohor
    end
283
end
284
 
285
 
286
always @ (posedge MRxClk or posedge Reset)
287
begin
288
  if(Reset)
289
    Multicast <= #Tp 1'b0;
290
  else
291
    begin
292
      if(Reset)
293
        Multicast <= #Tp 1'b0;
294
      else
295 53 billditt
      if(StateData[0] & ByteCntEq1 & LatchedByte == 8'h01)
296
        Multicast <= #Tp 1'b1;
297 58 mohor
    else if(RxAbort | RxEndFrm)
298
      Multicast <= #Tp 1'b0;
299 15 mohor
    end
300
end
301
 
302
 
303
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
304
 
305
always @ (posedge MRxClk or posedge Reset)
306
begin
307
  if(Reset)
308
    begin
309
      RxValid_d <= #Tp 1'b0;
310
      RxValid   <= #Tp 1'b0;
311
    end
312
  else
313
    begin
314
      RxValid_d <= #Tp GenerateRxValid;
315
      RxValid   <= #Tp RxValid_d;
316
    end
317
end
318
 
319
 
320
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
321
 
322
always @ (posedge MRxClk or posedge Reset)
323
begin
324
  if(Reset)
325
    begin
326
      RxStartFrm_d <= #Tp 1'b0;
327
      RxStartFrm   <= #Tp 1'b0;
328
    end
329
  else
330
    begin
331
      RxStartFrm_d <= #Tp GenerateRxStartFrm;
332
      RxStartFrm   <= #Tp RxStartFrm_d;
333
    end
334
end
335
 
336
 
337
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
338
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
339
 
340
 
341
always @ (posedge MRxClk or posedge Reset)
342
begin
343
  if(Reset)
344
    begin
345
      RxEndFrm_d <= #Tp 1'b0;
346
      RxEndFrm   <= #Tp 1'b0;
347
    end
348
  else
349
    begin
350
      RxEndFrm_d <= #Tp GenerateRxEndFrm;
351
      RxEndFrm   <= #Tp RxEndFrm_d | DribbleRxEndFrm;
352
    end
353
end
354
 
355
 
356
endmodule

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