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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.51  2005/02/21 11:13:17  igorm
45
// Defer indication fixed.
46
//
47 327 igorm
// Revision 1.50  2004/04/26 15:26:23  igorm
48
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
49
//   previous update of the core.
50
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
51
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
52
//   register. (thanks to Mathias and Torbjorn)
53
// - Multicast reception was fixed. Thanks to Ulrich Gries
54
//
55 321 igorm
// Revision 1.49  2003/11/12 18:24:59  tadejm
56
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
57
//
58 304 tadejm
// Revision 1.48  2003/10/17 07:46:16  markom
59
// mbist signals updated according to newest convention
60
//
61 302 markom
// Revision 1.47  2003/10/06 15:43:45  knguyen
62
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
63
//
64 301 knguyen
// Revision 1.46  2003/01/30 13:30:22  tadejm
65
// Defer indication changed.
66
//
67 276 tadejm
// Revision 1.45  2003/01/22 13:49:26  tadejm
68
// When control packets were received, they were ignored in some cases.
69
//
70 272 tadejm
// Revision 1.44  2003/01/21 12:09:40  mohor
71
// When receiving normal data frame and RxFlow control was switched on, RXB
72
// interrupt was not set.
73
//
74 270 mohor
// Revision 1.43  2002/11/22 01:57:06  mohor
75
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
76
// synchronized.
77
//
78 261 mohor
// Revision 1.42  2002/11/21 00:09:19  mohor
79
// TPauseRq synchronized to tx_clk.
80
//
81 255 mohor
// Revision 1.41  2002/11/19 18:13:49  mohor
82
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
83
//
84 253 mohor
// Revision 1.40  2002/11/19 17:34:25  mohor
85
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
86
// that a frame was received because of the promiscous mode.
87
//
88 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
89
// wb_rst_i is used for MIIM reset.
90
//
91 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
92
// r_Rst signal does not reset any module any more and is removed from the design.
93
//
94 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
95
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
96
//
97 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
98
// Changed BIST scan signals.
99
//
100 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
101
// Typo error fixed. (When using Bist)
102
//
103 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
104
// Signals for WISHBONE B3 compliant interface added.
105
//
106 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
107
// BIST added.
108
//
109 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
110
// CsMiss added. When address between 0x800 and 0xfff is accessed within
111
// Ethernet Core, error acknowledge is generated.
112
//
113 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
114
// CarrierSenseLost bug fixed when operating in full duplex mode.
115
//
116 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
117
// Ethernet debug registers removed.
118
//
119 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
120
// Error acknowledge is generated when accessing BDs and RST bit in the
121
// MODER register (r_Rst) is set.
122
//
123 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
124
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
125
// connected.
126
//
127 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
128
// RxAbort changed. Packets received with MRxErr (from PHY) are also
129
// aborted.
130
//
131 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
132
// EXTERNAL_DMA removed. External DMA not supported.
133
//
134 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
135
// Outputs registered. Reset changed for eth_wishbone module.
136
//
137 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
138
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
139
// selected in eth_defines.v
140
//
141 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
142
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
143
// name was incorrect.
144
//
145 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
146
// Small fixes for external/internal DMA missmatches.
147
//
148 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
149
// Interrupts changed in the top file
150
//
151 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
152
// Small fixes.
153
//
154 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
155
// Registered trimmed. Unused registers removed.
156
//
157 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
158
// EXTERNAL_DMA used instead of WISHBONE_DMA.
159
//
160 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
161
// Testbench fixed, code simplified, unused signals removed.
162
//
163 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
164
// RxAbort is connected differently.
165
//
166 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
167
// Changes that were lost when updating from 1.11 to 1.14 fixed.
168
//
169 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
170
// Modified for Address Checking,
171
// addition of eth_addrcheck.v
172
//
173
// Revision 1.13  2002/02/12 17:03:03  mohor
174
// HASH0 and HASH1 registers added. Registers address width was
175
// changed to 8 bits.
176
//
177
// Revision 1.12  2002/02/11 09:18:22  mohor
178
// Tx status is written back to the BD.
179
//
180 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
181
// Rx status is written back to the BD.
182
//
183 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
184
// non-DMA host interface added. Select the right configutation in eth_defines.
185
//
186 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
187
// Link in the header changed.
188
//
189 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
190
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
191
// instead of the number of RX descriptors).
192
//
193 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
194
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
195
//
196 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
197
// Number of addresses (wb_adr_i) minimized.
198
//
199 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
200
// eth_timescale.v changed to timescale.v This is done because of the
201
// simulation of the few cores in a one joined project.
202
//
203 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
204
// Status signals changed, Adress decoding changed, interrupt controller
205
// added.
206
//
207 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
208
// Defines changed (All precede with ETH_). Small changes because some
209
// tools generate warnings when two operands are together. Synchronization
210
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
211
// demands).
212
//
213 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
214
// Signal names changed on the top level for easier pad insertion (ASIC).
215
//
216 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
217
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
218
// Include files fixed to contain no path.
219
// File names and module names changed ta have a eth_ prologue in the name.
220
// File eth_timescale.v is used to define timescale
221
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
222
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
223
// and Mdo_OE. The bidirectional signal must be created on the top level. This
224
// is done due to the ASIC tools.
225
//
226 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
227
// Unconnected signals are now connected.
228
//
229
// Revision 1.1  2001/07/30 21:23:42  mohor
230
// Directory structure changed. Files checked and joind together.
231
//
232
//
233
//
234 20 mohor
// 
235 15 mohor
 
236
 
237
`include "eth_defines.v"
238 22 mohor
`include "timescale.v"
239 15 mohor
 
240
 
241
module eth_top
242
(
243
  // WISHBONE common
244 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
245 15 mohor
 
246
  // WISHBONE slave
247 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
248 15 mohor
 
249 41 mohor
  // WISHBONE master
250
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
251
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
252
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
253
 
254 214 mohor
`ifdef ETH_WISHBONE_B3
255
  m_wb_cti_o, m_wb_bte_o,
256
`endif
257
 
258 15 mohor
  //TX
259 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
260 15 mohor
 
261
  //RX
262 20 mohor
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
263 15 mohor
 
264
  // MIIM
265 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
266 17 mohor
 
267 21 mohor
  int_o
268 17 mohor
 
269 210 mohor
  // Bist
270
`ifdef ETH_BIST
271 227 tadejm
  ,
272
  // debug chain signals
273 302 markom
  mbist_si_i,       // bist scan serial in
274
  mbist_so_o,       // bist scan serial out
275
  mbist_ctrl_i        // bist chain shift control
276 210 mohor
`endif
277 21 mohor
 
278 15 mohor
);
279
 
280
 
281 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
282
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
283
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
284
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
285
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
286
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
287 15 mohor
 
288
 
289
// WISHBONE common
290 17 mohor
input           wb_clk_i;     // WISHBONE clock
291
input           wb_rst_i;     // WISHBONE reset
292
input   [31:0]  wb_dat_i;     // WISHBONE data input
293
output  [31:0]  wb_dat_o;     // WISHBONE data output
294
output          wb_err_o;     // WISHBONE error output
295 15 mohor
 
296
// WISHBONE slave
297 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
298 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
299
input           wb_we_i;      // WISHBONE write enable input
300
input           wb_cyc_i;     // WISHBONE cycle input
301
input           wb_stb_i;     // WISHBONE strobe input
302
output          wb_ack_o;     // WISHBONE acknowledge output
303 15 mohor
 
304 41 mohor
// WISHBONE master
305
output  [31:0]  m_wb_adr_o;
306
output   [3:0]  m_wb_sel_o;
307
output          m_wb_we_o;
308
input   [31:0]  m_wb_dat_i;
309
output  [31:0]  m_wb_dat_o;
310
output          m_wb_cyc_o;
311
output          m_wb_stb_o;
312
input           m_wb_ack_i;
313
input           m_wb_err_i;
314 15 mohor
 
315 327 igorm
wire    [29:0]  m_wb_adr_tmp;
316
 
317 214 mohor
`ifdef ETH_WISHBONE_B3
318
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
319
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
320
`endif
321 41 mohor
 
322 15 mohor
// Tx
323 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
324 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
325
output          mtxen_pad_o;   // Transmit enable (to PHY)
326
output          mtxerr_pad_o;  // Transmit error (to PHY)
327 15 mohor
 
328
// Rx
329 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
330 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
331
input           mrxdv_pad_i;   // Receive data valid (from PHY)
332
input           mrxerr_pad_i;  // Receive data error (from PHY)
333 15 mohor
 
334
// Common Tx and Rx
335 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
336
input           mcrs_pad_i;    // Carrier sense (from PHY)
337 15 mohor
 
338
// MII Management interface
339 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
340
output          mdc_pad_o;     // MII Management data clock (to PHY)
341
output          md_pad_o;      // MII data output (to I/O cell)
342 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
343 15 mohor
 
344 21 mohor
output          int_o;         // Interrupt output
345 15 mohor
 
346 210 mohor
// Bist
347
`ifdef ETH_BIST
348 302 markom
input   mbist_si_i;       // bist scan serial in
349
output  mbist_so_o;       // bist scan serial out
350
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
351 210 mohor
`endif
352
 
353 15 mohor
wire     [7:0]  r_ClkDiv;
354
wire            r_MiiNoPre;
355
wire    [15:0]  r_CtrlData;
356
wire     [4:0]  r_FIAD;
357
wire     [4:0]  r_RGAD;
358
wire            r_WCtrlData;
359
wire            r_RStat;
360
wire            r_ScanStat;
361
wire            NValid_stat;
362
wire            Busy_stat;
363
wire            LinkFail;
364
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
365
wire            WCtrlDataStart;
366
wire            RStatStart;
367
wire            UpdateMIIRX_DATAReg;
368
 
369
wire            TxStartFrm;
370
wire            TxEndFrm;
371
wire            TxUsedData;
372
wire     [7:0]  TxData;
373
wire            TxRetry;
374
wire            TxAbort;
375
wire            TxUnderRun;
376
wire            TxDone;
377
 
378
 
379 149 mohor
reg             WillSendControlFrame_sync1;
380
reg             WillSendControlFrame_sync2;
381
reg             WillSendControlFrame_sync3;
382
reg             RstTxPauseRq;
383 15 mohor
 
384 255 mohor
reg             TxPauseRq_sync1;
385
reg             TxPauseRq_sync2;
386
reg             TxPauseRq_sync3;
387
reg             TPauseRq;
388 15 mohor
 
389 255 mohor
 
390 15 mohor
// Connecting Miim module
391 352 olof
eth_miim miim1
392 15 mohor
(
393 248 mohor
  .Clk(wb_clk_i),                         .Reset(wb_rst_i),                   .Divider(r_ClkDiv),
394 15 mohor
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
395
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
396 17 mohor
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
397 95 mohor
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
398 15 mohor
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
399
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
400
);
401
 
402
 
403
 
404
 
405 304 tadejm
wire  [3:0] RegCs;          // Connected to registers
406 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
407 42 mohor
wire        r_RecSmall;     // Receive small frames
408 15 mohor
wire        r_LoopBck;      // Loopback
409
wire        r_TxEn;         // Tx Enable
410
wire        r_RxEn;         // Rx Enable
411
 
412
wire        MRxDV_Lb;       // Muxed MII receive data valid
413
wire        MRxErr_Lb;      // Muxed MII Receive Error
414
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
415
wire        Transmitting;   // Indication that TxEthMAC is transmitting
416
wire        r_HugEn;        // Huge packet enable
417
wire        r_DlyCrcEn;     // Delayed CRC enabled
418
wire [15:0] r_MaxFL;        // Maximum frame length
419
 
420
wire [15:0] r_MinFL;        // Minimum frame length
421 42 mohor
wire        ShortFrame;
422
wire        DribbleNibble;  // Extra nibble received
423
wire        ReceivedPacketTooBig; // Received packet is too big
424 15 mohor
wire [47:0] r_MAC;          // MAC address
425 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
426 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
427
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
428 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
429 15 mohor
wire  [6:0] r_IPGT;         // 
430
wire  [6:0] r_IPGR1;        // 
431
wire  [6:0] r_IPGR2;        // 
432
wire  [5:0] r_CollValid;    // 
433 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
434
wire        r_TxPauseRq;    // Transmit PAUSE request
435 15 mohor
 
436
wire  [3:0] r_MaxRet;       //
437
wire        r_NoBckof;      // 
438
wire        r_ExDfrEn;      // 
439
wire        r_TxFlow;       // Tx flow control enable
440
wire        r_IFG;          // Minimum interframe gap for incoming packets
441
 
442 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
443
wire        TxE_IRQ;        // Interrupt Tx Error
444
wire        RxB_IRQ;        // Interrupt Rx Buffer
445 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
446 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
447 15 mohor
 
448 304 tadejm
//wire        DWord;
449
wire        ByteSelected;
450 15 mohor
wire        BDAck;
451 103 mohor
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
452 304 tadejm
wire  [3:0] BDCs;           // Buffer descriptor CS
453 202 mohor
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
454
                            // but data is not valid.
455 327 igorm
wire        r_Pad;
456
wire        r_CrcEn;
457
wire        r_FullD;
458
wire        r_Pro;
459
wire        r_Bro;
460
wire        r_NoPre;
461
wire        r_RxFlow;
462
wire        r_PassAll;
463
wire        TxCtrlEndFrm;
464
wire        StartTxDone;
465
wire        SetPauseTimer;
466
wire        TxUsedDataIn;
467
wire        TxDoneIn;
468
wire        TxAbortIn;
469
wire        PerPacketPad;
470
wire        PadOut;
471
wire        PerPacketCrcEn;
472
wire        CrcEnOut;
473
wire        TxStartFrmOut;
474
wire        TxEndFrmOut;
475
wire        ReceivedPauseFrm;
476
wire        ControlFrmAddressOK;
477
wire        RxStatusWriteLatched_sync2;
478
wire        LateCollision;
479
wire        DeferIndication;
480
wire        LateCollLatched;
481
wire        DeferLatched;
482
wire        RstDeferLatched;
483
wire        CarrierSenseLost;
484 15 mohor
 
485 103 mohor
wire        temp_wb_ack_o;
486
wire [31:0] temp_wb_dat_o;
487
wire        temp_wb_err_o;
488 15 mohor
 
489 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
490
  reg         temp_wb_ack_o_reg;
491
  reg [31:0]  temp_wb_dat_o_reg;
492
  reg         temp_wb_err_o_reg;
493
`endif
494
 
495 304 tadejm
//assign DWord = &wb_sel_i;
496
assign ByteSelected = |wb_sel_i;
497
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3];   // 0x0   - 0x3FF
498
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2];   // 0x0   - 0x3FF
499
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1];   // 0x0   - 0x3FF
500
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0];   // 0x0   - 0x3FF
501
assign BDCs[3]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[3];   // 0x400 - 0x7FF
502
assign BDCs[2]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[2];   // 0x400 - 0x7FF
503
assign BDCs[1]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[1];   // 0x400 - 0x7FF
504
assign BDCs[0]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[0];   // 0x400 - 0x7FF
505
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11];                   // 0x800 - 0xfFF
506
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
507
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
508 15 mohor
 
509 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
510
  assign wb_ack_o = temp_wb_ack_o_reg;
511
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
512
  assign wb_err_o = temp_wb_err_o_reg;
513
`else
514
  assign wb_ack_o = temp_wb_ack_o;
515
  assign wb_dat_o[31:0] = temp_wb_dat_o;
516
  assign wb_err_o = temp_wb_err_o;
517
`endif
518 15 mohor
 
519 327 igorm
`ifdef ETH_AVALON_BUS
520
  // As Avalon has no corresponding "error" signal, I (erroneously) will
521
  // send an ack to Avalon, even when accessing undefined memory. This
522
  // is a grey area in Avalon vs. Wishbone specs: My understanding
523
  // is that Avalon expects all memory addressable by the addr bus feeding
524
  // a slave to be, at the very minimum, readable.
525
  assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
526
`else // WISHBONE
527
  assign temp_wb_ack_o = (|RegCs) | BDAck;
528
`endif
529 15 mohor
 
530 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
531
  always @ (posedge wb_clk_i or posedge wb_rst_i)
532
  begin
533
    if(wb_rst_i)
534
      begin
535 352 olof
        temp_wb_ack_o_reg <= 1'b0;
536
        temp_wb_dat_o_reg <= 32'h0;
537
        temp_wb_err_o_reg <= 1'b0;
538 103 mohor
      end
539
    else
540
      begin
541 352 olof
        temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
542
        temp_wb_dat_o_reg <= temp_wb_dat_o;
543
        temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
544 103 mohor
      end
545
  end
546
`endif
547
 
548
 
549 15 mohor
// Connecting Ethernet registers
550 352 olof
eth_registers ethreg1
551 15 mohor
(
552 47 mohor
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
553 17 mohor
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
554 68 mohor
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
555 15 mohor
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
556 244 mohor
  .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),
557 15 mohor
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
558 52 billditt
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
559
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
560 76 mohor
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
561 21 mohor
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
562 149 mohor
  .r_IPGT(r_IPGT),
563 15 mohor
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
564
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
565
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
566 253 mohor
  .r_MiiNoPre(r_MiiNoPre),                .r_ClkDiv(r_ClkDiv),
567 15 mohor
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
568
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
569
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
570
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
571
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
572 321 igorm
  .r_TxBDNum(r_TxBDNum),                  .int_o(int_o),
573 149 mohor
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
574
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
575
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
576 261 mohor
  .SetPauseTimer(SetPauseTimer)
577 149 mohor
 
578 15 mohor
);
579
 
580
 
581
 
582
wire  [7:0] RxData;
583
wire        RxValid;
584
wire        RxStartFrm;
585
wire        RxEndFrm;
586 41 mohor
wire        RxAbort;
587 15 mohor
 
588
wire        WillTransmit;            // Will transmit (to RxEthMAC)
589
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
590
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
591
wire        WillSendControlFrame;
592
wire        ReceiveEnd;
593
wire        ReceivedPacketGood;
594
wire        ReceivedLengthOK;
595 42 mohor
wire        InvalidSymbol;
596
wire        LatchedCrcError;
597
wire        RxLateCollision;
598 59 mohor
wire  [3:0] RetryCntLatched;
599
wire  [3:0] RetryCnt;
600
wire        StartTxAbort;
601
wire        MaxCollisionOccured;
602
wire        RetryLimit;
603
wire        StatePreamble;
604
wire  [1:0] StateData;
605 15 mohor
 
606
// Connecting MACControl
607 352 olof
eth_maccontrol maccontrol1
608 15 mohor
(
609 255 mohor
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(TPauseRq),
610 149 mohor
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
611 15 mohor
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
612
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
613 20 mohor
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
614 15 mohor
  .RxData(RxData),                              .RxValid(RxValid),
615
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
616
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
617 261 mohor
  .TxFlow(r_TxFlow),
618 15 mohor
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
619
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
620
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
621 240 tadejm
  .CrcEnOut(CrcEnOut),                          .TxReset(wb_rst_i),
622
  .RxReset(wb_rst_i),                           .ReceivedLengthOK(ReceivedLengthOK),
623 15 mohor
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
624
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
625
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
626
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
627 261 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm),          .ControlFrmAddressOK(ControlFrmAddressOK),
628 272 tadejm
  .SetPauseTimer(SetPauseTimer),
629
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),                .r_PassAll(r_PassAll)
630 15 mohor
);
631
 
632
 
633
 
634
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
635
wire Collision;               // Synchronized Collision
636
 
637
reg CarrierSense_Tx1;
638
reg CarrierSense_Tx2;
639
reg Collision_Tx1;
640
reg Collision_Tx2;
641
 
642
reg RxEnSync;                 // Synchronized Receive Enable
643
reg WillTransmit_q;
644
reg WillTransmit_q2;
645
 
646
 
647
 
648
// Muxed MII receive data valid
649 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
650 15 mohor
 
651
// Muxed MII Receive Error
652 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
653 15 mohor
 
654
// Muxed MII Receive Data
655 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
656 15 mohor
 
657
 
658
 
659
// Connecting TxEthMAC
660 352 olof
eth_txethmac txethmac1
661 15 mohor
(
662 240 tadejm
  .MTxClk(mtx_clk_pad_i),             .Reset(wb_rst_i),                   .CarrierSense(TxCarrierSense),
663 15 mohor
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
664
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
665
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
666
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
667
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
668
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
669 17 mohor
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
670
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
671 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
672 59 mohor
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
673
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
674 276 tadejm
  .DeferIndication(DeferIndication),  .StatePreamble(StatePreamble),      .StateData(StateData)
675 15 mohor
);
676
 
677
 
678
 
679
 
680
wire  [15:0]  RxByteCnt;
681
wire          RxByteCntEq0;
682
wire          RxByteCntGreat2;
683
wire          RxByteCntMaxFrame;
684
wire          RxCrcError;
685
wire          RxStateIdle;
686
wire          RxStatePreamble;
687
wire          RxStateSFD;
688
wire   [1:0]  RxStateData;
689 250 mohor
wire          AddressMiss;
690 15 mohor
 
691
 
692
 
693
// Connecting RxEthMAC
694 352 olof
eth_rxethmac rxethmac1
695 15 mohor
(
696 21 mohor
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
697 15 mohor
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
698 240 tadejm
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(wb_rst_i),
699 15 mohor
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
700 65 mohor
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
701 15 mohor
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
702
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
703 52 billditt
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
704 63 mohor
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
705 250 mohor
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort),
706 261 mohor
  .AddressMiss(AddressMiss),            .PassAll(r_PassAll),                  .ControlFrmAddressOK(ControlFrmAddressOK)
707 15 mohor
);
708
 
709
 
710
// MII Carrier Sense Synchronization
711 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
712 15 mohor
begin
713 240 tadejm
  if(wb_rst_i)
714 15 mohor
    begin
715 352 olof
      CarrierSense_Tx1 <=  1'b0;
716
      CarrierSense_Tx2 <=  1'b0;
717 15 mohor
    end
718
  else
719
    begin
720 352 olof
      CarrierSense_Tx1 <=  mcrs_pad_i;
721
      CarrierSense_Tx2 <=  CarrierSense_Tx1;
722 15 mohor
    end
723
end
724
 
725
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
726
 
727
 
728
// MII Collision Synchronization
729 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
730 15 mohor
begin
731 240 tadejm
  if(wb_rst_i)
732 15 mohor
    begin
733 352 olof
      Collision_Tx1 <=  1'b0;
734
      Collision_Tx2 <=  1'b0;
735 15 mohor
    end
736
  else
737
    begin
738 352 olof
      Collision_Tx1 <=  mcoll_pad_i;
739 15 mohor
      if(ResetCollision)
740 352 olof
        Collision_Tx2 <=  1'b0;
741 15 mohor
      else
742
      if(Collision_Tx1)
743 352 olof
        Collision_Tx2 <=  1'b1;
744 15 mohor
    end
745
end
746
 
747
 
748
// Synchronized Collision
749
assign Collision = ~r_FullD & Collision_Tx2;
750
 
751
 
752
 
753
// Delayed WillTransmit
754 20 mohor
always @ (posedge mrx_clk_pad_i)
755 15 mohor
begin
756 352 olof
  WillTransmit_q <=  WillTransmit;
757
  WillTransmit_q2 <=  WillTransmit_q;
758 15 mohor
end
759
 
760
 
761
assign Transmitting = ~r_FullD & WillTransmit_q2;
762
 
763
 
764
 
765
// Synchronized Receive Enable
766 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
767 15 mohor
begin
768 240 tadejm
  if(wb_rst_i)
769 352 olof
    RxEnSync <=  1'b0;
770 15 mohor
  else
771 301 knguyen
  if(~mrxdv_pad_i)
772 352 olof
    RxEnSync <=  r_RxEn;
773 15 mohor
end
774
 
775
 
776
 
777 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
778
always @ (posedge wb_clk_i or posedge wb_rst_i)
779
begin
780
  if(wb_rst_i)
781
    WillSendControlFrame_sync1 <= 1'b0;
782
  else
783 352 olof
    WillSendControlFrame_sync1 <= WillSendControlFrame;
784 149 mohor
end
785 15 mohor
 
786 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
787
begin
788
  if(wb_rst_i)
789
    WillSendControlFrame_sync2 <= 1'b0;
790
  else
791 352 olof
    WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
792 149 mohor
end
793
 
794
always @ (posedge wb_clk_i or posedge wb_rst_i)
795
begin
796
  if(wb_rst_i)
797
    WillSendControlFrame_sync3 <= 1'b0;
798
  else
799 352 olof
    WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
800 149 mohor
end
801
 
802
always @ (posedge wb_clk_i or posedge wb_rst_i)
803
begin
804
  if(wb_rst_i)
805
    RstTxPauseRq <= 1'b0;
806
  else
807 352 olof
    RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
808 149 mohor
end
809
 
810
 
811 255 mohor
 
812
 
813
// TX Pause request Synchronization
814
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
815
begin
816
  if(wb_rst_i)
817
    begin
818 352 olof
      TxPauseRq_sync1 <=  1'b0;
819
      TxPauseRq_sync2 <=  1'b0;
820
      TxPauseRq_sync3 <=  1'b0;
821 255 mohor
    end
822
  else
823
    begin
824 352 olof
      TxPauseRq_sync1 <=  (r_TxPauseRq & r_TxFlow);
825
      TxPauseRq_sync2 <=  TxPauseRq_sync1;
826
      TxPauseRq_sync3 <=  TxPauseRq_sync2;
827 255 mohor
    end
828
end
829
 
830
 
831
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
832
begin
833
  if(wb_rst_i)
834 352 olof
    TPauseRq <=  1'b0;
835 255 mohor
  else
836 352 olof
    TPauseRq <=  TxPauseRq_sync2 & (~TxPauseRq_sync3);
837 255 mohor
end
838
 
839
 
840 261 mohor
wire LatchedMRxErr;
841
reg RxAbort_latch;
842
reg RxAbort_sync1;
843
reg RxAbort_wb;
844
reg RxAbortRst_sync1;
845
reg RxAbortRst;
846 255 mohor
 
847 261 mohor
// Synchronizing RxAbort to the WISHBONE clock
848
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
849
begin
850
  if(wb_rst_i)
851 352 olof
    RxAbort_latch <=  1'b0;
852 261 mohor
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
853 352 olof
    RxAbort_latch <=  1'b1;
854 261 mohor
  else if(RxAbortRst)
855 352 olof
    RxAbort_latch <=  1'b0;
856 261 mohor
end
857 255 mohor
 
858 261 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
859
begin
860
  if(wb_rst_i)
861
    begin
862 352 olof
      RxAbort_sync1 <=  1'b0;
863
      RxAbort_wb    <=  1'b0;
864
      RxAbort_wb    <=  1'b0;
865 261 mohor
    end
866
  else
867
    begin
868 352 olof
      RxAbort_sync1 <=  RxAbort_latch;
869
      RxAbort_wb    <=  RxAbort_sync1;
870 261 mohor
    end
871
end
872
 
873
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
874
begin
875
  if(wb_rst_i)
876
    begin
877 352 olof
      RxAbortRst_sync1 <=  1'b0;
878
      RxAbortRst       <=  1'b0;
879 261 mohor
    end
880
  else
881
    begin
882 352 olof
      RxAbortRst_sync1 <=  RxAbort_wb;
883
      RxAbortRst       <=  RxAbortRst_sync1;
884 261 mohor
    end
885
end
886
 
887
 
888
 
889 114 mohor
// Connecting Wishbone module
890 352 olof
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
891 349 olof
               .TX_FIFO_DEPTH     (TX_FIFO_DEPTH),
892
               .TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
893
               .RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
894
               .RX_FIFO_DEPTH     (RX_FIFO_DEPTH),
895
               .RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
896
wishbone
897 15 mohor
(
898 41 mohor
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
899 103 mohor
  .WB_DAT_O(BD_WB_DAT_O),
900 15 mohor
 
901
  // WISHBONE slave
902 76 mohor
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
903 21 mohor
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
904 15 mohor
 
905 240 tadejm
  .Reset(wb_rst_i),
906 41 mohor
 
907
  // WISHBONE master
908 327 igorm
  .m_wb_adr_o(m_wb_adr_tmp),          .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
909 41 mohor
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
910
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
911 214 mohor
 
912
`ifdef ETH_WISHBONE_B3
913
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
914
`endif
915
 
916 41 mohor
 
917 15 mohor
    //TX
918 21 mohor
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
919 59 mohor
  .TxUsedData(TxUsedData),            .TxData(TxData),
920 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
921 149 mohor
  .TxDone(TxDone),
922
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
923 15 mohor
 
924
  // Register
925 34 mohor
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
926 321 igorm
  .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
927 15 mohor
 
928
  //RX
929 21 mohor
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
930 41 mohor
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
931 76 mohor
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
932 149 mohor
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
933 21 mohor
 
934 272 tadejm
  .RxAbort(RxAbort_wb),               .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
935 41 mohor
 
936 42 mohor
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
937
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
938 59 mohor
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
939
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
940 327 igorm
  .RstDeferLatched(RstDeferLatched),
941 261 mohor
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
942
  .ReceivedPauseFrm(ReceivedPauseFrm)
943 59 mohor
 
944 210 mohor
`ifdef ETH_BIST
945 218 mohor
  ,
946 302 markom
  .mbist_si_i       (mbist_si_i),
947
  .mbist_so_o       (mbist_so_o),
948
  .mbist_ctrl_i       (mbist_ctrl_i)
949 210 mohor
`endif
950 15 mohor
);
951
 
952 327 igorm
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
953 15 mohor
 
954
// Connecting MacStatus module
955 352 olof
eth_macstatus macstatus1
956 15 mohor
(
957 240 tadejm
  .MRxClk(mrx_clk_pad_i),             .Reset(wb_rst_i),
958 42 mohor
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
959
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
960
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
961
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
962
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
963 261 mohor
  .InvalidSymbol(InvalidSymbol),
964 42 mohor
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
965
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
966
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
967
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
968 59 mohor
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
969
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
970
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
971 276 tadejm
  .LateCollLatched(LateCollLatched),  .DeferIndication(DeferIndication),           .DeferLatched(DeferLatched),
972 327 igorm
  .RstDeferLatched(RstDeferLatched),
973 59 mohor
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
974 125 mohor
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
975 168 mohor
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
976 15 mohor
);
977
 
978
 
979
endmodule

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