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[/] [ethmac/] [tags/] [rel_1/] [rtl/] [verilog/] [eth_defines.v] - Blame information for rev 29

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_defines.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/10/18 12:07:11  mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2  2001/09/24 15:02:56  mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
// Selection of the used memory
//`define XILINX_RAMB4                // Core is going to be implemented in Virtex FPGA and contains Virtex 
                                      // specific elements. 
 
//`define ARTISAN_SDP                 // Core is going to be implemented in ASIC (using Artisan RAM)
 
 
`define ETH_MODER_ADR         6'h0    // 0x0 
`define ETH_INT_SOURCE_ADR    6'h1    // 0x4 
`define ETH_INT_MASK_ADR      6'h2    // 0x8 
`define ETH_IPGT_ADR          6'h3    // 0xC 
`define ETH_IPGR1_ADR         6'h4    // 0x10
`define ETH_IPGR2_ADR         6'h5    // 0x14
`define ETH_PACKETLEN_ADR     6'h6    // 0x18
`define ETH_COLLCONF_ADR      6'h7    // 0x1C
`define ETH_RX_BD_ADR_ADR     6'h8    // 0x20
`define ETH_CTRLMODER_ADR     6'h9    // 0x24
`define ETH_MIIMODER_ADR      6'hA    // 0x28
`define ETH_MIICOMMAND_ADR    6'hB    // 0x2C
`define ETH_MIIADDRESS_ADR    6'hC    // 0x30
`define ETH_MIITX_DATA_ADR    6'hD    // 0x34
`define ETH_MIIRX_DATA_ADR    6'hE    // 0x38
`define ETH_MIISTATUS_ADR     6'hF    // 0x3C
`define ETH_MAC_ADDR0_ADR     6'h10   // 0x40
`define ETH_MAC_ADDR1_ADR     6'h11   // 0x44
 
 
 
`define ETH_MODER_DEF         32'h0000A000
`define ETH_INT_SOURCE_DEF    32'h00000000
`define ETH_INT_MASK_DEF      32'h00000000
`define ETH_IPGT_DEF          32'h00000012
`define ETH_IPGR1_DEF         32'h0000000C
`define ETH_IPGR2_DEF         32'h00000012
`define ETH_PACKETLEN_DEF     32'h003C0600
`define ETH_COLLCONF_DEF      32'h000F0040
`define ETH_CTRLMODER_DEF     32'h00000000
`define ETH_MIIMODER_DEF      32'h00000064
`define ETH_MIICOMMAND_DEF    32'h00000000
`define ETH_MIIADDRESS_DEF    32'h00000000
`define ETH_MIITX_DATA_DEF    32'h00000000
`define ETH_MIIRX_DATA_DEF    32'h00000000
`define ETH_MIISTATUS_DEF     32'h00000000
`define ETH_MAC_ADDR0_DEF     32'h00000000
`define ETH_MAC_ADDR1_DEF     32'h00000000
 
`define ETH_RX_BD_ADR_DEF     8'h0

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_defines.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	29	mohor	`// Revision 1.3 2001/10/18 12:07:11 mohor`
45			`// Status signals changed, Adress decoding changed, interrupt controller`
46			`// added.`
47			`//`
48	21	mohor	`// Revision 1.2 2001/09/24 15:02:56 mohor`
49			`// Defines changed (All precede with ETH_). Small changes because some`
50			`// tools generate warnings when two operands are together. Synchronization`
51			`// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC`
52			`// demands).`
53			`//`
54	20	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
55			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
56			`// Include files fixed to contain no path.`
57			`// File names and module names changed ta have a eth_ prologue in the name.`
58			`// File eth_timescale.v is used to define timescale`
59			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
60			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
61			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
62			`// is done due to the ASIC tools.`
63			`//`
64	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
65			`// Directory structure changed. Files checked and joind together.`
66			`//`
67			`//`
68			`//`
69			`//`
70			`//`
71
72	29	mohor	`// Selection of the used memory`
73			//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
74			`// specific elements.`
75	15	mohor
76	29	mohor	//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
77	15	mohor
78
79	21	mohor	`define ETH_MODER_ADR 6'h0 // 0x0
80			`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
81			`define ETH_INT_MASK_ADR 6'h2 // 0x8
82			`define ETH_IPGT_ADR 6'h3 // 0xC
83			`define ETH_IPGR1_ADR 6'h4 // 0x10
84			`define ETH_IPGR2_ADR 6'h5 // 0x14
85			`define ETH_PACKETLEN_ADR 6'h6 // 0x18
86			`define ETH_COLLCONF_ADR 6'h7 // 0x1C
87			`define ETH_RX_BD_ADR_ADR 6'h8 // 0x20
88			`define ETH_CTRLMODER_ADR 6'h9 // 0x24
89			`define ETH_MIIMODER_ADR 6'hA // 0x28
90			`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
91			`define ETH_MIIADDRESS_ADR 6'hC // 0x30
92			`define ETH_MIITX_DATA_ADR 6'hD // 0x34
93			`define ETH_MIIRX_DATA_ADR 6'hE // 0x38
94			`define ETH_MIISTATUS_ADR 6'hF // 0x3C
95			`define ETH_MAC_ADDR0_ADR 6'h10 // 0x40
96			`define ETH_MAC_ADDR1_ADR 6'h11 // 0x44
97	15	mohor
98
99
100	20	mohor	`define ETH_MODER_DEF 32'h0000A000
101			`define ETH_INT_SOURCE_DEF 32'h00000000
102			`define ETH_INT_MASK_DEF 32'h00000000
103			`define ETH_IPGT_DEF 32'h00000012
104			`define ETH_IPGR1_DEF 32'h0000000C
105			`define ETH_IPGR2_DEF 32'h00000012
106			`define ETH_PACKETLEN_DEF 32'h003C0600
107			`define ETH_COLLCONF_DEF 32'h000F0040
108			`define ETH_CTRLMODER_DEF 32'h00000000
109			`define ETH_MIIMODER_DEF 32'h00000064
110			`define ETH_MIICOMMAND_DEF 32'h00000000
111			`define ETH_MIIADDRESS_DEF 32'h00000000
112			`define ETH_MIITX_DATA_DEF 32'h00000000
113			`define ETH_MIIRX_DATA_DEF 32'h00000000
114			`define ETH_MIISTATUS_DEF 32'h00000000
115			`define ETH_MAC_ADDR0_DEF 32'h00000000
116			`define ETH_MAC_ADDR1_DEF 32'h00000000
117	15	mohor
118	20	mohor	`define ETH_RX_BD_ADR_DEF 8'h0

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[/] [ethmac/] [tags/] [rel_1/] [rtl/] [verilog/] [eth_defines.v] - Blame information for rev 29