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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_bus_mon.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
// Revision 1.1  2001/08/06 18:12:58  mihad
// Pocasi delamo kompletno zadevo
//
//
 
`include "wb_model_defines.v"
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
// monitors for any illegal combinations appearing on the bus.
module WB_BUS_MON(
                    CLK_I,
                    RST_I,
                    ACK_I,
                    ADDR_O,
                    CYC_O,
                    DAT_I,
                    DAT_O,
                    ERR_I,
                    RTY_I,
                    SEL_O,
                    STB_O,
                    WE_O,
                    TAG_I,
                    TAG_O,
                    CAB_O,
                    log_file_desc
                  ) ;
 
input                           CLK_I  ;
input                           RST_I  ;
input                           ACK_I  ;
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
input                           CYC_O  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
input                           ERR_I  ;
input                           RTY_I  ;
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
input                           STB_O  ;
input                           WE_O   ;
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
input                           CAB_O  ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        // when reset is applied, all control signals must be low
        if (CYC_O)
        begin
            $display("*E (%0t) CYC_O active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;
        end
        if (STB_O)
        begin
            $display("*E (%0t) STB_O active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;
        end
        /*if (ACK_I)
            $display("ACK_I active under reset") ;*/
        if (ERR_I)
        begin
            $display("*E (%0t) ERR_I active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;
        end
        if (RTY_I)
        begin
            $display("*E (%0t) RTY_I active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;
        end
        if (CAB_O)
        begin
            $display("*E (%0t) CAB_O active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;
        end
    end // reset
    else
    if (~CYC_O)
    begin
        // when cycle indicator is low, all control signals must be low
        if (STB_O)
        begin
            $display("*E (%0t) STB_O active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;
        end
        if (ACK_I)
        begin
            $display("*E (%0t) ACK_I active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;
        end
        if (ERR_I)
        begin
            $display("*E (%0t) ERR_I active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;
        end
        if (RTY_I)
        begin
            $display("*E (%0t) RTY_I active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;
        end
        if (CAB_O)
        begin
            $display("*E (%0t) CAB_O active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;
        end
    end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg                     previous_stb ;
reg                     previous_ack ;
reg                     previous_err ;
reg                     previous_rty ;
reg                     previous_cyc ;
reg can_change ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        previous_stb <= 1'b0 ;
        previous_ack <= 1'b0 ;
        previous_err <= 1'b0 ;
        previous_rty <= 1'b0 ;
        previous_cyc <= 1'b0 ;
    end
    else
    begin
        previous_stb <= STB_O ;
        previous_ack <= ACK_I ;
        previous_err <= ERR_I ;
        previous_rty <= RTY_I ;
        previous_cyc <= CYC_O ;
    end
end
 
// cycle monitor
always@(posedge CLK_I)
begin
    if (CYC_O && ~RST_I) // cycle in progress
    begin
        if (STB_O)
        begin
            // check for two control signals active at same edge
            if ( ACK_I && RTY_I )
            begin
                $display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;
            end
            if ( ACK_I && ERR_I )
            begin
                $display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;
            end
            if ( RTY_I && ERR_I )
            begin
                $display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;
            end
 
            if ( can_change !== 1 )
            begin
                if ( ADDR_O !== previous_address )
                begin
                    $display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;
                end
 
                if ( SEL_O !== previous_sel )
                begin
                    $display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
                end
 
                if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
                begin
                    $display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
                end
            end
 
            if ( ACK_I || RTY_I || ERR_I )
                can_change       = 1 ;
            else
            begin
                previous_data    = DAT_O ;
                previous_address = ADDR_O ;
                previous_sel     = SEL_O ;
                can_change = 0 ;
            end
 
        end // STB_O
        else
        begin //~STB_O
            // while STB_O is inactive, only ACK_I is allowed to be active
            if ( ERR_I )
            begin
                $display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;
            end
            if ( RTY_I )
            begin
                $display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;
            end
 
            if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
            begin
                $display("STB_O de-asserted without reception of slave response") ;
                $fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
            end
 
            can_change = 1 ;
        end   // ~STB_O
    end // cycle in progress
    else if (!RST_I)
    begin
        // cycle not in progress anymore
        can_change = 1 ;
        if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
        begin
            $display("STB_O de-asserted without reception of slave response") ;
            $fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
        end
    end
end // cycle monitor
 
// CAB_O monitor - CAB_O musn't change during one cycle
reg [1:0] first_cab_val ;
always@(posedge CLK_I or RST_I)
begin
    if ((CYC_O === 0) || RST_I)
        first_cab_val <= 2'b00 ;
    else
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_cab_val[1] === 1'b0)
            first_cab_val <= {1'b1, CAB_O} ;
        else if ( first_cab_val[0] !== CAB_O )
        begin
            $display("*E (%0t) CAB_O value changed during cycle", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;
        end
    end
end // CAB_O monitor
 
// WE_O monitor for consecutive address bursts
reg [1:0] first_we_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        first_we_val <= 2'b00 ;
    else
    if (STB_O)
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_we_val[1] == 1'b0)
            first_we_val <= {1'b1, WE_O} ;
        else if ( first_we_val[0] != WE_O )
        begin
            $display("*E (%0t) WE_O value changed during CAB cycle", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;
        end
    end
end // CAB_O monitor
 
// address monitor for consecutive address bursts
reg [`WB_ADDR_WIDTH:0] address ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
    else
    begin
        if (STB_O && ACK_I)
        begin
            if (address[`WB_ADDR_WIDTH] == 1'b0)
                address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
            else
            begin
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
                begin
                    $display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;
                end
                else
                    address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
            end
        end
    end
end // address monitor
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin
    if (CYC_O && STB_O && ~RST_I)
    begin
        if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
        begin
            $display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;
        end
        if ( WE_O )
        begin
            if (
                (SEL_O[0] && (((^DAT_O[7:0])   !== 1'b0) && ((^DAT_O[7:0])   !== 1'b1))) ||
                (SEL_O[1] && (((^DAT_O[15:8])  !== 1'b0) && ((^DAT_O[15:8])  !== 1'b1))) ||
                (SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
                (SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
               )
            begin
                $display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;
                $display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", $time, SEL_O, DAT_O) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", $time, SEL_O, DAT_O) ;
            end
 
        end
        else
        if (~WE_O && ACK_I)
        begin
            if (
                (SEL_O[0] && (((^DAT_I[7:0])   !== 1'b0) && ((^DAT_I[7:0])   !== 1'b1))) ||
                (SEL_O[1] && (((^DAT_I[15:8])  !== 1'b0) && ((^DAT_I[15:8])  !== 1'b1))) ||
                (SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
                (SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
               )
            begin
                $display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;
                $display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", $time, SEL_O, DAT_I) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", $time, SEL_O, DAT_I) ;
            end
        end
    end
end
 
initial
begin
    previous_data = 0 ;
    previous_address = 0 ;
    can_change = 1 ;
end
endmodule // BUS_MON

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[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 169

Line No.	Rev	Author	Line
1	169	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_bus_mon.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.pdf ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.1 2002/02/01 13:39:43 mihad`
47			`// Initial testbench import. Still under development`
48			`//`
49			`// Revision 1.1 2001/08/06 18:12:58 mihad`
50			`// Pocasi delamo kompletno zadevo`
51			`//`
52			`//`
53
54			`include "wb_model_defines.v"
55			`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`
56			`// monitors for any illegal combinations appearing on the bus.`
57			`module WB_BUS_MON(`
58			`CLK_I,`
59			`RST_I,`
60			`ACK_I,`
61			`ADDR_O,`
62			`CYC_O,`
63			`DAT_I,`
64			`DAT_O,`
65			`ERR_I,`
66			`RTY_I,`
67			`SEL_O,`
68			`STB_O,`
69			`WE_O,`
70			`TAG_I,`
71			`TAG_O,`
72			`CAB_O,`
73			`log_file_desc`
74			`) ;`
75
76			`input CLK_I ;`
77			`input RST_I ;`
78			`input ACK_I ;`
79			input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
80			`input CYC_O ;`
81			input [(`WB_DATA_WIDTH-1):0] DAT_I ;
82			input [(`WB_DATA_WIDTH-1):0] DAT_O ;
83			`input ERR_I ;`
84			`input RTY_I ;`
85			input [(`WB_SEL_WIDTH-1):0] SEL_O ;
86			`input STB_O ;`
87			`input WE_O ;`
88			input [(`WB_TAG_WIDTH-1):0] TAG_I ;
89			input [(`WB_TAG_WIDTH-1):0] TAG_O ;
90			`input CAB_O ;`
91			`input [31:0] log_file_desc ;`
92
93			`always@(posedge CLK_I or posedge RST_I)`
94			`begin`
95			`if (RST_I)`
96			`begin`
97			`// when reset is applied, all control signals must be low`
98			`if (CYC_O)`
99			`begin`
100			`$display("*E (%0t) CYC_O active under reset", $time) ;`
101			`$fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;`
102			`end`
103			`if (STB_O)`
104			`begin`
105			`$display("*E (%0t) STB_O active under reset", $time) ;`
106			`$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;`
107			`end`
108			`/*if (ACK_I)`
109			`$display("ACK_I active under reset") ;*/`
110			`if (ERR_I)`
111			`begin`
112			`$display("*E (%0t) ERR_I active under reset", $time) ;`
113			`$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;`
114			`end`
115			`if (RTY_I)`
116			`begin`
117			`$display("*E (%0t) RTY_I active under reset", $time) ;`
118			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;`
119			`end`
120			`if (CAB_O)`
121			`begin`
122			`$display("*E (%0t) CAB_O active under reset", $time) ;`
123			`$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;`
124			`end`
125			`end // reset`
126			`else`
127			`if (~CYC_O)`
128			`begin`
129			`// when cycle indicator is low, all control signals must be low`
130			`if (STB_O)`
131			`begin`
132			`$display("*E (%0t) STB_O active without CYC_O being active", $time) ;`
133			`$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;`
134			`end`
135			`if (ACK_I)`
136			`begin`
137			`$display("*E (%0t) ACK_I active without CYC_O being active", $time) ;`
138			`$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;`
139			`end`
140			`if (ERR_I)`
141			`begin`
142			`$display("*E (%0t) ERR_I active without CYC_O being active", $time) ;`
143			`$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;`
144			`end`
145			`if (RTY_I)`
146			`begin`
147			`$display("*E (%0t) RTY_I active without CYC_O being active", $time) ;`
148			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;`
149			`end`
150			`if (CAB_O)`
151			`begin`
152			`$display("*E (%0t) CAB_O active without CYC_O being active", $time) ;`
153			`$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;`
154			`end`
155			`end // ~CYC_O`
156			`end`
157
158			reg [`WB_DATA_WIDTH-1:0] previous_data ;
159			reg [`WB_ADDR_WIDTH-1:0] previous_address ;
160			reg [`WB_SEL_WIDTH-1:0] previous_sel ;
161			`reg previous_stb ;`
162			`reg previous_ack ;`
163			`reg previous_err ;`
164			`reg previous_rty ;`
165			`reg previous_cyc ;`
166			`reg can_change ;`
167
168			`always@(posedge CLK_I or posedge RST_I)`
169			`begin`
170			`if (RST_I)`
171			`begin`
172			`previous_stb <= 1'b0 ;`
173			`previous_ack <= 1'b0 ;`
174			`previous_err <= 1'b0 ;`
175			`previous_rty <= 1'b0 ;`
176			`previous_cyc <= 1'b0 ;`
177			`end`
178			`else`
179			`begin`
180			`previous_stb <= STB_O ;`
181			`previous_ack <= ACK_I ;`
182			`previous_err <= ERR_I ;`
183			`previous_rty <= RTY_I ;`
184			`previous_cyc <= CYC_O ;`
185			`end`
186			`end`
187
188			`// cycle monitor`
189			`always@(posedge CLK_I)`
190			`begin`
191			`if (CYC_O && ~RST_I) // cycle in progress`
192			`begin`
193			`if (STB_O)`
194			`begin`
195			`// check for two control signals active at same edge`
196			`if ( ACK_I && RTY_I )`
197			`begin`
198			`$display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;`
199			`$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;`
200			`end`
201			`if ( ACK_I && ERR_I )`
202			`begin`
203			`$display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;`
204			`$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;`
205			`end`
206			`if ( RTY_I && ERR_I )`
207			`begin`
208			`$display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;`
209			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;`
210			`end`
211
212			`if ( can_change !== 1 )`
213			`begin`
214			`if ( ADDR_O !== previous_address )`
215			`begin`
216			`$display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;`
217			`$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;`
218			`end`
219
220			`if ( SEL_O !== previous_sel )`
221			`begin`
222			`$display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;`
223			`$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;`
224			`end`
225
226			`if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )`
227			`begin`
228			`$display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;`
229			`$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;`
230			`end`
231			`end`
232
233			`if ( ACK_I \|\| RTY_I \|\| ERR_I )`
234			`can_change = 1 ;`
235			`else`
236			`begin`
237			`previous_data = DAT_O ;`
238			`previous_address = ADDR_O ;`
239			`previous_sel = SEL_O ;`
240			`can_change = 0 ;`
241			`end`
242
243			`end // STB_O`
244			`else`
245			`begin //~STB_O`
246			`// while STB_O is inactive, only ACK_I is allowed to be active`
247			`if ( ERR_I )`
248			`begin`
249			`$display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;`
250			`$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;`
251			`end`
252			`if ( RTY_I )`
253			`begin`
254			`$display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;`
255			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;`
256			`end`
257
258			`if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))`
259			`begin`
260			`$display("STB_O de-asserted without reception of slave response") ;`
261			`$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;`
262			`end`
263
264			`can_change = 1 ;`
265			`end // ~STB_O`
266			`end // cycle in progress`
267			`else if (!RST_I)`
268			`begin`
269			`// cycle not in progress anymore`
270			`can_change = 1 ;`
271			`if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))`
272			`begin`
273			`$display("STB_O de-asserted without reception of slave response") ;`
274			`$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;`
275			`end`
276			`end`
277			`end // cycle monitor`
278
279			`// CAB_O monitor - CAB_O musn't change during one cycle`
280			`reg [1:0] first_cab_val ;`
281			`always@(posedge CLK_I or RST_I)`
282			`begin`
283			`if ((CYC_O === 0) \|\| RST_I)`
284			`first_cab_val <= 2'b00 ;`
285			`else`
286			`begin`
287			`// cycle in progress - is this first clock edge in a cycle ?`
288			`if (first_cab_val[1] === 1'b0)`
289			`first_cab_val <= {1'b1, CAB_O} ;`
290			`else if ( first_cab_val[0] !== CAB_O )`
291			`begin`
292			`$display("*E (%0t) CAB_O value changed during cycle", $time) ;`
293			`$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;`
294			`end`
295			`end`
296			`end // CAB_O monitor`
297
298			`// WE_O monitor for consecutive address bursts`
299			`reg [1:0] first_we_val ;`
300			`always@(posedge CLK_I or posedge RST_I)`
301			`begin`
302			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
303			`first_we_val <= 2'b00 ;`
304			`else`
305			`if (STB_O)`
306			`begin`
307			`// cycle in progress - is this first clock edge in a cycle ?`
308			`if (first_we_val[1] == 1'b0)`
309			`first_we_val <= {1'b1, WE_O} ;`
310			`else if ( first_we_val[0] != WE_O )`
311			`begin`
312			`$display("*E (%0t) WE_O value changed during CAB cycle", $time) ;`
313			`$fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;`
314			`end`
315			`end`
316			`end // CAB_O monitor`
317
318			`// address monitor for consecutive address bursts`
319			reg [`WB_ADDR_WIDTH:0] address ;
320			`always@(posedge CLK_I or posedge RST_I)`
321			`begin`
322			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
323			address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
324			`else`
325			`begin`
326			`if (STB_O && ACK_I)`
327			`begin`
328			if (address[`WB_ADDR_WIDTH] == 1'b0)
329			address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
330			`else`
331			`begin`
332			if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
333			`begin`
334			`$display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;`
335			`$fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;`
336			`end`
337			`else`
338			address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
339			`end`
340			`end`
341			`end`
342			`end // address monitor`
343
344			`// data monitor`
345			`always@(posedge CLK_I or posedge RST_I)`
346			`begin`
347			`if (CYC_O && STB_O && ~RST_I)`
348			`begin`
349			`if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )`
350			`begin`
351			`$display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;`
352			`$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;`
353			`end`
354			`if ( WE_O )`
355			`begin`
356			`if (`
357			`(SEL_O[0] && (((^DAT_O[7:0]) !== 1'b0) && ((^DAT_O[7:0]) !== 1'b1))) \|\|`
358			`(SEL_O[1] && (((^DAT_O[15:8]) !== 1'b0) && ((^DAT_O[15:8]) !== 1'b1))) \|\|`
359			`(SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) \|\|`
360			`(SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))`
361			`)`
362			`begin`
363			`$display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;`
364			`$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;`
365			`$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;`
366			`$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;`
367			`end`
368
369			`end`
370			`else`
371			`if (~WE_O && ACK_I)`
372			`begin`
373			`if (`
374			`(SEL_O[0] && (((^DAT_I[7:0]) !== 1'b0) && ((^DAT_I[7:0]) !== 1'b1))) \|\|`
375			`(SEL_O[1] && (((^DAT_I[15:8]) !== 1'b0) && ((^DAT_I[15:8]) !== 1'b1))) \|\|`
376			`(SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) \|\|`
377			`(SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))`
378			`)`
379			`begin`
380			`$display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;`
381			`$fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;`
382			`$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;`
383			`$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;`
384			`end`
385			`end`
386			`end`
387			`end`
388
389			`initial`
390			`begin`
391			`previous_data = 0 ;`
392			`previous_address = 0 ;`
393			`can_change = 1 ;`
394			`end`
395			`endmodule // BUS_MON`