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[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 169

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_master_behavioral.v"                          ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/07/29 11:25:20  mihad
// Adding test bench for memory interface
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
 
`include "wb_model_defines.v"
`include "timescale.v"
module WB_MASTER_BEHAVIORAL
(
    CLK_I,
    RST_I,
    TAG_I,
    TAG_O,
    ACK_I,
    ADR_O,
    CYC_O,
    DAT_I,
    DAT_O,
    ERR_I,
    RTY_I,
    SEL_O,
    STB_O,
    WE_O,
    CAB_O
);
 
    input                    CLK_I;
    input                    RST_I;
    input    `WB_TAG_TYPE    TAG_I;
    output   `WB_TAG_TYPE    TAG_O;
    input                    ACK_I;
    output   `WB_ADDR_TYPE   ADR_O;
    output                   CYC_O;
    input    `WB_DATA_TYPE   DAT_I;
    output   `WB_DATA_TYPE   DAT_O;
    input                    ERR_I;
    input                    RTY_I;
    output   `WB_SEL_TYPE    SEL_O;
    output                   STB_O;
    output                   WE_O;
    output                   CAB_O;
 
// instantiate low level master module
WB_MASTER32 wbm_low_level
(
    .CLK_I(CLK_I),
    .RST_I(RST_I),
    .TAG_I(TAG_I),
    .TAG_O(TAG_O),
    .ACK_I(ACK_I),
    .ADR_O(ADR_O),
    .CYC_O(CYC_O),
    .DAT_I(DAT_I),
    .DAT_O(DAT_O),
    .ERR_I(ERR_I),
    .RTY_I(RTY_I),
    .SEL_O(SEL_O),
    .STB_O(STB_O),
    .WE_O(WE_O),
    .CAB_O(CAB_O)
) ;
 
// block read and write buffers definition
// single write buffer
reg `WRITE_STIM_TYPE  blk_write_data    [0:(`MAX_BLK_SIZE - 1)] ;
// read stimulus buffer - addresses, tags, selects etc.
reg `READ_STIM_TYPE   blk_read_data_in  [0:(`MAX_BLK_SIZE - 1)] ;
// read return buffer - data and tags received while performing block reads
reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
 
// single write task
task wb_single_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b1, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_write
 
task wb_single_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_read
 
task wb_RMW_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        if (retry === 1)
            wbm_low_level.end_cycle ;
        else
            wbm_low_level.modify_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_read
 
task wb_RMW_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        //@(posedge CLK_I) ;
        ok = 1 ;
        if (rty_count !== 0)
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
 
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_write
 
task wb_block_write ;
    input  `WB_TRANSFER_FLAGS write_flags ;
    inout  `WRITE_RETURN_TYPE return ;
 
    reg in_use ;
    reg `WRITE_STIM_TYPE  current_write ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    @(posedge CLK_I) ;
    cab = write_flags`WB_TRANSFER_CAB ;
    wbm_low_level.start_cycle(cab, 1'b1, ok) ;
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = write_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
        // collect data for current data beat
        current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
        wbm_low_level.wbm_write(current_write, return) ;
 
        // check result of write operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = write_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            wbm_low_level.end_cycle ;
            @(posedge CLK_I) ;
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
            if ( ok !== 1 )
            begin
                $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
                return`TB_ERROR_BIT = 1'b1 ;
                end_blk = 1 ;
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_write
 
task wb_block_read ;
    input  `WB_TRANSFER_FLAGS      read_flags ;
    inout `READ_RETURN_TYPE       return ;
 
    reg in_use ;
    reg `READ_STIM_TYPE  current_read ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
    integer transfered ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    transfered = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    @(posedge CLK_I) ;
    cab = read_flags`WB_TRANSFER_CAB ;
 
    wbm_low_level.start_cycle(cab, 1'b0, ok) ;
 
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = read_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
        // collect data for current data beat
        current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
 
        wbm_low_level.wbm_read(current_read, return) ;
 
        if ( transfered !== return`CYC_ACTUAL_TRANSFER )
        begin
            blk_read_data_out[transfered] = return ;
            transfered = return`CYC_ACTUAL_TRANSFER ;
        end
 
        // check result of read operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = read_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            wbm_low_level.end_cycle ;
            @(posedge CLK_I) ;
            wbm_low_level.start_cycle(cab, 1'b0, ok) ;
            if ( ok !== 1 )
            begin
                $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
                return`TB_ERROR_BIT = 1'b1 ;
                end_blk = 1 ;
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_read
 
endmodule
 

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[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 169

Line No.	Rev	Author	Line
1	169	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_master_behavioral.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//`
38			`// CVS Revision History`
39			`//`
40			`// $Log: not supported by cvs2svn $`
41			`// Revision 1.1 2002/07/29 11:25:20 mihad`
42			`// Adding test bench for memory interface`
43			`//`
44			`// Revision 1.1 2002/02/01 13:39:43 mihad`
45			`// Initial testbench import. Still under development`
46			`//`
47
48			`include "wb_model_defines.v"
49			`include "timescale.v"
50			`module WB_MASTER_BEHAVIORAL`
51			`(`
52			`CLK_I,`
53			`RST_I,`
54			`TAG_I,`
55			`TAG_O,`
56			`ACK_I,`
57			`ADR_O,`
58			`CYC_O,`
59			`DAT_I,`
60			`DAT_O,`
61			`ERR_I,`
62			`RTY_I,`
63			`SEL_O,`
64			`STB_O,`
65			`WE_O,`
66			`CAB_O`
67			`);`
68
69			`input CLK_I;`
70			`input RST_I;`
71			input `WB_TAG_TYPE TAG_I;
72			output `WB_TAG_TYPE TAG_O;
73			`input ACK_I;`
74			output `WB_ADDR_TYPE ADR_O;
75			`output CYC_O;`
76			input `WB_DATA_TYPE DAT_I;
77			output `WB_DATA_TYPE DAT_O;
78			`input ERR_I;`
79			`input RTY_I;`
80			output `WB_SEL_TYPE SEL_O;
81			`output STB_O;`
82			`output WE_O;`
83			`output CAB_O;`
84
85			`// instantiate low level master module`
86			`WB_MASTER32 wbm_low_level`
87			`(`
88			`.CLK_I(CLK_I),`
89			`.RST_I(RST_I),`
90			`.TAG_I(TAG_I),`
91			`.TAG_O(TAG_O),`
92			`.ACK_I(ACK_I),`
93			`.ADR_O(ADR_O),`
94			`.CYC_O(CYC_O),`
95			`.DAT_I(DAT_I),`
96			`.DAT_O(DAT_O),`
97			`.ERR_I(ERR_I),`
98			`.RTY_I(RTY_I),`
99			`.SEL_O(SEL_O),`
100			`.STB_O(STB_O),`
101			`.WE_O(WE_O),`
102			`.CAB_O(CAB_O)`
103			`) ;`
104
105			`// block read and write buffers definition`
106			`// single write buffer`
107			reg `WRITE_STIM_TYPE blk_write_data [0:(`MAX_BLK_SIZE - 1)] ;
108			`// read stimulus buffer - addresses, tags, selects etc.`
109			reg `READ_STIM_TYPE blk_read_data_in [0:(`MAX_BLK_SIZE - 1)] ;
110			`// read return buffer - data and tags received while performing block reads`
111			reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
112
113			`// single write task`
114			`task wb_single_write ;`
115			input `WRITE_STIM_TYPE write_data ;
116			input `WB_TRANSFER_FLAGS write_flags ;
117			inout `WRITE_RETURN_TYPE return ;
118			`reg in_use ;`
119			`reg cab ;`
120			`reg ok ;`
121			`integer cyc_count ;`
122			`integer rty_count ;`
123			`reg retry ;`
124			`begin:main`
125
126			return`TB_ERROR_BIT = 1'b0 ;
127			`cab = 0 ;`
128			return`CYC_ACTUAL_TRANSFER = 0 ;
129			`rty_count = 0 ;`
130
131			`// check if task was called before previous call finished`
132			`if ( in_use === 1 )`
133			`begin`
134			`$display("*E, wb_single_write routine re-entered! Time %t ", $time) ;`
135			return`TB_ERROR_BIT = 1'b1 ;
136			`disable main ;`
137			`end`
138
139			`in_use = 1 ;`
140
141			`retry = 1 ;`
142
143			`while (retry === 1)`
144			`begin`
145			`// synchronize operation to clock`
146			`@(posedge CLK_I) ;`
147
148			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
149			`if ( ok !== 1 )`
150			`begin`
151			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
152			return`TB_ERROR_BIT = 1'b1 ;
153			`disable main ;`
154			`end`
155
156			`// first insert initial wait states`
157			cyc_count = write_flags`INIT_WAITS ;
158			`while ( cyc_count > 0 )`
159			`begin`
160			`@(posedge CLK_I) ;`
161			`cyc_count = cyc_count - 1 ;`
162			`end`
163
164			`wbm_low_level.wbm_write(write_data, return) ;`
165
166			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
167			`begin`
168			if ( rty_count === `WB_TB_MAX_RTY )
169			`begin`
170			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;`
171			`retry = 0 ;`
172			`end`
173			`else`
174			`begin`
175			`retry = 1 ;`
176			`rty_count = rty_count + 1 ;`
177			`end`
178			`end`
179			`else`
180			`retry = 0 ;`
181
182			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
183			if ( return`TB_ERROR_BIT !== 0 )
184			`begin`
185			`@(posedge CLK_I) ;`
186			`wbm_low_level.end_cycle ;`
187			`disable main ;`
188			`end`
189
190			cyc_count = write_flags`SUBSEQ_WAITS ;
191			`while ( cyc_count > 0 )`
192			`begin`
193			`@(posedge CLK_I) ;`
194			`cyc_count = cyc_count - 1 ;`
195			`end`
196
197			`wbm_low_level.end_cycle ;`
198			`end`
199
200			`in_use = 0 ;`
201
202			`end //main`
203			`endtask // wb_single_write`
204
205			`task wb_single_read ;`
206			input `READ_STIM_TYPE read_data ;
207			input `WB_TRANSFER_FLAGS read_flags ;
208			inout `READ_RETURN_TYPE return ;
209			`reg in_use ;`
210			`reg cab ;`
211			`reg ok ;`
212			`integer cyc_count ;`
213			`integer rty_count ;`
214			`reg retry ;`
215			`begin:main`
216
217			return`TB_ERROR_BIT = 1'b0 ;
218			`cab = 0 ;`
219			`rty_count = 0 ;`
220			return`CYC_ACTUAL_TRANSFER = 0 ;
221
222			`// check if task was called before previous call finished`
223			`if ( in_use === 1 )`
224			`begin`
225			`$display("*E, wb_single_read routine re-entered! Time %t ", $time) ;`
226			return`TB_ERROR_BIT = 1'b1 ;
227			`disable main ;`
228			`end`
229
230			`in_use = 1 ;`
231
232			`retry = 1 ;`
233
234			`while (retry === 1)`
235			`begin`
236			`// synchronize operation to clock`
237			`@(posedge CLK_I) ;`
238
239			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
240			`if ( ok !== 1 )`
241			`begin`
242			`$display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;`
243			return`TB_ERROR_BIT = 1'b1 ;
244			`disable main ;`
245			`end`
246
247			`// first insert initial wait states`
248			cyc_count = read_flags`INIT_WAITS ;
249			`while ( cyc_count > 0 )`
250			`begin`
251			`@(posedge CLK_I) ;`
252			`cyc_count = cyc_count - 1 ;`
253			`end`
254
255			`wbm_low_level.wbm_read(read_data, return) ;`
256
257			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
258			`begin`
259			if ( rty_count === `WB_TB_MAX_RTY )
260			`begin`
261			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;`
262			`retry = 0 ;`
263			`end`
264			`else`
265			`begin`
266			`retry = 1 ;`
267			`rty_count = rty_count + 1 ;`
268			`end`
269			`end`
270			`else`
271			`begin`
272			`retry = 0 ;`
273			`end`
274
275			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
276			if ( return`TB_ERROR_BIT !== 0 )
277			`begin`
278			`@(posedge CLK_I) ;`
279			`wbm_low_level.end_cycle ;`
280			`disable main ;`
281			`end`
282
283			cyc_count = read_flags`SUBSEQ_WAITS ;
284			`while ( cyc_count > 0 )`
285			`begin`
286			`@(posedge CLK_I) ;`
287			`cyc_count = cyc_count - 1 ;`
288			`end`
289
290			`wbm_low_level.end_cycle ;`
291			`end`
292
293			`in_use = 0 ;`
294
295			`end //main`
296			`endtask // wb_single_read`
297
298			`task wb_RMW_read ;`
299			input `READ_STIM_TYPE read_data ;
300			input `WB_TRANSFER_FLAGS read_flags ;
301			inout `READ_RETURN_TYPE return ;
302			`reg in_use ;`
303			`reg cab ;`
304			`reg ok ;`
305			`integer cyc_count ;`
306			`integer rty_count ;`
307			`reg retry ;`
308			`begin:main`
309
310			return`TB_ERROR_BIT = 1'b0 ;
311			`cab = 0 ;`
312			`rty_count = 0 ;`
313			return`CYC_ACTUAL_TRANSFER = 0 ;
314
315			`// check if task was called before previous call finished`
316			`if ( in_use === 1 )`
317			`begin`
318			`$display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;`
319			return`TB_ERROR_BIT = 1'b1 ;
320			`disable main ;`
321			`end`
322
323			`in_use = 1 ;`
324
325			`retry = 1 ;`
326
327			`while (retry === 1)`
328			`begin`
329			`// synchronize operation to clock`
330			`@(posedge CLK_I) ;`
331
332			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
333			`if ( ok !== 1 )`
334			`begin`
335			`$display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;`
336			return`TB_ERROR_BIT = 1'b1 ;
337			`disable main ;`
338			`end`
339
340			`// first insert initial wait states`
341			cyc_count = read_flags`INIT_WAITS ;
342			`while ( cyc_count > 0 )`
343			`begin`
344			`@(posedge CLK_I) ;`
345			`cyc_count = cyc_count - 1 ;`
346			`end`
347
348			`wbm_low_level.wbm_read(read_data, return) ;`
349
350			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
351			`begin`
352			if ( rty_count === `WB_TB_MAX_RTY )
353			`begin`
354			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;`
355			`retry = 0 ;`
356			`end`
357			`else`
358			`begin`
359			`retry = 1 ;`
360			`rty_count = rty_count + 1 ;`
361			`end`
362			`end`
363			`else`
364			`begin`
365			`retry = 0 ;`
366			`end`
367
368			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
369			if ( return`TB_ERROR_BIT !== 0 )
370			`begin`
371			`@(posedge CLK_I) ;`
372			`wbm_low_level.end_cycle ;`
373			`disable main ;`
374			`end`
375
376			cyc_count = read_flags`SUBSEQ_WAITS ;
377			`while ( cyc_count > 0 )`
378			`begin`
379			`@(posedge CLK_I) ;`
380			`cyc_count = cyc_count - 1 ;`
381			`end`
382
383			`if (retry === 1)`
384			`wbm_low_level.end_cycle ;`
385			`else`
386			`wbm_low_level.modify_cycle ;`
387			`end`
388
389			`in_use = 0 ;`
390
391			`end //main`
392			`endtask // wb_RMW_read`
393
394			`task wb_RMW_write ;`
395			input `WRITE_STIM_TYPE write_data ;
396			input `WB_TRANSFER_FLAGS write_flags ;
397			inout `WRITE_RETURN_TYPE return ;
398			`reg in_use ;`
399			`reg cab ;`
400			`reg ok ;`
401			`integer cyc_count ;`
402			`integer rty_count ;`
403			`reg retry ;`
404			`begin:main`
405
406			return`TB_ERROR_BIT = 1'b0 ;
407			`cab = 0 ;`
408			return`CYC_ACTUAL_TRANSFER = 0 ;
409			`rty_count = 0 ;`
410
411			`// check if task was called before previous call finished`
412			`if ( in_use === 1 )`
413			`begin`
414			`$display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;`
415			return`TB_ERROR_BIT = 1'b1 ;
416			`disable main ;`
417			`end`
418
419			`in_use = 1 ;`
420
421			`retry = 1 ;`
422
423			`while (retry === 1)`
424			`begin`
425			`// synchronize operation to clock`
426			`//@(posedge CLK_I) ;`
427			`ok = 1 ;`
428			`if (rty_count !== 0)`
429			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
430
431			`if ( ok !== 1 )`
432			`begin`
433			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
434			return`TB_ERROR_BIT = 1'b1 ;
435			`disable main ;`
436			`end`
437
438			`// first insert initial wait states`
439			cyc_count = write_flags`INIT_WAITS ;
440			`while ( cyc_count > 0 )`
441			`begin`
442			`@(posedge CLK_I) ;`
443			`cyc_count = cyc_count - 1 ;`
444			`end`
445
446			`wbm_low_level.wbm_write(write_data, return) ;`
447
448			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
449			`begin`
450			if ( rty_count === `WB_TB_MAX_RTY )
451			`begin`
452			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;`
453			`retry = 0 ;`
454			`end`
455			`else`
456			`begin`
457			`retry = 1 ;`
458			`rty_count = rty_count + 1 ;`
459			`end`
460			`end`
461			`else`
462			`retry = 0 ;`
463
464			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
465			if ( return`TB_ERROR_BIT !== 0 )
466			`begin`
467			`@(posedge CLK_I) ;`
468			`wbm_low_level.end_cycle ;`
469			`disable main ;`
470			`end`
471
472			cyc_count = write_flags`SUBSEQ_WAITS ;
473			`while ( cyc_count > 0 )`
474			`begin`
475			`@(posedge CLK_I) ;`
476			`cyc_count = cyc_count - 1 ;`
477			`end`
478
479			`wbm_low_level.end_cycle ;`
480			`end`
481
482			`in_use = 0 ;`
483
484			`end //main`
485			`endtask // wb_RMW_write`
486
487			`task wb_block_write ;`
488			input `WB_TRANSFER_FLAGS write_flags ;
489			inout `WRITE_RETURN_TYPE return ;
490
491			`reg in_use ;`
492			reg `WRITE_STIM_TYPE current_write ;
493			`reg cab ;`
494			`reg ok ;`
495			`integer cyc_count ;`
496			`integer rty_count ;`
497			`reg end_blk ;`
498			`begin:main`
499
500			return`CYC_ACTUAL_TRANSFER = 0 ;
501			`rty_count = 0 ;`
502
503			`// check if task was called before previous call finished`
504			`if ( in_use === 1 )`
505			`begin`
506			`$display("*E, wb_block_write routine re-entered! Time %t ", $time) ;`
507			return`TB_ERROR_BIT = 1'b1 ;
508			`disable main ;`
509			`end`
510
511			if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
512			`begin`
513			`$display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;`
514			return`TB_ERROR_BIT = 1'b1 ;
515			`disable main ;`
516			`end`
517
518			`in_use = 1 ;`
519			`@(posedge CLK_I) ;`
520			cab = write_flags`WB_TRANSFER_CAB ;
521			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
522			`if ( ok !== 1 )`
523			`begin`
524			`$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;`
525			return`TB_ERROR_BIT = 1'b1 ;
526			`disable main ;`
527			`end`
528
529			`// insert initial wait states`
530			cyc_count = write_flags`INIT_WAITS ;
531			`while ( cyc_count > 0 )`
532			`begin`
533			`@(posedge CLK_I) ;`
534			`cyc_count = cyc_count - 1 ;`
535			`end`
536
537			`end_blk = 0 ;`
538			`while (end_blk === 0)`
539			`begin`
540			`// collect data for current data beat`
541			current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
542			`wbm_low_level.wbm_write(current_write, return) ;`
543
544			`// check result of write operation`
545			`// check for severe test error`
546			if (return`TB_ERROR_BIT !== 0)
547			`begin`
548			`@(posedge CLK_I) ;`
549			`wbm_low_level.end_cycle ;`
550			`disable main ;`
551			`end`
552
553			`// slave returned error or error signal had invalid value`
554			if (return`CYC_ERR !== 0)
555			`end_blk = 1 ;`
556
557			`if (`
558			(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) \|\|
559			(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) \|\|
560			(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
561			`)`
562			`begin`
563			`end_blk = 1 ;`
564			`$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;`
565			$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
566			`end`
567
568			if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
569			`end_blk = 1 ;`
570
571			if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
572			`begin`
573			if ( rty_count === `WB_TB_MAX_RTY )
574			`begin`
575			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;`
576			`end_blk = 1 ;`
577			`end`
578			`else`
579			`begin`
580			`rty_count = rty_count + 1 ;`
581			`end`
582			`end`
583			`else`
584			`rty_count = 0 ;`
585
586			`// check if slave responded at all`
587			if (return`CYC_RESPONSE === 0)
588			`end_blk = 1 ;`
589
590			`// check if all intended data was transfered`
591			if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
592			`end_blk = 1 ;`
593
594			`// insert subsequent wait cycles, if transfer is supposed to continue`
595			`if ( end_blk === 0 )`
596			`begin`
597			cyc_count = write_flags`SUBSEQ_WAITS ;
598			`while ( cyc_count > 0 )`
599			`begin`
600			`@(posedge CLK_I) ;`
601			`cyc_count = cyc_count - 1 ;`
602			`end`
603			`end`
604
605			if ( (end_blk === 0) && (return`CYC_RTY === 1) )
606			`begin`
607			`wbm_low_level.end_cycle ;`
608			`@(posedge CLK_I) ;`
609			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
610			`if ( ok !== 1 )`
611			`begin`
612			`$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;`
613			return`TB_ERROR_BIT = 1'b1 ;
614			`end_blk = 1 ;`
615			`end`
616			`end`
617			`end //while`
618
619			`wbm_low_level.end_cycle ;`
620			`in_use = 0 ;`
621			`end //main`
622			`endtask //wb_block_write`
623
624			`task wb_block_read ;`
625			input `WB_TRANSFER_FLAGS read_flags ;
626			inout `READ_RETURN_TYPE return ;
627
628			`reg in_use ;`
629			reg `READ_STIM_TYPE current_read ;
630			`reg cab ;`
631			`reg ok ;`
632			`integer cyc_count ;`
633			`integer rty_count ;`
634			`reg end_blk ;`
635			`integer transfered ;`
636			`begin:main`
637
638			return`CYC_ACTUAL_TRANSFER = 0 ;
639			`transfered = 0 ;`
640			`rty_count = 0 ;`
641
642			`// check if task was called before previous call finished`
643			`if ( in_use === 1 )`
644			`begin`
645			`$display("*E, wb_block_read routine re-entered! Time %t ", $time) ;`
646			return`TB_ERROR_BIT = 1'b1 ;
647			`disable main ;`
648			`end`
649
650			if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
651			`begin`
652			`$display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;`
653			return`TB_ERROR_BIT = 1'b1 ;
654			`disable main ;`
655			`end`
656
657			`in_use = 1 ;`
658			`@(posedge CLK_I) ;`
659			cab = read_flags`WB_TRANSFER_CAB ;
660
661			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
662
663			`if ( ok !== 1 )`
664			`begin`
665			`$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;`
666			return`TB_ERROR_BIT = 1'b1 ;
667			`disable main ;`
668			`end`
669
670			`// insert initial wait states`
671			cyc_count = read_flags`INIT_WAITS ;
672			`while ( cyc_count > 0 )`
673			`begin`
674			`@(posedge CLK_I) ;`
675			`cyc_count = cyc_count - 1 ;`
676			`end`
677
678			`end_blk = 0 ;`
679			`while (end_blk === 0)`
680			`begin`
681			`// collect data for current data beat`
682			current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
683
684			`wbm_low_level.wbm_read(current_read, return) ;`
685
686			if ( transfered !== return`CYC_ACTUAL_TRANSFER )
687			`begin`
688			`blk_read_data_out[transfered] = return ;`
689			transfered = return`CYC_ACTUAL_TRANSFER ;
690			`end`
691
692			`// check result of read operation`
693			`// check for severe test error`
694			if (return`TB_ERROR_BIT !== 0)
695			`begin`
696			`@(posedge CLK_I) ;`
697			`wbm_low_level.end_cycle ;`
698			`disable main ;`
699			`end`
700
701			`// slave returned error or error signal had invalid value`
702			if (return`CYC_ERR !== 0)
703			`end_blk = 1 ;`
704
705			`if (`
706			(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) \|\|
707			(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) \|\|
708			(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
709			`)`
710			`begin`
711			`end_blk = 1 ;`
712			`$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;`
713			$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
714			`end`
715
716			if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
717			`end_blk = 1 ;`
718
719			if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
720			`begin`
721			if ( rty_count === `WB_TB_MAX_RTY )
722			`begin`
723			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;`
724			`end_blk = 1 ;`
725			`end`
726			`else`
727			`begin`
728			`rty_count = rty_count + 1 ;`
729			`end`
730			`end`
731			`else`
732			`rty_count = 0 ;`
733
734			`// check if slave responded at all`
735			if (return`CYC_RESPONSE === 0)
736			`end_blk = 1 ;`
737
738			`// check if all intended data was transfered`
739			if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
740			`end_blk = 1 ;`
741
742			`// insert subsequent wait cycles, if transfer is supposed to continue`
743			`if ( end_blk === 0 )`
744			`begin`
745			cyc_count = read_flags`SUBSEQ_WAITS ;
746			`while ( cyc_count > 0 )`
747			`begin`
748			`@(posedge CLK_I) ;`
749			`cyc_count = cyc_count - 1 ;`
750			`end`
751			`end`
752
753			if ( (end_blk === 0) && (return`CYC_RTY === 1) )
754			`begin`
755			`wbm_low_level.end_cycle ;`
756			`@(posedge CLK_I) ;`
757			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
758			`if ( ok !== 1 )`
759			`begin`
760			`$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;`
761			return`TB_ERROR_BIT = 1'b1 ;
762			`end_blk = 1 ;`
763			`end`
764			`end`
765			`end //while`
766
767			`wbm_low_level.end_cycle ;`
768			`in_use = 0 ;`
769			`end //main`
770			`endtask //wb_block_read`
771
772			`endmodule`
773