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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_clockgen.v] - Blame information for rev 338

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_clockgen.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
44 37 mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.3  2001/06/01 22:28:55  mohor
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// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
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//
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//
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`include "timescale.v"
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module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
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parameter Tp=1;
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input       Clk;              // Input clock (Host clock)
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input       Reset;            // Reset signal
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input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])
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output      Mdc;              // Output clock
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output      MdcEn;            // Enable signal is asserted for one Clk period before Mdc rises.
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output      MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
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reg         Mdc;
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reg   [7:0] Counter;
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wire        CountEq0;
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wire  [7:0] CounterPreset;
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wire  [7:0] TempDivider;
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assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
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assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1;               // We are counting half of period
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// Counter counts half period
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always @ (posedge Clk or posedge Reset)
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begin
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  if(Reset)
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    Counter[7:0] <= #Tp 8'h1;
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  else
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    begin
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      if(CountEq0)
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        begin
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          Counter[7:0] <= #Tp CounterPreset[7:0];
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        end
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      else
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        Counter[7:0] <= #Tp Counter - 8'h1;
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    end
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end
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// Mdc is asserted every other half period
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always @ (posedge Clk or posedge Reset)
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begin
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  if(Reset)
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    Mdc <= #Tp 1'b0;
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  else
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    begin
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      if(CountEq0)
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        Mdc <= #Tp ~Mdc;
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    end
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end
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assign CountEq0 = Counter == 8'h0;
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assign MdcEn = CountEq0 & ~Mdc;
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assign MdcEn_n = CountEq0 & Mdc;
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endmodule
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