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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_miim.v] - Blame information for rev 15

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_miim.v                                                  ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/cores/ethmac/                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2001/08/02 09:25:31  mohor
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// Unconnected signals are now connected.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.3  2001/06/01 22:28:56  mohor
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// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
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//
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//
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`include "eth_timescale.v"
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module eth_miim
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(
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  Clk,
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  Reset,
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  Divider,
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  NoPre,
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  CtrlData,
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  Rgad,
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  Fiad,
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  WCtrlData,
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  RStat,
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  ScanStat,
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  Mdi,
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  Mdo,
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  MdoEn,
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  Mdc,
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  Busy,
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  Prsd,
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  LinkFail,
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  Nvalid,
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  WCtrlDataStart,
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  RStatStart,
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  UpdateMIIRX_DATAReg
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);
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83
 
84
 
85
input         Clk;                // Host Clock
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input         Reset;              // General Reset
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input   [7:0] Divider;            // Divider for the host clock
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input  [15:0] CtrlData;           // Control Data (to be written to the PHY reg.)
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input   [4:0] Rgad;               // Register Address (within the PHY)
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input   [4:0] Fiad;               // PHY Address
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input         NoPre;              // No Preamble (no 32-bit preamble)
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input         WCtrlData;          // Write Control Data operation
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input         RStat;              // Read Status operation
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input         ScanStat;           // Scan Status operation
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input         Mdi;                // MII Management Data In
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97
output        Mdc;                // MII Management Data Clock
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output        Mdo;                // MII Management Data Output
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output        MdoEn;              // MII Management Data Output Enable
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output        Busy;               // Busy Signal
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output        LinkFail;           // Link Integrity Signal
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output        Nvalid;             // Invalid Status (qualifier for the valid scan result)
103
 
104
output [15:0] Prsd;               // Read Status Data (data read from the PHY)
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106
output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
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output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
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output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
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110
parameter Tp = 1;
111
 
112
 
113
reg           Nvalid;
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reg           EndBusy_d;          // Pre-end Busy signal
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reg           EndBusy;            // End Busy signal (stops the operation in progress)
116
 
117
reg           WCtrlData_q1;       // Write Control Data operation delayed 1 Clk cycle
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reg           WCtrlData_q2;       // Write Control Data operation delayed 2 Clk cycles
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reg           WCtrlData_q3;       // Write Control Data operation delayed 3 Clk cycles
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reg           WCtrlDataStart;     // Start Write Control Data Command (positive edge detected)
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reg           WCtrlDataStart_q;
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reg           WCtrlDataStart_q1;  // Start Write Control Data Command delayed 1 Mdc cycle
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reg           WCtrlDataStart_q2;  // Start Write Control Data Command delayed 2 Mdc cycles
124
 
125
reg           RStat_q1;           // Read Status operation delayed 1 Clk cycle
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reg           RStat_q2;           // Read Status operation delayed 2 Clk cycles
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reg           RStat_q3;           // Read Status operation delayed 3 Clk cycles
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reg           RStatStart;         // Start Read Status Command (positive edge detected)
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reg           RStatStart_q1;      // Start Read Status Command delayed 1 Mdc cycle
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reg           RStatStart_q2;      // Start Read Status Command delayed 2 Mdc cycles
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132
reg           ScanStat_q1;        // Scan Status operation delayed 1 cycle
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reg           ScanStat_q2;        // Scan Status operation delayed 2 cycles
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reg           SyncStatMdcEn;      // Scan Status operation delayed at least cycles and synchronized to MdcEn
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136
wire          WriteDataOp;        // Write Data Operation (positive edge detected)
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wire          ReadStatusOp;       // Read Status Operation (positive edge detected)
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wire          ScanStatusOp;       // Scan Status Operation (positive edge detected)
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wire          StartOp;            // Start Operation (start of any of the preceding operations)
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wire          EndOp;              // End of Operation
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142
reg           InProgress;         // Operation in progress
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reg           InProgress_q1;      // Operation in progress delayed 1 Mdc cycle
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reg           InProgress_q2;      // Operation in progress delayed 2 Mdc cycles
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reg           InProgress_q3;      // Operation in progress delayed 3 Mdc cycles
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147
reg           WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
148
reg     [6:0] BitCounter;         // Bit Counter
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150
 
151
wire          MdcFrame;           // Frame window for limiting the Mdc
152
wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
153
wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
154
wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
155
 
156
 
157
wire          LatchByte1_d2;
158
wire          LatchByte0_d2;
159
reg           LatchByte1_d;
160
reg           LatchByte0_d;
161
reg     [1:0] LatchByte;          // Latch Byte selects which part of Read Status Data is updated from the shift register
162
 
163
reg           UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
164
 
165
 
166
 
167
 
168
 
169
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
170
always @ (posedge Clk or posedge Reset)
171
begin
172
  if(Reset)
173
    begin
174
      EndBusy_d <= #Tp 1'b0;
175
      EndBusy <= #Tp 1'b0;
176
    end
177
  else
178
    begin
179
      EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
180
      EndBusy   <= #Tp EndBusy_d;
181
    end
182
end
183
 
184
 
185
// Update MII RX_DATA register
186
always @ (posedge Clk or posedge Reset)
187
begin
188
  if(Reset)
189
    UpdateMIIRX_DATAReg <= #Tp 0;
190
  else
191
  if(EndBusy & ~WCtrlDataStart_q)
192
    UpdateMIIRX_DATAReg <= #Tp 1;
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  else
194
    UpdateMIIRX_DATAReg <= #Tp 0;
195
end
196
 
197
 
198
 
199
// Generation of the delayed signals used for positive edge triggering.
200
always @ (posedge Clk or posedge Reset)
201
begin
202
  if(Reset)
203
    begin
204
      WCtrlData_q1 <= #Tp 1'b0;
205
      WCtrlData_q2 <= #Tp 1'b0;
206
      WCtrlData_q3 <= #Tp 1'b0;
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208
      RStat_q1 <= #Tp 1'b0;
209
      RStat_q2 <= #Tp 1'b0;
210
      RStat_q3 <= #Tp 1'b0;
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212
      ScanStat_q1  <= #Tp 1'b0;
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      ScanStat_q2  <= #Tp 1'b0;
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      SyncStatMdcEn <= #Tp 1'b0;
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    end
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  else
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    begin
218
      WCtrlData_q1 <= #Tp WCtrlData;
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      WCtrlData_q2 <= #Tp WCtrlData_q1;
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      WCtrlData_q3 <= #Tp WCtrlData_q2;
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222
      RStat_q1 <= #Tp RStat;
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      RStat_q2 <= #Tp RStat_q1;
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      RStat_q3 <= #Tp RStat_q2;
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226
      ScanStat_q1  <= #Tp ScanStat;
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      ScanStat_q2  <= #Tp ScanStat_q1;
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      if(MdcEn)
229
        SyncStatMdcEn  <= #Tp ScanStat_q2;
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    end
231
end
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// Generation of the Start Commands (Write Control Data or Read Status)
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always @ (posedge Clk or posedge Reset)
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begin
237
  if(Reset)
238
    begin
239
      WCtrlDataStart <= #Tp 1'b0;
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      WCtrlDataStart_q <= #Tp 1'b0;
241
      RStatStart <= #Tp 1'b0;
242
    end
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  else
244
    begin
245
      if(EndBusy)
246
        begin
247
          WCtrlDataStart <= #Tp 1'b0;
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          RStatStart <= #Tp 1'b0;
249
        end
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      else
251
        begin
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          if(WCtrlData_q2 & ~WCtrlData_q3)
253
            WCtrlDataStart <= #Tp 1'b1;
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          if(RStat_q2 & ~RStat_q3)
255
            RStatStart <= #Tp 1'b1;
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          WCtrlDataStart_q <= #Tp WCtrlDataStart;
257
        end
258
    end
259
end
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// Generation of the Nvalid signal (indicates when the status is invalid)
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always @ (posedge Clk or posedge Reset)
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begin
265
  if(Reset)
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    Nvalid <= #Tp 1'b0;
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  else
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    begin
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      if(~InProgress & InProgress_q1)
270
        begin
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          Nvalid <= #Tp 1'b0;
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        end
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      else
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        begin
275
          if(ScanStat_q2  & ~SyncStatMdcEn)
276
            Nvalid <= #Tp 1'b1;
277
        end
278
    end
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end
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// Signals used for the generation of the Operation signals (positive edge)
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always @ (posedge Clk or posedge Reset)
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begin
284
  if(Reset)
285
    begin
286
      WCtrlDataStart_q1 <= #Tp 1'b0;
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      WCtrlDataStart_q2 <= #Tp 1'b0;
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289
      RStatStart_q1 <= #Tp 1'b0;
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      RStatStart_q2 <= #Tp 1'b0;
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292
      InProgress_q1 <= #Tp 1'b0;
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      InProgress_q2 <= #Tp 1'b0;
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      InProgress_q3 <= #Tp 1'b0;
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296
          LatchByte0_d <= #Tp 1'b0;
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          LatchByte1_d <= #Tp 1'b0;
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299
          LatchByte <= #Tp 2'b00;
300
    end
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  else
302
    begin
303
      if(MdcEn)
304
        begin
305
          WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
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          WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
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308
          RStatStart_q1 <= #Tp RStatStart;
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          RStatStart_q2 <= #Tp RStatStart_q1;
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311
          LatchByte[0] <= #Tp LatchByte0_d;
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          LatchByte[1] <= #Tp LatchByte1_d;
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314
          LatchByte0_d <= #Tp LatchByte0_d2;
315
          LatchByte1_d <= #Tp LatchByte1_d2;
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317
          InProgress_q1 <= #Tp InProgress;
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          InProgress_q2 <= #Tp InProgress_q1;
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          InProgress_q3 <= #Tp InProgress_q2;
320
        end
321
    end
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end
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// Generation of the Operation signals
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assign WriteDataOp  = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
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assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
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assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
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assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
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331
// Busy
332
assign Busy = WCtrlDataStart | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3;
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// Generation of the InProgress signal (indicates when an operation is in progress)
336
// Generation of the WriteOp signal (indicates when a write is in progress)
337
always @ (posedge Clk or posedge Reset)
338
begin
339
  if(Reset)
340
    begin
341
      InProgress <= #Tp 1'b0;
342
      WriteOp <= #Tp 1'b0;
343
    end
344
  else
345
    begin
346
      if(MdcEn)
347
        begin
348
          if(StartOp)
349
            begin
350
              if(~InProgress)
351
                WriteOp <= #Tp WriteDataOp;
352
              InProgress <= #Tp 1'b1;
353
            end
354
          else
355
            begin
356
              if(EndOp)
357
                begin
358
                  InProgress <= #Tp 1'b0;
359
                  WriteOp <= #Tp 1'b0;
360
                end
361
            end
362
        end
363
    end
364
end
365
 
366
 
367
 
368
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
369
always @ (posedge Clk or posedge Reset)
370
begin
371
  if(Reset)
372
    BitCounter[6:0] <= #Tp 7'h0;
373
  else
374
    begin
375
      if(MdcEn)
376
        begin
377
          if(InProgress)
378
            begin
379
              if(NoPre & ( BitCounter == 7'h0 ))
380
                BitCounter[6:0] <= #Tp 7'h21;
381
              else
382
                BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
383
            end
384
          else
385
            BitCounter[6:0] <= #Tp 7'h0;
386
        end
387
    end
388
end
389
 
390
 
391
// Operation ends when the Bit Counter reaches 63
392
assign EndOp = BitCounter==63;
393
 
394
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
395
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
396
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
397
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
398
 
399
 
400
// Latch Byte selects which part of Read Status Data is updated from the shift register
401
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
402
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
403
 
404
 
405
// Connecting the Clock Generator Module
406
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
407
                   );
408
 
409
// Connecting the Shift Register Module
410
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
411
                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
412
                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
413
                   );
414
 
415
// Connecting the Output Control Module
416
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
417
                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
418
                          .Mdo(Mdo), .MdoEn(MdoEn)
419
                         );
420
 
421
endmodule

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