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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_miim.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_miim.v                                                  ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/02 09:25:31  mohor
// Unconnected signals are now connected.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3  2001/06/01 22:28:56  mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`include "eth_timescale.v"
 
 
module eth_miim
(
  Clk,
  Reset,
  Divider,
  NoPre,
  CtrlData,
  Rgad,
  Fiad,
  WCtrlData,
  RStat,
  ScanStat,
  Mdi,
  Mdo,
  MdoEn,
  Mdc,
  Busy,
  Prsd,
  LinkFail,
  Nvalid,
  WCtrlDataStart,
  RStatStart,
  UpdateMIIRX_DATAReg
);
 
 
 
input         Clk;                // Host Clock
input         Reset;              // General Reset
input   [7:0] Divider;            // Divider for the host clock
input  [15:0] CtrlData;           // Control Data (to be written to the PHY reg.)
input   [4:0] Rgad;               // Register Address (within the PHY)
input   [4:0] Fiad;               // PHY Address
input         NoPre;              // No Preamble (no 32-bit preamble)
input         WCtrlData;          // Write Control Data operation
input         RStat;              // Read Status operation
input         ScanStat;           // Scan Status operation
input         Mdi;                // MII Management Data In
 
output        Mdc;                // MII Management Data Clock
output        Mdo;                // MII Management Data Output
output        MdoEn;              // MII Management Data Output Enable
output        Busy;               // Busy Signal
output        LinkFail;           // Link Integrity Signal
output        Nvalid;             // Invalid Status (qualifier for the valid scan result)
 
output [15:0] Prsd;               // Read Status Data (data read from the PHY)
 
output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
 
parameter Tp = 1;
 
 
reg           Nvalid;
reg           EndBusy_d;          // Pre-end Busy signal
reg           EndBusy;            // End Busy signal (stops the operation in progress)
 
reg           WCtrlData_q1;       // Write Control Data operation delayed 1 Clk cycle
reg           WCtrlData_q2;       // Write Control Data operation delayed 2 Clk cycles
reg           WCtrlData_q3;       // Write Control Data operation delayed 3 Clk cycles
reg           WCtrlDataStart;     // Start Write Control Data Command (positive edge detected)
reg           WCtrlDataStart_q;
reg           WCtrlDataStart_q1;  // Start Write Control Data Command delayed 1 Mdc cycle
reg           WCtrlDataStart_q2;  // Start Write Control Data Command delayed 2 Mdc cycles
 
reg           RStat_q1;           // Read Status operation delayed 1 Clk cycle
reg           RStat_q2;           // Read Status operation delayed 2 Clk cycles
reg           RStat_q3;           // Read Status operation delayed 3 Clk cycles
reg           RStatStart;         // Start Read Status Command (positive edge detected)
reg           RStatStart_q1;      // Start Read Status Command delayed 1 Mdc cycle
reg           RStatStart_q2;      // Start Read Status Command delayed 2 Mdc cycles
 
reg           ScanStat_q1;        // Scan Status operation delayed 1 cycle
reg           ScanStat_q2;        // Scan Status operation delayed 2 cycles
reg           SyncStatMdcEn;      // Scan Status operation delayed at least cycles and synchronized to MdcEn
 
wire          WriteDataOp;        // Write Data Operation (positive edge detected)
wire          ReadStatusOp;       // Read Status Operation (positive edge detected)
wire          ScanStatusOp;       // Scan Status Operation (positive edge detected)
wire          StartOp;            // Start Operation (start of any of the preceding operations)
wire          EndOp;              // End of Operation
 
reg           InProgress;         // Operation in progress
reg           InProgress_q1;      // Operation in progress delayed 1 Mdc cycle
reg           InProgress_q2;      // Operation in progress delayed 2 Mdc cycles
reg           InProgress_q3;      // Operation in progress delayed 3 Mdc cycles
 
reg           WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
reg     [6:0] BitCounter;         // Bit Counter
 
 
wire          MdcFrame;           // Frame window for limiting the Mdc
wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
 
 
wire          LatchByte1_d2;
wire          LatchByte0_d2;
reg           LatchByte1_d;
reg           LatchByte0_d;
reg     [1:0] LatchByte;          // Latch Byte selects which part of Read Status Data is updated from the shift register
 
reg           UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
 
 
 
 
 
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      EndBusy_d <= #Tp 1'b0;
      EndBusy <= #Tp 1'b0;
    end
  else
    begin
      EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
      EndBusy   <= #Tp EndBusy_d;
    end
end
 
 
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    UpdateMIIRX_DATAReg <= #Tp 0;
  else
  if(EndBusy & ~WCtrlDataStart_q)
    UpdateMIIRX_DATAReg <= #Tp 1;
  else
    UpdateMIIRX_DATAReg <= #Tp 0;
end
 
 
 
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      WCtrlData_q1 <= #Tp 1'b0;
      WCtrlData_q2 <= #Tp 1'b0;
      WCtrlData_q3 <= #Tp 1'b0;
 
      RStat_q1 <= #Tp 1'b0;
      RStat_q2 <= #Tp 1'b0;
      RStat_q3 <= #Tp 1'b0;
 
      ScanStat_q1  <= #Tp 1'b0;
      ScanStat_q2  <= #Tp 1'b0;
      SyncStatMdcEn <= #Tp 1'b0;
    end
  else
    begin
      WCtrlData_q1 <= #Tp WCtrlData;
      WCtrlData_q2 <= #Tp WCtrlData_q1;
      WCtrlData_q3 <= #Tp WCtrlData_q2;
 
      RStat_q1 <= #Tp RStat;
      RStat_q2 <= #Tp RStat_q1;
      RStat_q3 <= #Tp RStat_q2;
 
      ScanStat_q1  <= #Tp ScanStat;
      ScanStat_q2  <= #Tp ScanStat_q1;
      if(MdcEn)
        SyncStatMdcEn  <= #Tp ScanStat_q2;
    end
end
 
 
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      WCtrlDataStart <= #Tp 1'b0;
      WCtrlDataStart_q <= #Tp 1'b0;
      RStatStart <= #Tp 1'b0;
    end
  else
    begin
      if(EndBusy)
        begin
          WCtrlDataStart <= #Tp 1'b0;
          RStatStart <= #Tp 1'b0;
        end
      else
        begin
          if(WCtrlData_q2 & ~WCtrlData_q3)
            WCtrlDataStart <= #Tp 1'b1;
          if(RStat_q2 & ~RStat_q3)
            RStatStart <= #Tp 1'b1;
          WCtrlDataStart_q <= #Tp WCtrlDataStart;
        end
    end
end
 
 
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    Nvalid <= #Tp 1'b0;
  else
    begin
      if(~InProgress & InProgress_q1)
        begin
          Nvalid <= #Tp 1'b0;
        end
      else
        begin
          if(ScanStat_q2  & ~SyncStatMdcEn)
            Nvalid <= #Tp 1'b1;
        end
    end
end
 
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      WCtrlDataStart_q1 <= #Tp 1'b0;
      WCtrlDataStart_q2 <= #Tp 1'b0;
 
      RStatStart_q1 <= #Tp 1'b0;
      RStatStart_q2 <= #Tp 1'b0;
 
      InProgress_q1 <= #Tp 1'b0;
      InProgress_q2 <= #Tp 1'b0;
      InProgress_q3 <= #Tp 1'b0;
 
          LatchByte0_d <= #Tp 1'b0;
          LatchByte1_d <= #Tp 1'b0;
 
          LatchByte <= #Tp 2'b00;
    end
  else
    begin
      if(MdcEn)
        begin
          WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
          WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
 
          RStatStart_q1 <= #Tp RStatStart;
          RStatStart_q2 <= #Tp RStatStart_q1;
 
          LatchByte[0] <= #Tp LatchByte0_d;
          LatchByte[1] <= #Tp LatchByte1_d;
 
          LatchByte0_d <= #Tp LatchByte0_d2;
          LatchByte1_d <= #Tp LatchByte1_d2;
 
          InProgress_q1 <= #Tp InProgress;
          InProgress_q2 <= #Tp InProgress_q1;
          InProgress_q3 <= #Tp InProgress_q2;
        end
    end
end
 
 
// Generation of the Operation signals
assign WriteDataOp  = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
 
// Busy
assign Busy = WCtrlDataStart | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3;
 
 
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      InProgress <= #Tp 1'b0;
      WriteOp <= #Tp 1'b0;
    end
  else
    begin
      if(MdcEn)
        begin
          if(StartOp)
            begin
              if(~InProgress)
                WriteOp <= #Tp WriteDataOp;
              InProgress <= #Tp 1'b1;
            end
          else
            begin
              if(EndOp)
                begin
                  InProgress <= #Tp 1'b0;
                  WriteOp <= #Tp 1'b0;
                end
            end
        end
    end
end
 
 
 
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    BitCounter[6:0] <= #Tp 7'h0;
  else
    begin
      if(MdcEn)
        begin
          if(InProgress)
            begin
              if(NoPre & ( BitCounter == 7'h0 ))
                BitCounter[6:0] <= #Tp 7'h21;
              else
                BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
            end
          else
            BitCounter[6:0] <= #Tp 7'h0;
        end
    end
end
 
 
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
 
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
 
 
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
 
 
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
                   );
 
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
                   );
 
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
                          .Mdo(Mdo), .MdoEn(MdoEn)
                         );
 
endmodule

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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_miim.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_miim.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.2 2001/08/02 09:25:31 mohor`
45			`// Unconnected signals are now connected.`
46			`//`
47			`// Revision 1.1 2001/07/30 21:23:42 mohor`
48			`// Directory structure changed. Files checked and joind together.`
49			`//`
50			`// Revision 1.3 2001/06/01 22:28:56 mohor`
51			`// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.`
52			`//`
53			`//`
54
55			`include "eth_timescale.v"
56
57
58			`module eth_miim`
59			`(`
60			`Clk,`
61			`Reset,`
62			`Divider,`
63			`NoPre,`
64			`CtrlData,`
65			`Rgad,`
66			`Fiad,`
67			`WCtrlData,`
68			`RStat,`
69			`ScanStat,`
70			`Mdi,`
71			`Mdo,`
72			`MdoEn,`
73			`Mdc,`
74			`Busy,`
75			`Prsd,`
76			`LinkFail,`
77			`Nvalid,`
78			`WCtrlDataStart,`
79			`RStatStart,`
80			`UpdateMIIRX_DATAReg`
81			`);`
82
83
84
85			`input Clk; // Host Clock`
86			`input Reset; // General Reset`
87			`input [7:0] Divider; // Divider for the host clock`
88			`input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)`
89			`input [4:0] Rgad; // Register Address (within the PHY)`
90			`input [4:0] Fiad; // PHY Address`
91			`input NoPre; // No Preamble (no 32-bit preamble)`
92			`input WCtrlData; // Write Control Data operation`
93			`input RStat; // Read Status operation`
94			`input ScanStat; // Scan Status operation`
95			`input Mdi; // MII Management Data In`
96
97			`output Mdc; // MII Management Data Clock`
98			`output Mdo; // MII Management Data Output`
99			`output MdoEn; // MII Management Data Output Enable`
100			`output Busy; // Busy Signal`
101			`output LinkFail; // Link Integrity Signal`
102			`output Nvalid; // Invalid Status (qualifier for the valid scan result)`
103
104			`output [15:0] Prsd; // Read Status Data (data read from the PHY)`
105
106			`output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register`
107			`output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register`
108			`output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data`
109
110			`parameter Tp = 1;`
111
112
113			`reg Nvalid;`
114			`reg EndBusy_d; // Pre-end Busy signal`
115			`reg EndBusy; // End Busy signal (stops the operation in progress)`
116
117			`reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle`
118			`reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles`
119			`reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles`
120			`reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)`
121			`reg WCtrlDataStart_q;`
122			`reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle`
123			`reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles`
124
125			`reg RStat_q1; // Read Status operation delayed 1 Clk cycle`
126			`reg RStat_q2; // Read Status operation delayed 2 Clk cycles`
127			`reg RStat_q3; // Read Status operation delayed 3 Clk cycles`
128			`reg RStatStart; // Start Read Status Command (positive edge detected)`
129			`reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle`
130			`reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles`
131
132			`reg ScanStat_q1; // Scan Status operation delayed 1 cycle`
133			`reg ScanStat_q2; // Scan Status operation delayed 2 cycles`
134			`reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn`
135
136			`wire WriteDataOp; // Write Data Operation (positive edge detected)`
137			`wire ReadStatusOp; // Read Status Operation (positive edge detected)`
138			`wire ScanStatusOp; // Scan Status Operation (positive edge detected)`
139			`wire StartOp; // Start Operation (start of any of the preceding operations)`
140			`wire EndOp; // End of Operation`
141
142			`reg InProgress; // Operation in progress`
143			`reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle`
144			`reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles`
145			`reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles`
146
147			`reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)`
148			`reg [6:0] BitCounter; // Bit Counter`
149
150
151			`wire MdcFrame; // Frame window for limiting the Mdc`
152			`wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.`
153			`wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.`
154			`wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal`
155
156
157			`wire LatchByte1_d2;`
158			`wire LatchByte0_d2;`
159			`reg LatchByte1_d;`
160			`reg LatchByte0_d;`
161			`reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register`
162
163			`reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data`
164
165
166
167
168
169			`// Generation of the EndBusy signal. It is used for ending the MII Management operation.`
170			`always @ (posedge Clk or posedge Reset)`
171			`begin`
172			`if(Reset)`
173			`begin`
174			`EndBusy_d <= #Tp 1'b0;`
175			`EndBusy <= #Tp 1'b0;`
176			`end`
177			`else`
178			`begin`
179			`EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;`
180			`EndBusy <= #Tp EndBusy_d;`
181			`end`
182			`end`
183
184
185			`// Update MII RX_DATA register`
186			`always @ (posedge Clk or posedge Reset)`
187			`begin`
188			`if(Reset)`
189			`UpdateMIIRX_DATAReg <= #Tp 0;`
190			`else`
191			`if(EndBusy & ~WCtrlDataStart_q)`
192			`UpdateMIIRX_DATAReg <= #Tp 1;`
193			`else`
194			`UpdateMIIRX_DATAReg <= #Tp 0;`
195			`end`
196
197
198
199			`// Generation of the delayed signals used for positive edge triggering.`
200			`always @ (posedge Clk or posedge Reset)`
201			`begin`
202			`if(Reset)`
203			`begin`
204			`WCtrlData_q1 <= #Tp 1'b0;`
205			`WCtrlData_q2 <= #Tp 1'b0;`
206			`WCtrlData_q3 <= #Tp 1'b0;`
207
208			`RStat_q1 <= #Tp 1'b0;`
209			`RStat_q2 <= #Tp 1'b0;`
210			`RStat_q3 <= #Tp 1'b0;`
211
212			`ScanStat_q1 <= #Tp 1'b0;`
213			`ScanStat_q2 <= #Tp 1'b0;`
214			`SyncStatMdcEn <= #Tp 1'b0;`
215			`end`
216			`else`
217			`begin`
218			`WCtrlData_q1 <= #Tp WCtrlData;`
219			`WCtrlData_q2 <= #Tp WCtrlData_q1;`
220			`WCtrlData_q3 <= #Tp WCtrlData_q2;`
221
222			`RStat_q1 <= #Tp RStat;`
223			`RStat_q2 <= #Tp RStat_q1;`
224			`RStat_q3 <= #Tp RStat_q2;`
225
226			`ScanStat_q1 <= #Tp ScanStat;`
227			`ScanStat_q2 <= #Tp ScanStat_q1;`
228			`if(MdcEn)`
229			`SyncStatMdcEn <= #Tp ScanStat_q2;`
230			`end`
231			`end`
232
233
234			`// Generation of the Start Commands (Write Control Data or Read Status)`
235			`always @ (posedge Clk or posedge Reset)`
236			`begin`
237			`if(Reset)`
238			`begin`
239			`WCtrlDataStart <= #Tp 1'b0;`
240			`WCtrlDataStart_q <= #Tp 1'b0;`
241			`RStatStart <= #Tp 1'b0;`
242			`end`
243			`else`
244			`begin`
245			`if(EndBusy)`
246			`begin`
247			`WCtrlDataStart <= #Tp 1'b0;`
248			`RStatStart <= #Tp 1'b0;`
249			`end`
250			`else`
251			`begin`
252			`if(WCtrlData_q2 & ~WCtrlData_q3)`
253			`WCtrlDataStart <= #Tp 1'b1;`
254			`if(RStat_q2 & ~RStat_q3)`
255			`RStatStart <= #Tp 1'b1;`
256			`WCtrlDataStart_q <= #Tp WCtrlDataStart;`
257			`end`
258			`end`
259			`end`
260
261
262			`// Generation of the Nvalid signal (indicates when the status is invalid)`
263			`always @ (posedge Clk or posedge Reset)`
264			`begin`
265			`if(Reset)`
266			`Nvalid <= #Tp 1'b0;`
267			`else`
268			`begin`
269			`if(~InProgress & InProgress_q1)`
270			`begin`
271			`Nvalid <= #Tp 1'b0;`
272			`end`
273			`else`
274			`begin`
275			`if(ScanStat_q2 & ~SyncStatMdcEn)`
276			`Nvalid <= #Tp 1'b1;`
277			`end`
278			`end`
279			`end`
280
281			`// Signals used for the generation of the Operation signals (positive edge)`
282			`always @ (posedge Clk or posedge Reset)`
283			`begin`
284			`if(Reset)`
285			`begin`
286			`WCtrlDataStart_q1 <= #Tp 1'b0;`
287			`WCtrlDataStart_q2 <= #Tp 1'b0;`
288
289			`RStatStart_q1 <= #Tp 1'b0;`
290			`RStatStart_q2 <= #Tp 1'b0;`
291
292			`InProgress_q1 <= #Tp 1'b0;`
293			`InProgress_q2 <= #Tp 1'b0;`
294			`InProgress_q3 <= #Tp 1'b0;`
295
296			`LatchByte0_d <= #Tp 1'b0;`
297			`LatchByte1_d <= #Tp 1'b0;`
298
299			`LatchByte <= #Tp 2'b00;`
300			`end`
301			`else`
302			`begin`
303			`if(MdcEn)`
304			`begin`
305			`WCtrlDataStart_q1 <= #Tp WCtrlDataStart;`
306			`WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;`
307
308			`RStatStart_q1 <= #Tp RStatStart;`
309			`RStatStart_q2 <= #Tp RStatStart_q1;`
310
311			`LatchByte[0] <= #Tp LatchByte0_d;`
312			`LatchByte[1] <= #Tp LatchByte1_d;`
313
314			`LatchByte0_d <= #Tp LatchByte0_d2;`
315			`LatchByte1_d <= #Tp LatchByte1_d2;`
316
317			`InProgress_q1 <= #Tp InProgress;`
318			`InProgress_q2 <= #Tp InProgress_q1;`
319			`InProgress_q3 <= #Tp InProgress_q2;`
320			`end`
321			`end`
322			`end`
323
324
325			`// Generation of the Operation signals`
326			`assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;`
327			`assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;`
328			`assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;`
329			`assign StartOp = WriteDataOp \| ReadStatusOp \| ScanStatusOp;`
330
331			`// Busy`
332			`assign Busy = WCtrlDataStart \| RStatStart \| SyncStatMdcEn \| EndBusy \| InProgress \| InProgress_q3;`
333
334
335			`// Generation of the InProgress signal (indicates when an operation is in progress)`
336			`// Generation of the WriteOp signal (indicates when a write is in progress)`
337			`always @ (posedge Clk or posedge Reset)`
338			`begin`
339			`if(Reset)`
340			`begin`
341			`InProgress <= #Tp 1'b0;`
342			`WriteOp <= #Tp 1'b0;`
343			`end`
344			`else`
345			`begin`
346			`if(MdcEn)`
347			`begin`
348			`if(StartOp)`
349			`begin`
350			`if(~InProgress)`
351			`WriteOp <= #Tp WriteDataOp;`
352			`InProgress <= #Tp 1'b1;`
353			`end`
354			`else`
355			`begin`
356			`if(EndOp)`
357			`begin`
358			`InProgress <= #Tp 1'b0;`
359			`WriteOp <= #Tp 1'b0;`
360			`end`
361			`end`
362			`end`
363			`end`
364			`end`
365
366
367
368			`// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)`
369			`always @ (posedge Clk or posedge Reset)`
370			`begin`
371			`if(Reset)`
372			`BitCounter[6:0] <= #Tp 7'h0;`
373			`else`
374			`begin`
375			`if(MdcEn)`
376			`begin`
377			`if(InProgress)`
378			`begin`
379			`if(NoPre & ( BitCounter == 7'h0 ))`
380			`BitCounter[6:0] <= #Tp 7'h21;`
381			`else`
382			`BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;`
383			`end`
384			`else`
385			`BitCounter[6:0] <= #Tp 7'h0;`
386			`end`
387			`end`
388			`end`
389
390
391			`// Operation ends when the Bit Counter reaches 63`
392			`assign EndOp = BitCounter==63;`
393
394			`assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) \| (~NoPre & (BitCounter == 7'h20)));`
395			`assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);`
396			`assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);`
397			`assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);`
398
399
400			`// Latch Byte selects which part of Read Status Data is updated from the shift register`
401			`assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;`
402			`assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;`
403
404
405			`// Connecting the Clock Generator Module`
406			`eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)`
407			`);`
408
409			`// Connecting the Shift Register Module`
410			`eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),`
411			`.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),`
412			`.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)`
413			`);`
414
415			`// Connecting the Output Control Module`
416			`eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),`
417			`.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),`
418			`.Mdo(Mdo), .MdoEn(MdoEn)`
419			`);`
420
421			`endmodule`