OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Blame information for rev 85

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 50 billditt 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  eth_rxaddrcheck.v                                           ////
4 
////                                                              ////
5 
////  This file is part of the Ethernet IP core project           ////
6 
////  http://www.opencores.org/cores/ethmac/                      ////
7 
////                                                              ////
8 
////  Author(s):                                                  ////
9 
////      - Bill Dittenhofer (billditt@aol.com)                   ////
10 
////                                                              ////
11 
////  All additional information is avaliable in the Readme.txt   ////
12 
////  file.                                                       ////
13 
////                                                              ////
14 
//////////////////////////////////////////////////////////////////////
15 
////                                                              ////
16 
//// Copyright (C) 2001 Authors                                   ////
17 
////                                                              ////
18 
//// This source file may be used and distributed without         ////
19 
//// restriction provided that this copyright statement is not    ////
20 
//// removed from the file and that any derivative work contains  ////
21 
//// the original copyright notice and the associated disclaimer. ////
22 
////                                                              ////
23 
//// This source file is free software; you can redistribute it   ////
24 
//// and/or modify it under the terms of the GNU Lesser General   ////
25 
//// Public License as published by the Free Software Foundation; ////
26 
//// either version 2.1 of the License, or (at your option) any   ////
27 
//// later version.                                               ////
28 
////                                                              ////
29 
//// This source is distributed in the hope that it will be       ////
30 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33 
//// details.                                                     ////
34 
////                                                              ////
35 
//// You should have received a copy of the GNU Lesser General    ////
36 
//// Public License along with this source; if not, download it   ////
37 
//// from http://www.opencores.org/lgpl.shtml                     ////
38 
////                                                              ////
39 
//////////////////////////////////////////////////////////////////////
40 
//
41 
// CVS Revision History
42 
//
43 85 mohor 
// $Log: not supported by cvs2svn $
44 
//
45 50 billditt 
// Revision 1.1  2002/02/08 12:51:54  ditt
46 
// Initial release of the ethernet addresscheck module.
47 
//
48 
//
49 
//
50 
//
51 
//
52 
 
53 
 
54 
`include "timescale.v"
55 
 
56 
 
57 65 mohor 
module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
58 
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
59 
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
60 
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
61 
                       Multicast, MAC, RxAbort
62 
                      );
63 50 billditt 
 
64 
parameter Tp = 1;
65 
 
66 
  input        MRxClk;
67 
  input        Reset;
68 
  input [7:0]  RxData;
69 
  input        Broadcast;
70 
  input        r_Bro;
71 
  input        r_Pro;
72 
  input        ByteCntEq2;
73 
  input        ByteCntEq3;
74 
  input        ByteCntEq4;
75 
  input        ByteCntEq5;
76 
  input        ByteCntEq6;
77 
  input        ByteCntEq7;
78 
  input [31:0] HASH0;
79 
  input [31:0] HASH1;
80 
  input [5:0]  CrcHash;
81 
  input        CrcHashGood;
82 
  input        Multicast;
83 
  input [47:0] MAC;
84 
  input [1:0]  StateData;
85 
  input        RxEndFrm;
86 
 
87 
  output       RxAbort;
88 
 
89 
 
90 
 wire BroadcastOK;
91 
 wire ByteCntEq2;
92 
 wire ByteCntEq3;
93 
 wire ByteCntEq4;
94 
 wire ByteCntEq5;
95 
 wire RxAddressInvalid;
96 
 wire RxCheckEn;
97 65 mohor 
 wire HashBit;
98 
 wire [31:0] IntHash;
99 50 billditt 
 reg [7:0]  ByteHash;
100 
 reg MulticastOK;
101 
 reg UnicastOK;
102 
 reg RxAbort;
103 
 reg CrcHashGood_d;  // delay HashGood by one cycle
104 
 
105 65 mohor 
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK);
106 50 billditt 
 
107 75 mohor 
assign BroadcastOK = Broadcast & ~r_Bro;
108 50 billditt 
 
109 65 mohor 
assign RxCheckEn   = | StateData;
110 50 billditt 
 
111 
 // Address Error Reported at end of address cycle
112 
 // RxAbort clears after one cycle
113 
 
114 65 mohor 
always @ (posedge MRxClk or posedge Reset)
115 
begin
116 
  if(Reset)
117 
    RxAbort <= #Tp 1'b0;
118 
  else if(CrcHashGood_d & RxAddressInvalid & ~r_Pro & RxCheckEn)
119 
    RxAbort <= #Tp 1'b1;
120 
  else
121 
    RxAbort <= #Tp 1'b0;
122 
end
123 50 billditt 
 
124 65 mohor 
// Hash Address Check, Multicast
125 50 billditt 
 
126 
 
127 
// delay CrcHashGood by 1 cycle
128 
always @ (posedge MRxClk or posedge Reset)
129 65 mohor 
begin
130 
  if(Reset)
131 
    CrcHashGood_d <= #Tp 1'b0;
132 
  else
133 
    CrcHashGood_d <= #Tp CrcHashGood;
134 
end
135 50 billditt 
 
136 65 mohor 
always @ (posedge MRxClk or posedge Reset)
137 
begin
138 
  if(Reset)
139 
    MulticastOK <= #Tp 1'b0;
140 
  else if(RxEndFrm | RxAbort)
141 
    MulticastOK <= #Tp 1'b0;
142 
  else if(CrcHashGood & Multicast)
143 
    MulticastOK <= #Tp HashBit;
144 
end
145 50 billditt 
 
146 
 
147 65 mohor 
// Address Detection (unicast)
148 
// start with ByteCntEq2 due to delay of addres from RxData
149 50 billditt 
always @ (posedge MRxClk or posedge Reset)
150 
begin
151 
  if(Reset)
152 
    UnicastOK <= #Tp 1'b0;
153 
  else
154 65 mohor 
  if(RxCheckEn & ByteCntEq2)
155 83 mohor 
    UnicastOK <= #Tp   RxData[7:0] == MAC[47:40];
156 50 billditt 
  else
157 65 mohor 
  if(RxCheckEn & ByteCntEq3)
158 83 mohor 
    UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
159 50 billditt 
  else
160 65 mohor 
  if(RxCheckEn & ByteCntEq4)
161 83 mohor 
    UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
162 50 billditt 
  else
163 65 mohor 
  if(RxCheckEn & ByteCntEq5)
164 83 mohor 
    UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
165 50 billditt 
  else
166 65 mohor 
  if(RxCheckEn & ByteCntEq6)
167 83 mohor 
    UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8])  & UnicastOK;
168 50 billditt 
  else
169 65 mohor 
  if(RxCheckEn & ByteCntEq7)
170 83 mohor 
    UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0])   & UnicastOK;
171 50 billditt 
  else
172 
  if(RxEndFrm | RxAbort)
173 
    UnicastOK <= #Tp 1'b0;
174 
end
175 
 
176 65 mohor 
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
177 
 
178 
always@(CrcHash or IntHash)
179 
begin
180 
  case(CrcHash[4:3])
181 
    2'b00: ByteHash = IntHash[7:0];
182 
    2'b01: ByteHash = IntHash[15:8];
183 
    2'b10: ByteHash = IntHash[23:16];
184 
    2'b11: ByteHash = IntHash[31:24];
185 
  endcase
186 
end
187 
 
188 
assign HashBit = ByteHash[CrcHash[2:0]];
189 50 billditt 
 
190 65 mohor 
 
191 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.