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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 338

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
45
// When in full duplex, transmit was sometimes blocked. Fixed.
46
//
47 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
48
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
49
// anywhere. Removed.
50
//
51 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
52
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
53
// synchronized.
54
//
55 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
56
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
57
// that a frame was received because of the promiscous mode.
58
//
59 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
60
// RxError is not generated when small frame reception is enabled and small
61
// frames are received.
62
//
63 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
64
// case changed to casex.
65
//
66 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
67
// Changed BIST scan signals.
68
//
69 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
70
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
71
//
72 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
73
// TxStatus is written after last access to the TX fifo is finished (in case of abort
74
// or retry). TxDone is fixed.
75
//
76 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
77
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
78
// TxDone and TxRetry are generated after the current WISHBONE access is
79
// finished.
80
//
81 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
82
// BIST added.
83
//
84 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
85
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
86
//
87 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
88
// Reception is possible after RxPointer is read and not after BD is read. For
89
// that reason RxBDReady is changed to RxReady.
90
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
91
// comes, interrupt is generated.
92
//
93 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
94
// Ethernet debug registers removed.
95
//
96 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
97
// Async reset for WB_ACK_O removed (when core was in reset, it was
98
// impossible to access BDs).
99
// RxPointers and TxPointers names changed to be more descriptive.
100
// TxUnderRun synchronized.
101
//
102 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
103
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
104
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
105
// was not used OK.
106
//
107 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
108
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
109
// need to multiply or devide any more.
110
//
111 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
112
// WriteRxDataToMemory signal changed so end of frame (when last word is
113
// written to fifo) is changed.
114
//
115 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
116
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
117
//
118 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
119
// ShiftEnded synchronization changed.
120
//
121 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
122
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
123
//
124 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
125
// RxPointer bug fixed.
126
//
127 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
128
// Previous bug wasn't succesfully removed. Now fixed.
129
//
130 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
131
// Master state machine had a bug when switching from master write to
132
// master read.
133
//
134 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
135
// m_wb_cyc_o signal released after every single transfer.
136
//
137 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
138
// Outputs registered. Reset changed for eth_wishbone module.
139
//
140 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
141
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
142
// bug fixed.
143
//
144 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
145
// Small typo fixed.
146
//
147 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
148
// Any address can be used for Tx and Rx BD pointers. Address does not need
149
// to be aligned.
150
//
151 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
152
// Comments in Slovene language removed.
153
//
154 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
155
// casex changed with case, fifo reset changed.
156
//
157 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
158
// rx_fifo was not always cleared ok. Fixed.
159
//
160 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
161
// Status was not latched correctly sometimes. Fixed.
162
//
163 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
164
// Big Endian problem when sending frames fixed.
165
//
166 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
167
// Byte ordering changed (Big Endian used). casex changed with case because
168
// Xilinx Foundation had problems. Tested in HW. It WORKS.
169
//
170 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
171
// Small fixes for external/internal DMA missmatches.
172
//
173 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
174
// Interrupts changed
175
//
176 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
177
// Status was not written correctly when frames were discarted because of
178
// address mismatch.
179
//
180 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
181
// RxStartFrm cleared when abort or retry comes.
182
//
183 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
184
// Changes that were lost when updating from 1.5 to 1.8 fixed.
185
//
186 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
187
// Addition  of new module eth_addrcheck.v
188
//
189
// Revision 1.7  2002/02/12 17:03:47  mohor
190
// RxOverRun added to statuses.
191
//
192
// Revision 1.6  2002/02/11 09:18:22  mohor
193
// Tx status is written back to the BD.
194
//
195 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
196
// Rx status is written back to the BD.
197
//
198 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
199
// non-DMA host interface added. Select the right configutation in eth_defines.
200
//
201 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
202
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
203
// MHz. Statuses, overrun, control frame transmission and reception still  need
204
// to be fixed.
205
//
206 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
207
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
208
// added.
209
//
210 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
211
// Initial version. Equals to eth_wishbonedma.v at this moment.
212 38 mohor
//
213
//
214
//
215
 
216
`include "eth_defines.v"
217
`include "timescale.v"
218
 
219
 
220
module eth_wishbone
221
   (
222
 
223
    // WISHBONE common
224 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
225 38 mohor
 
226
    // WISHBONE slave
227 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
228 40 mohor
    BDCs,
229 38 mohor
 
230 40 mohor
    Reset,
231
 
232 39 mohor
    // WISHBONE master
233
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
234
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
235
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
236
 
237 219 mohor
`ifdef ETH_WISHBONE_B3
238
    m_wb_cti_o, m_wb_bte_o,
239
`endif
240
 
241 38 mohor
    //TX
242 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
243 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
244 38 mohor
    PerPacketPad,
245
 
246
    //RX
247 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
248 38 mohor
 
249
    // Register
250 270 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
251 38 mohor
 
252
    // Interrupts
253 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
254 42 mohor
 
255 60 mohor
    // Rx Status
256 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
257 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
258 261 mohor
    ReceivedPauseFrm,
259 60 mohor
 
260
    // Tx Status
261 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
262
 
263 210 mohor
    // Bist
264
`ifdef ETH_BIST
265 227 tadejm
    ,
266
    // debug chain signals
267
    scanb_rst,      // bist scan reset
268
    scanb_clk,      // bist scan clock
269
    scanb_si,       // bist scan serial in
270
    scanb_so,       // bist scan serial out
271
    scanb_en        // bist scan shift enable
272 210 mohor
`endif
273
 
274
 
275
 
276 38 mohor
                );
277
 
278
 
279
parameter Tp = 1;
280
 
281 150 mohor
 
282 38 mohor
// WISHBONE common
283
input           WB_CLK_I;       // WISHBONE clock
284
input  [31:0]   WB_DAT_I;       // WISHBONE data input
285
output [31:0]   WB_DAT_O;       // WISHBONE data output
286
 
287
// WISHBONE slave
288
input   [9:2]   WB_ADR_I;       // WISHBONE address input
289
input           WB_WE_I;        // WISHBONE write enable input
290
input           BDCs;           // Buffer descriptors are selected
291
output          WB_ACK_O;       // WISHBONE acknowledge output
292
 
293 39 mohor
// WISHBONE master
294
output  [31:0]  m_wb_adr_o;     // 
295
output   [3:0]  m_wb_sel_o;     // 
296
output          m_wb_we_o;      // 
297
output  [31:0]  m_wb_dat_o;     // 
298
output          m_wb_cyc_o;     // 
299
output          m_wb_stb_o;     // 
300
input   [31:0]  m_wb_dat_i;     // 
301
input           m_wb_ack_i;     // 
302
input           m_wb_err_i;     // 
303
 
304 219 mohor
`ifdef ETH_WISHBONE_B3
305
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
306
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
307
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
308
`endif
309
 
310 40 mohor
input           Reset;       // Reset signal
311 39 mohor
 
312 60 mohor
// Rx Status signals
313 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
314
input           LatchedCrcError;  // CRC error
315
input           RxLateCollision;  // Late collision occured while receiving frame
316
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
317
input           DribbleNibble;    // Extra nibble received
318
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
319
input    [15:0] RxLength;         // Length of the incoming frame
320
input           LoadRxStatus;     // Rx status was loaded
321 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
322 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
323 261 mohor
input           r_RxFlow;
324 270 mohor
input           r_PassAll;
325 261 mohor
input           ReceivedPauseFrm;
326 39 mohor
 
327 60 mohor
// Tx Status signals
328
input     [3:0] RetryCntLatched;  // Latched Retry Counter
329
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
330
input           LateCollLatched;  // Late collision occured
331
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
332
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
333
 
334 38 mohor
// Tx
335
input           MTxClk;         // Transmit clock (from PHY)
336
input           TxUsedData;     // Transmit packet used data
337
input           TxRetry;        // Transmit packet retry
338
input           TxAbort;        // Transmit packet abort
339
input           TxDone;         // Transmission ended
340
output          TxStartFrm;     // Transmit packet start frame
341
output          TxEndFrm;       // Transmit packet end frame
342
output  [7:0]   TxData;         // Transmit packet data byte
343
output          TxUnderRun;     // Transmit packet under-run
344
output          PerPacketCrcEn; // Per packet crc enable
345
output          PerPacketPad;   // Per packet pading
346
 
347
// Rx
348
input           MRxClk;         // Receive clock (from PHY)
349
input   [7:0]   RxData;         // Received data byte (from PHY)
350
input           RxValid;        // 
351
input           RxStartFrm;     // 
352
input           RxEndFrm;       // 
353 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
354 38 mohor
 
355
//Register
356
input           r_TxEn;         // Transmit enable
357
input           r_RxEn;         // Receive enable
358
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
359
input           TX_BD_NUM_Wr;   // RxBDNumber written
360
 
361
// Interrupts
362
output TxB_IRQ;
363
output TxE_IRQ;
364
output RxB_IRQ;
365 77 mohor
output RxE_IRQ;
366 38 mohor
output Busy_IRQ;
367
 
368 77 mohor
 
369 210 mohor
// Bist
370
`ifdef ETH_BIST
371 227 tadejm
input   scanb_rst;      // bist scan reset
372
input   scanb_clk;      // bist scan clock
373
input   scanb_si;       // bist scan serial in
374
output  scanb_so;       // bist scan serial out
375
input   scanb_en;       // bist scan shift enable
376 210 mohor
`endif
377
 
378 77 mohor
reg TxB_IRQ;
379
reg TxE_IRQ;
380
reg RxB_IRQ;
381
reg RxE_IRQ;
382
 
383 38 mohor
reg             TxStartFrm;
384
reg             TxEndFrm;
385
reg     [7:0]   TxData;
386
 
387
reg             TxUnderRun;
388 60 mohor
reg             TxUnderRun_wb;
389 38 mohor
 
390
reg             TxBDRead;
391 39 mohor
wire            TxStatusWrite;
392 38 mohor
 
393
reg     [1:0]   TxValidBytesLatched;
394
 
395
reg    [15:0]   TxLength;
396 60 mohor
reg    [15:0]   LatchedTxLength;
397
reg   [14:11]   TxStatus;
398 38 mohor
 
399 60 mohor
reg   [14:13]   RxStatus;
400 38 mohor
 
401
reg             TxStartFrm_wb;
402
reg             TxRetry_wb;
403 39 mohor
reg             TxAbort_wb;
404 38 mohor
reg             TxDone_wb;
405
 
406
reg             TxDone_wb_q;
407
reg             TxAbort_wb_q;
408 39 mohor
reg             TxRetry_wb_q;
409 219 mohor
reg             TxRetryPacket;
410 221 mohor
reg             TxRetryPacket_NotCleared;
411
reg             TxDonePacket;
412
reg             TxDonePacket_NotCleared;
413 219 mohor
reg             TxAbortPacket;
414 221 mohor
reg             TxAbortPacket_NotCleared;
415 38 mohor
reg             RxBDReady;
416 166 mohor
reg             RxReady;
417 38 mohor
reg             TxBDReady;
418
 
419
reg             RxBDRead;
420 40 mohor
wire            RxStatusWrite;
421 38 mohor
 
422
reg    [31:0]   TxDataLatched;
423
reg     [1:0]   TxByteCnt;
424
reg             LastWord;
425 39 mohor
reg             ReadTxDataFromFifo_tck;
426 38 mohor
 
427
reg             BlockingTxStatusWrite;
428
reg             BlockingTxBDRead;
429
 
430 40 mohor
reg             Flop;
431 38 mohor
 
432
reg     [7:0]   TxBDAddress;
433
reg     [7:0]   RxBDAddress;
434
 
435
reg             TxRetrySync1;
436
reg             TxAbortSync1;
437 39 mohor
reg             TxDoneSync1;
438 38 mohor
 
439
reg             TxAbort_q;
440
reg             TxRetry_q;
441
reg             TxUsedData_q;
442
 
443
reg    [31:0]   RxDataLatched2;
444 82 mohor
 
445
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
446
 
447 38 mohor
reg     [1:0]   RxValidBytes;
448
reg     [1:0]   RxByteCnt;
449
reg             LastByteIn;
450
reg             ShiftWillEnd;
451
 
452 40 mohor
reg             WriteRxDataToFifo;
453 42 mohor
reg    [15:0]   LatchedRxLength;
454 64 mohor
reg             RxAbortLatched;
455 38 mohor
 
456 40 mohor
reg             ShiftEnded;
457 60 mohor
reg             RxOverrun;
458 38 mohor
 
459 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
460
reg             BDRead;                     // BD Read access from WISHBONE side
461 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
462
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
463 38 mohor
 
464 39 mohor
reg             TxEndFrm_wb;
465 38 mohor
 
466 39 mohor
wire            TxRetryPulse;
467 38 mohor
wire            TxDonePulse;
468
wire            TxAbortPulse;
469
 
470
wire            StartRxBDRead;
471
 
472
wire            StartTxBDRead;
473
 
474
wire            TxIRQEn;
475
wire            WrapTxStatusBit;
476
 
477 77 mohor
wire            RxIRQEn;
478 38 mohor
wire            WrapRxStatusBit;
479
 
480
wire    [1:0]   TxValidBytes;
481
 
482
wire    [7:0]   TempTxBDAddress;
483
wire    [7:0]   TempRxBDAddress;
484
 
485
wire            SetGotData;
486
wire            GotDataEvaluate;
487
 
488 106 mohor
reg             WB_ACK_O;
489 38 mohor
 
490 261 mohor
wire    [8:0]   RxStatusIn;
491
reg     [8:0]   RxStatusInLatched;
492 42 mohor
 
493 39 mohor
reg WbEn, WbEn_q;
494
reg RxEn, RxEn_q;
495
reg TxEn, TxEn_q;
496 38 mohor
 
497 39 mohor
wire ram_ce;
498
wire ram_we;
499
wire ram_oe;
500
reg [7:0]   ram_addr;
501
reg [31:0]  ram_di;
502
wire [31:0] ram_do;
503 38 mohor
 
504 39 mohor
wire StartTxPointerRead;
505
reg  TxPointerRead;
506
reg TxEn_needed;
507 40 mohor
reg RxEn_needed;
508 38 mohor
 
509 40 mohor
wire StartRxPointerRead;
510
reg RxPointerRead;
511 38 mohor
 
512 219 mohor
`ifdef ETH_WISHBONE_B3
513
assign m_wb_bte_o = 2'b00;    // Linear burst
514
`endif
515 39 mohor
 
516 219 mohor
 
517 159 mohor
always @ (posedge WB_CLK_I)
518 40 mohor
begin
519 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
520 40 mohor
end
521 39 mohor
 
522 106 mohor
assign WB_DAT_O = ram_do;
523 39 mohor
 
524 41 mohor
// Generic synchronous single-port RAM interface
525 119 mohor
eth_spram_256x32 bd_ram (
526 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
527 210 mohor
`ifdef ETH_BIST
528 227 tadejm
  ,
529
  .scanb_rst      (scanb_rst),
530
  .scanb_clk      (scanb_clk),
531
  .scanb_si       (scanb_si),
532
  .scanb_so       (scanb_so),
533
  .scanb_en       (scanb_en)
534 210 mohor
`endif
535 39 mohor
);
536 41 mohor
 
537 39 mohor
assign ram_ce = 1'b1;
538 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
539 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
540 39 mohor
 
541
 
542 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
543 38 mohor
begin
544 40 mohor
  if(Reset)
545 39 mohor
    TxEn_needed <=#Tp 1'b0;
546 38 mohor
  else
547 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
548 39 mohor
    TxEn_needed <=#Tp 1'b1;
549
  else
550
  if(TxPointerRead & TxEn & TxEn_q)
551
    TxEn_needed <=#Tp 1'b0;
552 38 mohor
end
553
 
554 39 mohor
// Enabling access to the RAM for three devices.
555 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
556 39 mohor
begin
557 40 mohor
  if(Reset)
558 39 mohor
    begin
559
      WbEn <=#Tp 1'b1;
560
      RxEn <=#Tp 1'b0;
561
      TxEn <=#Tp 1'b0;
562
      ram_addr <=#Tp 8'h0;
563
      ram_di <=#Tp 32'h0;
564 77 mohor
      BDRead <=#Tp 1'b0;
565
      BDWrite <=#Tp 1'b0;
566 39 mohor
    end
567
  else
568
    begin
569
      // Switching between three stages depends on enable signals
570 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
571
        5'b100_10, 5'b100_11 :
572 39 mohor
          begin
573
            WbEn <=#Tp 1'b0;
574
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
575
            TxEn <=#Tp 1'b0;
576 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
577 39 mohor
            ram_di <=#Tp RxBDDataIn;
578
          end
579
        5'b100_01 :
580
          begin
581
            WbEn <=#Tp 1'b0;
582
            RxEn <=#Tp 1'b0;
583
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
584
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
585
            ram_di <=#Tp TxBDDataIn;
586
          end
587 90 mohor
        5'b010_00, 5'b010_10 :
588 39 mohor
          begin
589
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
590
            RxEn <=#Tp 1'b0;
591
            TxEn <=#Tp 1'b0;
592
            ram_addr <=#Tp WB_ADR_I[9:2];
593
            ram_di <=#Tp WB_DAT_I;
594 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
595
            BDRead <=#Tp BDCs & ~WB_WE_I;
596 39 mohor
          end
597 90 mohor
        5'b010_01, 5'b010_11 :
598 39 mohor
          begin
599
            WbEn <=#Tp 1'b0;
600
            RxEn <=#Tp 1'b0;
601
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
602
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
603
            ram_di <=#Tp TxBDDataIn;
604
          end
605 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
606 39 mohor
          begin
607
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
608
            RxEn <=#Tp 1'b0;
609
            TxEn <=#Tp 1'b0;
610
            ram_addr <=#Tp WB_ADR_I[9:2];
611
            ram_di <=#Tp WB_DAT_I;
612 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
613
            BDRead <=#Tp BDCs & ~WB_WE_I;
614 39 mohor
          end
615
        5'b100_00 :
616
          begin
617
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
618
          end
619
        5'b000_00 :
620
          begin
621
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
622
            RxEn <=#Tp 1'b0;
623
            TxEn <=#Tp 1'b0;
624
            ram_addr <=#Tp WB_ADR_I[9:2];
625
            ram_di <=#Tp WB_DAT_I;
626 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
627
            BDRead <=#Tp BDCs & ~WB_WE_I;
628 39 mohor
          end
629
      endcase
630
    end
631
end
632
 
633
 
634
// Delayed stage signals
635 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
636 39 mohor
begin
637 40 mohor
  if(Reset)
638 39 mohor
    begin
639
      WbEn_q <=#Tp 1'b0;
640
      RxEn_q <=#Tp 1'b0;
641
      TxEn_q <=#Tp 1'b0;
642
    end
643
  else
644
    begin
645
      WbEn_q <=#Tp WbEn;
646
      RxEn_q <=#Tp RxEn;
647
      TxEn_q <=#Tp TxEn;
648
    end
649
end
650
 
651 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
652 40 mohor
always @ (posedge MTxClk or posedge Reset)
653 38 mohor
begin
654 40 mohor
  if(Reset)
655 38 mohor
    Flop <=#Tp 1'b0;
656
  else
657
  if(TxDone | TxAbort | TxRetry_q)
658
    Flop <=#Tp 1'b0;
659
  else
660
  if(TxUsedData)
661
    Flop <=#Tp ~Flop;
662
end
663
 
664 39 mohor
wire ResetTxBDReady;
665
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
666 38 mohor
 
667
// Latching READY status of the Tx buffer descriptor
668 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
669 38 mohor
begin
670 40 mohor
  if(Reset)
671 38 mohor
    TxBDReady <=#Tp 1'b0;
672
  else
673 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
674
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
675
  else                                                // Only packets larger then 4 bytes are transmitted.
676 39 mohor
  if(ResetTxBDReady)
677 38 mohor
    TxBDReady <=#Tp 1'b0;
678
end
679
 
680
 
681 39 mohor
// Reading the Tx buffer descriptor
682 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
683 39 mohor
 
684 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
685 38 mohor
begin
686 40 mohor
  if(Reset)
687 39 mohor
    TxBDRead <=#Tp 1'b1;
688 38 mohor
  else
689 110 mohor
  if(StartTxBDRead)
690 39 mohor
    TxBDRead <=#Tp 1'b1;
691 38 mohor
  else
692 39 mohor
  if(TxBDReady)
693
    TxBDRead <=#Tp 1'b0;
694 38 mohor
end
695
 
696
 
697 39 mohor
// Reading Tx BD pointer
698
assign StartTxPointerRead = TxBDRead & TxBDReady;
699 38 mohor
 
700 39 mohor
// Reading Tx BD Pointer
701 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
702 38 mohor
begin
703 40 mohor
  if(Reset)
704 39 mohor
    TxPointerRead <=#Tp 1'b0;
705 38 mohor
  else
706 39 mohor
  if(StartTxPointerRead)
707
    TxPointerRead <=#Tp 1'b1;
708 38 mohor
  else
709 39 mohor
  if(TxEn_q)
710
    TxPointerRead <=#Tp 1'b0;
711 38 mohor
end
712
 
713
 
714 39 mohor
// Writing status back to the Tx buffer descriptor
715 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
716 38 mohor
 
717
 
718
 
719 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
720 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
721 38 mohor
begin
722 40 mohor
  if(Reset)
723 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
724 38 mohor
  else
725 39 mohor
  if(TxStatusWrite)
726
    BlockingTxStatusWrite <=#Tp 1'b1;
727 38 mohor
  else
728 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
729
    BlockingTxStatusWrite <=#Tp 1'b0;
730 38 mohor
end
731
 
732
 
733 159 mohor
reg BlockingTxStatusWrite_sync1;
734
reg BlockingTxStatusWrite_sync2;
735
 
736
// Synchronizing BlockingTxStatusWrite to MTxClk
737
always @ (posedge MTxClk or posedge Reset)
738
begin
739
  if(Reset)
740
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
741
  else
742
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
743
end
744
 
745
// Synchronizing BlockingTxStatusWrite to MTxClk
746
always @ (posedge MTxClk or posedge Reset)
747
begin
748
  if(Reset)
749
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
750
  else
751
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
752
end
753
 
754
 
755 39 mohor
// TxBDRead state is activated only once. 
756 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
757 39 mohor
begin
758 40 mohor
  if(Reset)
759 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
760
  else
761 110 mohor
  if(StartTxBDRead)
762 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
763
  else
764 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
765 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
766
end
767 38 mohor
 
768
 
769 39 mohor
// Latching status from the tx buffer descriptor
770
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
771 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
772 38 mohor
begin
773 40 mohor
  if(Reset)
774 60 mohor
    TxStatus <=#Tp 4'h0;
775 38 mohor
  else
776 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
777 60 mohor
    TxStatus <=#Tp ram_do[14:11];
778 38 mohor
end
779
 
780 40 mohor
reg ReadTxDataFromMemory;
781
wire WriteRxDataToMemory;
782 38 mohor
 
783 39 mohor
reg MasterWbTX;
784
reg MasterWbRX;
785
 
786
reg [31:0] m_wb_adr_o;
787
reg        m_wb_cyc_o;
788
reg        m_wb_stb_o;
789 96 mohor
reg  [3:0] m_wb_sel_o;
790 39 mohor
reg        m_wb_we_o;
791 40 mohor
 
792 39 mohor
wire TxLengthEq0;
793
wire TxLengthLt4;
794
 
795 150 mohor
reg BlockingIncrementTxPointer;
796 159 mohor
reg [31:2] TxPointerMSB;
797
reg [1:0]  TxPointerLSB;
798
reg [1:0]  TxPointerLSB_rst;
799
reg [31:2] RxPointerMSB;
800
reg [1:0]  RxPointerLSB_rst;
801 39 mohor
 
802 150 mohor
wire RxBurstAcc;
803
wire RxWordAcc;
804
wire RxHalfAcc;
805
wire RxByteAcc;
806
 
807 39 mohor
//Latching length from the buffer descriptor;
808 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
809 38 mohor
begin
810 40 mohor
  if(Reset)
811 39 mohor
    TxLength <=#Tp 16'h0;
812 38 mohor
  else
813 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
814
    TxLength <=#Tp ram_do[31:16];
815 38 mohor
  else
816 39 mohor
  if(MasterWbTX & m_wb_ack_i)
817
    begin
818
      if(TxLengthLt4)
819
        TxLength <=#Tp 16'h0;
820 150 mohor
      else
821 159 mohor
      if(TxPointerLSB_rst==2'h0)
822 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
823 39 mohor
      else
824 159 mohor
      if(TxPointerLSB_rst==2'h1)
825 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
826
      else
827 159 mohor
      if(TxPointerLSB_rst==2'h2)
828 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
829
      else
830 159 mohor
      if(TxPointerLSB_rst==2'h3)
831 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
832 39 mohor
    end
833 38 mohor
end
834
 
835 96 mohor
 
836
 
837 60 mohor
//Latching length from the buffer descriptor;
838
always @ (posedge WB_CLK_I or posedge Reset)
839
begin
840
  if(Reset)
841
    LatchedTxLength <=#Tp 16'h0;
842
  else
843
  if(TxEn & TxEn_q & TxBDRead)
844
    LatchedTxLength <=#Tp ram_do[31:16];
845
end
846
 
847 39 mohor
assign TxLengthEq0 = TxLength == 0;
848
assign TxLengthLt4 = TxLength < 4;
849 38 mohor
 
850 150 mohor
reg cyc_cleared;
851
reg IncrTxPointer;
852 39 mohor
 
853
 
854 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
855
// because TxPointerMSB is only used for word-aligned accesses.
856 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
857 38 mohor
begin
858 40 mohor
  if(Reset)
859 159 mohor
    TxPointerMSB <=#Tp 30'h0;
860 38 mohor
  else
861 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
862 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
863 38 mohor
  else
864 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
865 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
866 38 mohor
end
867
 
868 96 mohor
 
869 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
870
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
871
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
872
// set by this two bits.
873 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
874
begin
875
  if(Reset)
876 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
877 96 mohor
  else
878
  if(TxEn & TxEn_q & TxPointerRead)
879 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
880 96 mohor
end
881
 
882
 
883 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
884
// After the read access, TxLength needs to be decremented for the number of the valid
885
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
886
// valid so this two bits are reset to zero. 
887 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
888
begin
889
  if(Reset)
890 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
891 150 mohor
  else
892
  if(TxEn & TxEn_q & TxPointerRead)
893 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
894 150 mohor
  else
895
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
896 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
897 150 mohor
end
898 96 mohor
 
899 150 mohor
 
900 159 mohor
reg  [3:0] RxByteSel;
901 39 mohor
wire MasterAccessFinished;
902 38 mohor
 
903 39 mohor
 
904 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
905 38 mohor
begin
906 40 mohor
  if(Reset)
907 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
908 38 mohor
  else
909 39 mohor
  if(MasterAccessFinished)
910
    BlockingIncrementTxPointer <=#Tp 0;
911 38 mohor
  else
912 150 mohor
  if(IncrTxPointer)
913 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
914 38 mohor
end
915
 
916
 
917 39 mohor
wire TxBufferAlmostFull;
918
wire TxBufferFull;
919
wire TxBufferEmpty;
920
wire TxBufferAlmostEmpty;
921 40 mohor
wire SetReadTxDataFromMemory;
922 39 mohor
 
923 40 mohor
reg BlockReadTxDataFromMemory;
924 39 mohor
 
925 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
926 39 mohor
 
927 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
928 38 mohor
begin
929 40 mohor
  if(Reset)
930
    ReadTxDataFromMemory <=#Tp 1'b0;
931 38 mohor
  else
932 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
933 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
934 39 mohor
  else
935 40 mohor
  if(SetReadTxDataFromMemory)
936
    ReadTxDataFromMemory <=#Tp 1'b1;
937 38 mohor
end
938
 
939 226 tadejm
reg tx_burst_en;
940
reg rx_burst_en;
941 221 mohor
reg BlockingLastReadOn_Abort_Retry;
942
 
943
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
944 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
945 221 mohor
 
946 39 mohor
wire [31:0] TxData_wb;
947
wire ReadTxDataFromFifo_wb;
948 38 mohor
 
949 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
950 38 mohor
begin
951 40 mohor
  if(Reset)
952
    BlockReadTxDataFromMemory <=#Tp 1'b0;
953 38 mohor
  else
954 269 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket | TxRetryPacket)))
955 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
956 219 mohor
  else
957 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
958 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
959 39 mohor
end
960
 
961
 
962 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
963
begin
964
  if(Reset)
965
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
966
  else
967
  if(TxAbortPacket | TxRetryPacket)
968
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
969
  else
970
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
971
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
972
end
973 39 mohor
 
974 221 mohor
 
975
 
976
 
977 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
978 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
979
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
980 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
981
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
982 159 mohor
 
983 226 tadejm
wire rx_burst;
984
wire enough_data_in_rxfifo_for_burst;
985
wire enough_data_in_rxfifo_for_burst_plus1;
986 229 mohor
 
987 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
988 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
989 39 mohor
begin
990 40 mohor
  if(Reset)
991 38 mohor
    begin
992 39 mohor
      MasterWbTX <=#Tp 1'b0;
993
      MasterWbRX <=#Tp 1'b0;
994
      m_wb_adr_o <=#Tp 32'h0;
995
      m_wb_cyc_o <=#Tp 1'b0;
996
      m_wb_stb_o <=#Tp 1'b0;
997
      m_wb_we_o  <=#Tp 1'b0;
998 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
999 110 mohor
      cyc_cleared<=#Tp 1'b0;
1000 226 tadejm
      tx_burst_cnt<=#Tp 0;
1001
      rx_burst_cnt<=#Tp 0;
1002 150 mohor
      IncrTxPointer<=#Tp 1'b0;
1003 226 tadejm
      tx_burst_en<=#Tp 1'b1;
1004
      rx_burst_en<=#Tp 1'b0;
1005
      `ifdef ETH_WISHBONE_B3
1006
        m_wb_cti_o <=#Tp 3'b0;
1007
      `endif
1008 38 mohor
    end
1009 39 mohor
  else
1010
    begin
1011
      // Switching between two stages depends on enable signals
1012 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1013 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1014 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1015 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1016 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1017 39 mohor
          begin
1018 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1019
            MasterWbRX <=#Tp 1'b0;
1020
            m_wb_cyc_o <=#Tp 1'b1;
1021
            m_wb_stb_o <=#Tp 1'b1;
1022
            m_wb_we_o  <=#Tp 1'b0;
1023
            m_wb_sel_o <=#Tp 4'hf;
1024
            cyc_cleared<=#Tp 1'b0;
1025
            IncrTxPointer<=#Tp 1'b1;
1026
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1027
            if(tx_burst_cnt==0)
1028
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1029
            else
1030
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1031
 
1032
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1033
              begin
1034
                tx_burst_en<=#Tp 1'b0;
1035
              `ifdef ETH_WISHBONE_B3
1036
                m_wb_cti_o <=#Tp 3'b111;
1037
              `endif
1038
              end
1039
            else
1040
              begin
1041
              `ifdef ETH_WISHBONE_B3
1042
                m_wb_cti_o <=#Tp 3'b010;
1043
              `endif
1044
              end
1045
          end
1046 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1047
        8'b01_x1_10_x1,             // MWB continues
1048 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1049 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1050 226 tadejm
          begin
1051
            MasterWbTX <=#Tp 1'b0;  // rx burst
1052 39 mohor
            MasterWbRX <=#Tp 1'b1;
1053 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1054
            m_wb_stb_o <=#Tp 1'b1;
1055
            m_wb_we_o  <=#Tp 1'b1;
1056
            m_wb_sel_o <=#Tp RxByteSel;
1057
            IncrTxPointer<=#Tp 1'b0;
1058
            cyc_cleared<=#Tp 1'b0;
1059
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1060
 
1061
            if(rx_burst_cnt==0)
1062
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1063
            else
1064
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1065
 
1066
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1067
              begin
1068
                rx_burst_en<=#Tp 1'b0;
1069
              `ifdef ETH_WISHBONE_B3
1070
                m_wb_cti_o <=#Tp 3'b111;
1071
              `endif
1072
              end
1073
            else
1074
              begin
1075
              `ifdef ETH_WISHBONE_B3
1076
                m_wb_cti_o <=#Tp 3'b010;
1077
              `endif
1078
              end
1079
          end
1080 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1081 226 tadejm
          begin
1082
            MasterWbTX <=#Tp 1'b0;
1083
            MasterWbRX <=#Tp 1'b1;
1084 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1085 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1086
            m_wb_stb_o <=#Tp 1'b1;
1087
            m_wb_we_o  <=#Tp 1'b1;
1088 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1089 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1090 39 mohor
          end
1091 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1092 39 mohor
          begin
1093 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1094 39 mohor
            MasterWbRX <=#Tp 1'b0;
1095 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1096 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1097
            m_wb_stb_o <=#Tp 1'b1;
1098
            m_wb_we_o  <=#Tp 1'b0;
1099 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1100
            IncrTxPointer<=#Tp 1'b1;
1101 39 mohor
          end
1102 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1103 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1104 39 mohor
          begin
1105 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1106 39 mohor
            MasterWbRX <=#Tp 1'b0;
1107 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1108 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1109
            m_wb_stb_o <=#Tp 1'b1;
1110
            m_wb_we_o  <=#Tp 1'b0;
1111 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1112 110 mohor
            cyc_cleared<=#Tp 1'b0;
1113 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1114 39 mohor
          end
1115 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1116 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1117 39 mohor
          begin
1118 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1119 39 mohor
            MasterWbRX <=#Tp 1'b1;
1120 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1121 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1122
            m_wb_stb_o <=#Tp 1'b1;
1123 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1124 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1125 110 mohor
            cyc_cleared<=#Tp 1'b0;
1126 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1127 39 mohor
          end
1128 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1129 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1130 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1131 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1132 39 mohor
          begin
1133 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1134
            m_wb_stb_o <=#Tp 1'b0;
1135
            cyc_cleared<=#Tp 1'b1;
1136 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1137 226 tadejm
            tx_burst_cnt<=#Tp 0;
1138
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1139
            rx_burst_cnt<=#Tp 0;
1140
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1141
            `ifdef ETH_WISHBONE_B3
1142
              m_wb_cti_o <=#Tp 3'b0;
1143
            `endif
1144 110 mohor
          end
1145 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1146
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1147 110 mohor
          begin
1148 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1149 39 mohor
            MasterWbRX <=#Tp 1'b0;
1150
            m_wb_cyc_o <=#Tp 1'b0;
1151
            m_wb_stb_o <=#Tp 1'b0;
1152 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1153 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1154 226 tadejm
            rx_burst_cnt<=#Tp 0;
1155
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1156
            `ifdef ETH_WISHBONE_B3
1157
              m_wb_cti_o <=#Tp 3'b0;
1158
            `endif
1159 39 mohor
          end
1160 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1161 127 mohor
          begin
1162 226 tadejm
            tx_burst_cnt<=#Tp 0;
1163
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1164 127 mohor
          end
1165 226 tadejm
        default:                    // Don't touch
1166 82 mohor
          begin
1167
            MasterWbTX <=#Tp MasterWbTX;
1168
            MasterWbRX <=#Tp MasterWbRX;
1169
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1170
            m_wb_stb_o <=#Tp m_wb_stb_o;
1171 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1172 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1173 82 mohor
          end
1174 39 mohor
      endcase
1175
    end
1176 38 mohor
end
1177
 
1178 110 mohor
 
1179 39 mohor
wire TxFifoClear;
1180 96 mohor
 
1181 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1182 38 mohor
 
1183 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1184 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1185 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1186 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1187 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1188
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1189 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1190 96 mohor
        );
1191 39 mohor
 
1192
 
1193
reg StartOccured;
1194
reg TxStartFrm_sync1;
1195
reg TxStartFrm_sync2;
1196
reg TxStartFrm_syncb1;
1197
reg TxStartFrm_syncb2;
1198
 
1199
 
1200
 
1201
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1202 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1203 38 mohor
begin
1204 40 mohor
  if(Reset)
1205 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1206 38 mohor
  else
1207 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1208
    TxStartFrm_wb <=#Tp 1'b1;
1209 38 mohor
  else
1210 39 mohor
  if(TxStartFrm_syncb2)
1211
    TxStartFrm_wb <=#Tp 1'b0;
1212 38 mohor
end
1213
 
1214 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1215 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1216 38 mohor
begin
1217 40 mohor
  if(Reset)
1218 39 mohor
    StartOccured <=#Tp 1'b0;
1219 38 mohor
  else
1220 39 mohor
  if(TxStartFrm_wb)
1221
    StartOccured <=#Tp 1'b1;
1222 38 mohor
  else
1223 39 mohor
  if(ResetTxBDReady)
1224
    StartOccured <=#Tp 1'b0;
1225 38 mohor
end
1226
 
1227 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1228 40 mohor
always @ (posedge MTxClk or posedge Reset)
1229 39 mohor
begin
1230 40 mohor
  if(Reset)
1231 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1232
  else
1233
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1234
end
1235 38 mohor
 
1236 40 mohor
always @ (posedge MTxClk or posedge Reset)
1237 39 mohor
begin
1238 40 mohor
  if(Reset)
1239 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1240
  else
1241
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1242
end
1243
 
1244 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1245 38 mohor
begin
1246 40 mohor
  if(Reset)
1247 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1248 38 mohor
  else
1249 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1250 38 mohor
end
1251
 
1252 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1253 38 mohor
begin
1254 40 mohor
  if(Reset)
1255 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1256 38 mohor
  else
1257 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1258
end
1259
 
1260 40 mohor
always @ (posedge MTxClk or posedge Reset)
1261 39 mohor
begin
1262 40 mohor
  if(Reset)
1263 39 mohor
    TxStartFrm <=#Tp 1'b0;
1264 38 mohor
  else
1265 39 mohor
  if(TxStartFrm_sync2)
1266 61 mohor
    TxStartFrm <=#Tp 1'b1;
1267 39 mohor
  else
1268 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1269 39 mohor
    TxStartFrm <=#Tp 1'b0;
1270 38 mohor
end
1271 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1272 38 mohor
 
1273
 
1274 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1275 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1276 38 mohor
begin
1277 40 mohor
  if(Reset)
1278 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1279 38 mohor
  else
1280 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1281 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1282 38 mohor
  else
1283 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1284
    TxEndFrm_wb <=#Tp 1'b0;
1285 38 mohor
end
1286
 
1287
 
1288
// Marks which bytes are valid within the word.
1289 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1290 38 mohor
 
1291 39 mohor
reg LatchValidBytes;
1292
reg LatchValidBytes_q;
1293 38 mohor
 
1294 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1295 38 mohor
begin
1296 40 mohor
  if(Reset)
1297 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1298 38 mohor
  else
1299 39 mohor
  if(TxLengthLt4 & TxBDReady)
1300
    LatchValidBytes <=#Tp 1'b1;
1301 38 mohor
  else
1302 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1303 38 mohor
end
1304
 
1305 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1306 38 mohor
begin
1307 40 mohor
  if(Reset)
1308 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1309 38 mohor
  else
1310 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1311 38 mohor
end
1312
 
1313
 
1314 39 mohor
// Latching valid bytes
1315 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1316 38 mohor
begin
1317 40 mohor
  if(Reset)
1318 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1319 38 mohor
  else
1320 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1321
    TxValidBytesLatched <=#Tp TxValidBytes;
1322
  else
1323
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1324
    TxValidBytesLatched <=#Tp 2'h0;
1325 38 mohor
end
1326
 
1327
 
1328
assign TxIRQEn          = TxStatus[14];
1329 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1330
assign PerPacketPad     = TxStatus[12];
1331
assign PerPacketCrcEn   = TxStatus[11];
1332 38 mohor
 
1333
 
1334 77 mohor
assign RxIRQEn         = RxStatus[14];
1335 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1336 38 mohor
 
1337
 
1338
// Temporary Tx and Rx buffer descriptor address 
1339 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1340 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1341 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1342 38 mohor
 
1343
 
1344
// Latching Tx buffer descriptor address
1345 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1346 38 mohor
begin
1347 40 mohor
  if(Reset)
1348 38 mohor
    TxBDAddress <=#Tp 8'h0;
1349
  else
1350
  if(TxStatusWrite)
1351
    TxBDAddress <=#Tp TempTxBDAddress;
1352
end
1353
 
1354
 
1355
// Latching Rx buffer descriptor address
1356 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1357 38 mohor
begin
1358 40 mohor
  if(Reset)
1359 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1360 38 mohor
  else
1361 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1362 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1363 38 mohor
  else
1364
  if(RxStatusWrite)
1365
    RxBDAddress <=#Tp TempRxBDAddress;
1366
end
1367
 
1368 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1369 38 mohor
 
1370 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1371 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1372 38 mohor
 
1373 60 mohor
 
1374 38 mohor
// Signals used for various purposes
1375 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1376 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1377
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1378
 
1379
 
1380
 
1381 39 mohor
// Generating delayed signals
1382 40 mohor
always @ (posedge MTxClk or posedge Reset)
1383 38 mohor
begin
1384 40 mohor
  if(Reset)
1385 39 mohor
    begin
1386
      TxAbort_q      <=#Tp 1'b0;
1387
      TxRetry_q      <=#Tp 1'b0;
1388
      TxUsedData_q   <=#Tp 1'b0;
1389
    end
1390 38 mohor
  else
1391 39 mohor
    begin
1392
      TxAbort_q      <=#Tp TxAbort;
1393
      TxRetry_q      <=#Tp TxRetry;
1394
      TxUsedData_q   <=#Tp TxUsedData;
1395
    end
1396 38 mohor
end
1397
 
1398
// Generating delayed signals
1399 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1400 38 mohor
begin
1401 40 mohor
  if(Reset)
1402 38 mohor
    begin
1403 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1404
      TxAbort_wb_q  <=#Tp 1'b0;
1405 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1406 38 mohor
    end
1407
  else
1408
    begin
1409 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1410
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1411 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1412 38 mohor
    end
1413
end
1414
 
1415
 
1416 219 mohor
reg TxAbortPacketBlocked;
1417
always @ (posedge WB_CLK_I or posedge Reset)
1418
begin
1419
  if(Reset)
1420
    TxAbortPacket <=#Tp 1'b0;
1421
  else
1422 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1423
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1424 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1425
  else
1426
    TxAbortPacket <=#Tp 1'b0;
1427
end
1428
 
1429
 
1430
always @ (posedge WB_CLK_I or posedge Reset)
1431
begin
1432
  if(Reset)
1433 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1434
  else
1435 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1436
     TxAbort_wb & !MasterWbTX)
1437 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1438
  else
1439
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1440
end
1441
 
1442
 
1443
always @ (posedge WB_CLK_I or posedge Reset)
1444
begin
1445
  if(Reset)
1446 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1447
  else
1448
  if(TxAbortPacket)
1449
    TxAbortPacketBlocked <=#Tp 1'b1;
1450
  else
1451
  if(!TxAbort_wb & TxAbort_wb_q)
1452
    TxAbortPacketBlocked <=#Tp 1'b0;
1453
end
1454
 
1455
 
1456
reg TxRetryPacketBlocked;
1457
always @ (posedge WB_CLK_I or posedge Reset)
1458
begin
1459
  if(Reset)
1460
    TxRetryPacket <=#Tp 1'b0;
1461
  else
1462 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1463
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1464 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1465
  else
1466
    TxRetryPacket <=#Tp 1'b0;
1467
end
1468
 
1469
 
1470
always @ (posedge WB_CLK_I or posedge Reset)
1471
begin
1472
  if(Reset)
1473 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1474
  else
1475 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1476
     TxRetry_wb & !MasterWbTX)
1477 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1478
  else
1479
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1480
end
1481
 
1482
 
1483
always @ (posedge WB_CLK_I or posedge Reset)
1484
begin
1485
  if(Reset)
1486 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1487
  else
1488
  if(TxRetryPacket)
1489
    TxRetryPacketBlocked <=#Tp 1'b1;
1490
  else
1491
  if(!TxRetry_wb & TxRetry_wb_q)
1492
    TxRetryPacketBlocked <=#Tp 1'b0;
1493
end
1494
 
1495
 
1496 221 mohor
reg TxDonePacketBlocked;
1497
always @ (posedge WB_CLK_I or posedge Reset)
1498
begin
1499
  if(Reset)
1500
    TxDonePacket <=#Tp 1'b0;
1501
  else
1502 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1503
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1504 221 mohor
    TxDonePacket <=#Tp 1'b1;
1505
  else
1506
    TxDonePacket <=#Tp 1'b0;
1507
end
1508
 
1509
 
1510
always @ (posedge WB_CLK_I or posedge Reset)
1511
begin
1512
  if(Reset)
1513
    TxDonePacket_NotCleared <=#Tp 1'b0;
1514
  else
1515 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1516
     TxDone_wb & !MasterWbTX)
1517 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1518
  else
1519
    TxDonePacket_NotCleared <=#Tp 1'b0;
1520
end
1521
 
1522
 
1523
always @ (posedge WB_CLK_I or posedge Reset)
1524
begin
1525
  if(Reset)
1526
    TxDonePacketBlocked <=#Tp 1'b0;
1527
  else
1528
  if(TxDonePacket)
1529
    TxDonePacketBlocked <=#Tp 1'b1;
1530
  else
1531
  if(!TxDone_wb & TxDone_wb_q)
1532
    TxDonePacketBlocked <=#Tp 1'b0;
1533
end
1534
 
1535
 
1536 38 mohor
// Sinchronizing and evaluating tx data
1537 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1538 219 mohor
assign SetGotData = (TxStartFrm_wb);
1539 38 mohor
 
1540
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1541 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1542
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1543 38 mohor
 
1544
 
1545
// Indication of the last word
1546 40 mohor
always @ (posedge MTxClk or posedge Reset)
1547 38 mohor
begin
1548 40 mohor
  if(Reset)
1549 38 mohor
    LastWord <=#Tp 1'b0;
1550
  else
1551
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1552
    LastWord <=#Tp 1'b0;
1553
  else
1554
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1555 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1556 38 mohor
end
1557
 
1558
 
1559
// Tx end frame generation
1560 40 mohor
always @ (posedge MTxClk or posedge Reset)
1561 38 mohor
begin
1562 40 mohor
  if(Reset)
1563 38 mohor
    TxEndFrm <=#Tp 1'b0;
1564
  else
1565 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1566 38 mohor
    TxEndFrm <=#Tp 1'b0;
1567
  else
1568
  if(Flop & LastWord)
1569
    begin
1570 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1571 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1572
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1573
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1574
 
1575
        default : TxEndFrm <=#Tp 1'b0;
1576
      endcase
1577
    end
1578
end
1579
 
1580
 
1581
// Tx data selection (latching)
1582 40 mohor
always @ (posedge MTxClk or posedge Reset)
1583 38 mohor
begin
1584 40 mohor
  if(Reset)
1585 96 mohor
    TxData <=#Tp 0;
1586 38 mohor
  else
1587 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1588 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1589 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1590
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1591
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1592
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1593
    endcase
1594 38 mohor
  else
1595 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1596 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1597
  else
1598 38 mohor
  if(TxUsedData & Flop)
1599
    begin
1600 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1601 226 tadejm
 
1602 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1603
        2 : TxData <=#Tp TxDataLatched[15:8];
1604
        3 : TxData <=#Tp TxDataLatched[7:0];
1605 38 mohor
      endcase
1606
    end
1607
end
1608
 
1609
 
1610
// Latching tx data
1611 40 mohor
always @ (posedge MTxClk or posedge Reset)
1612 38 mohor
begin
1613 40 mohor
  if(Reset)
1614 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1615
  else
1616 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1617 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1618 38 mohor
end
1619
 
1620
 
1621
// Tx under run
1622 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1623 38 mohor
begin
1624 40 mohor
  if(Reset)
1625 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1626 38 mohor
  else
1627 39 mohor
  if(TxAbortPulse)
1628 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1629
  else
1630
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1631
    TxUnderRun_wb <=#Tp 1'b1;
1632
end
1633
 
1634
 
1635 159 mohor
reg TxUnderRun_sync1;
1636
 
1637 60 mohor
// Tx under run
1638
always @ (posedge MTxClk or posedge Reset)
1639
begin
1640
  if(Reset)
1641 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1642 43 mohor
  else
1643 60 mohor
  if(TxUnderRun_wb)
1644 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1645 60 mohor
  else
1646 159 mohor
  if(BlockingTxStatusWrite_sync2)
1647
    TxUnderRun_sync1 <=#Tp 1'b0;
1648
end
1649
 
1650
// Tx under run
1651
always @ (posedge MTxClk or posedge Reset)
1652
begin
1653
  if(Reset)
1654 60 mohor
    TxUnderRun <=#Tp 1'b0;
1655 159 mohor
  else
1656
  if(BlockingTxStatusWrite_sync2)
1657
    TxUnderRun <=#Tp 1'b0;
1658
  else
1659
  if(TxUnderRun_sync1)
1660
    TxUnderRun <=#Tp 1'b1;
1661 38 mohor
end
1662
 
1663
 
1664
// Tx Byte counter
1665 40 mohor
always @ (posedge MTxClk or posedge Reset)
1666 38 mohor
begin
1667 40 mohor
  if(Reset)
1668 38 mohor
    TxByteCnt <=#Tp 2'h0;
1669
  else
1670
  if(TxAbort_q | TxRetry_q)
1671
    TxByteCnt <=#Tp 2'h0;
1672
  else
1673
  if(TxStartFrm & ~TxUsedData)
1674 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1675 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1676
      2'h1 : TxByteCnt <=#Tp 2'h2;
1677
      2'h2 : TxByteCnt <=#Tp 2'h3;
1678
      2'h3 : TxByteCnt <=#Tp 2'h0;
1679
    endcase
1680 38 mohor
  else
1681
  if(TxUsedData & Flop)
1682 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1683 38 mohor
end
1684
 
1685 39 mohor
 
1686 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1687
reg ReadTxDataFromFifo_sync1;
1688
reg ReadTxDataFromFifo_sync2;
1689
reg ReadTxDataFromFifo_sync3;
1690
reg ReadTxDataFromFifo_syncb1;
1691
reg ReadTxDataFromFifo_syncb2;
1692
reg ReadTxDataFromFifo_syncb3;
1693
 
1694
 
1695
always @ (posedge MTxClk or posedge Reset)
1696
begin
1697
  if(Reset)
1698
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1699
  else
1700 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1701 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1702 150 mohor
  else
1703
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1704
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1705 38 mohor
end
1706
 
1707 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1708 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1709 38 mohor
begin
1710 40 mohor
  if(Reset)
1711 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1712 38 mohor
  else
1713 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1714
end
1715 38 mohor
 
1716 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1717 38 mohor
begin
1718 40 mohor
  if(Reset)
1719 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1720 38 mohor
  else
1721 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1722 38 mohor
end
1723
 
1724 40 mohor
always @ (posedge MTxClk or posedge Reset)
1725 38 mohor
begin
1726 40 mohor
  if(Reset)
1727 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1728 38 mohor
  else
1729 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1730 38 mohor
end
1731
 
1732 40 mohor
always @ (posedge MTxClk or posedge Reset)
1733 38 mohor
begin
1734 40 mohor
  if(Reset)
1735 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1736 38 mohor
  else
1737 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1738 38 mohor
end
1739
 
1740 150 mohor
always @ (posedge MTxClk or posedge Reset)
1741
begin
1742
  if(Reset)
1743
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1744
  else
1745
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1746
end
1747
 
1748 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1749 38 mohor
begin
1750 40 mohor
  if(Reset)
1751 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1752 38 mohor
  else
1753 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1754 38 mohor
end
1755
 
1756 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1757
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1758 38 mohor
 
1759
 
1760 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1761 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1762 38 mohor
begin
1763 40 mohor
  if(Reset)
1764 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1765 38 mohor
  else
1766 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1767 38 mohor
end
1768
 
1769 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1770 38 mohor
begin
1771 40 mohor
  if(Reset)
1772 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1773 38 mohor
  else
1774 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1775 38 mohor
end
1776
 
1777
 
1778 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1779 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1780 38 mohor
begin
1781 40 mohor
  if(Reset)
1782 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1783 38 mohor
  else
1784 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1785 38 mohor
end
1786
 
1787 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1788 38 mohor
begin
1789 40 mohor
  if(Reset)
1790 39 mohor
    TxDone_wb <=#Tp 1'b0;
1791 38 mohor
  else
1792 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1793 38 mohor
end
1794
 
1795 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1796 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1797 38 mohor
begin
1798 40 mohor
  if(Reset)
1799 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1800 38 mohor
  else
1801 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1802 38 mohor
end
1803
 
1804 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1805 38 mohor
begin
1806 40 mohor
  if(Reset)
1807 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1808
  else
1809 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1810 38 mohor
end
1811
 
1812
 
1813 150 mohor
reg RxAbortSync1;
1814
reg RxAbortSync2;
1815
reg RxAbortSync3;
1816
reg RxAbortSync4;
1817
reg RxAbortSyncb1;
1818
reg RxAbortSyncb2;
1819 39 mohor
 
1820 150 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1821
 
1822 40 mohor
// Reading the Rx buffer descriptor
1823
always @ (posedge WB_CLK_I or posedge Reset)
1824
begin
1825
  if(Reset)
1826
    RxBDRead <=#Tp 1'b1;
1827
  else
1828 166 mohor
  if(StartRxBDRead & ~RxReady)
1829 40 mohor
    RxBDRead <=#Tp 1'b1;
1830
  else
1831
  if(RxBDReady)
1832
    RxBDRead <=#Tp 1'b0;
1833
end
1834 39 mohor
 
1835
 
1836 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1837
// written to the previous one.
1838
 
1839
// Latching READY status of the Rx buffer descriptor
1840 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1841 38 mohor
begin
1842 40 mohor
  if(Reset)
1843 38 mohor
    RxBDReady <=#Tp 1'b0;
1844
  else
1845 166 mohor
  if(RxPointerRead)
1846 150 mohor
    RxBDReady <=#Tp 1'b0;
1847
  else
1848 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1849
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1850 38 mohor
end
1851
 
1852 40 mohor
// Latching Rx buffer descriptor status
1853
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1854
always @ (posedge WB_CLK_I or posedge Reset)
1855 38 mohor
begin
1856 40 mohor
  if(Reset)
1857 60 mohor
    RxStatus <=#Tp 2'h0;
1858 38 mohor
  else
1859 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1860 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1861 38 mohor
end
1862
 
1863
 
1864 166 mohor
// RxReady generation
1865
always @ (posedge WB_CLK_I or posedge Reset)
1866
begin
1867
  if(Reset)
1868
    RxReady <=#Tp 1'b0;
1869
  else
1870
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1871
    RxReady <=#Tp 1'b0;
1872
  else
1873
  if(RxEn & RxEn_q & RxPointerRead)
1874
    RxReady <=#Tp 1'b1;
1875
end
1876 38 mohor
 
1877
 
1878 40 mohor
// Reading Rx BD pointer
1879
 
1880
 
1881
assign StartRxPointerRead = RxBDRead & RxBDReady;
1882
 
1883
// Reading Tx BD Pointer
1884
always @ (posedge WB_CLK_I or posedge Reset)
1885 38 mohor
begin
1886 40 mohor
  if(Reset)
1887
    RxPointerRead <=#Tp 1'b0;
1888 38 mohor
  else
1889 40 mohor
  if(StartRxPointerRead)
1890
    RxPointerRead <=#Tp 1'b1;
1891 38 mohor
  else
1892 166 mohor
  if(RxEn & RxEn_q)
1893 40 mohor
    RxPointerRead <=#Tp 1'b0;
1894 38 mohor
end
1895
 
1896 113 mohor
 
1897 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1898
always @ (posedge WB_CLK_I or posedge Reset)
1899
begin
1900
  if(Reset)
1901 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1902 40 mohor
  else
1903
  if(RxEn & RxEn_q & RxPointerRead)
1904 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1905 40 mohor
  else
1906 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1907 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1908 40 mohor
end
1909 38 mohor
 
1910
 
1911 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1912 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1913
begin
1914
  if(Reset)
1915 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1916 96 mohor
  else
1917 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1918
    RxPointerLSB_rst[1:0] <=#Tp 0;
1919 96 mohor
  else
1920
  if(RxEn & RxEn_q & RxPointerRead)
1921 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1922 96 mohor
end
1923
 
1924
 
1925 159 mohor
always @ (RxPointerLSB_rst)
1926 96 mohor
begin
1927 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1928
    2'h0 : RxByteSel[3:0] = 4'hf;
1929
    2'h1 : RxByteSel[3:0] = 4'h7;
1930
    2'h2 : RxByteSel[3:0] = 4'h3;
1931
    2'h3 : RxByteSel[3:0] = 4'h1;
1932 96 mohor
  endcase
1933
end
1934
 
1935
 
1936
always @ (posedge WB_CLK_I or posedge Reset)
1937
begin
1938
  if(Reset)
1939 40 mohor
    RxEn_needed <=#Tp 1'b0;
1940 38 mohor
  else
1941 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1942 40 mohor
    RxEn_needed <=#Tp 1'b1;
1943 38 mohor
  else
1944 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1945
    RxEn_needed <=#Tp 1'b0;
1946 38 mohor
end
1947
 
1948
 
1949 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1950
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1951 38 mohor
 
1952 40 mohor
reg RxEnableWindow;
1953 38 mohor
 
1954
// Indicating that last byte is being reveived
1955 40 mohor
always @ (posedge MRxClk or posedge Reset)
1956 38 mohor
begin
1957 40 mohor
  if(Reset)
1958 38 mohor
    LastByteIn <=#Tp 1'b0;
1959
  else
1960 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1961 38 mohor
    LastByteIn <=#Tp 1'b0;
1962
  else
1963 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1964 38 mohor
    LastByteIn <=#Tp 1'b1;
1965
end
1966
 
1967 159 mohor
reg ShiftEnded_rck;
1968 40 mohor
reg ShiftEndedSync1;
1969
reg ShiftEndedSync2;
1970 118 mohor
reg ShiftEndedSync3;
1971
reg ShiftEndedSync_c1;
1972
reg ShiftEndedSync_c2;
1973
 
1974 40 mohor
wire StartShiftWillEnd;
1975 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1976 38 mohor
 
1977
// Indicating that data reception will end
1978 40 mohor
always @ (posedge MRxClk or posedge Reset)
1979 38 mohor
begin
1980 40 mohor
  if(Reset)
1981 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1982
  else
1983 159 mohor
  if(ShiftEnded_rck | RxAbort)
1984 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1985
  else
1986 40 mohor
  if(StartShiftWillEnd)
1987 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1988
end
1989
 
1990
 
1991 40 mohor
 
1992 38 mohor
// Receive byte counter
1993 40 mohor
always @ (posedge MRxClk or posedge Reset)
1994 38 mohor
begin
1995 40 mohor
  if(Reset)
1996 38 mohor
    RxByteCnt <=#Tp 2'h0;
1997
  else
1998 159 mohor
  if(ShiftEnded_rck | RxAbort)
1999 38 mohor
    RxByteCnt <=#Tp 2'h0;
2000 97 lampret
  else
2001 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2002 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2003 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2004
      2'h1 : RxByteCnt <=#Tp 2'h2;
2005
      2'h2 : RxByteCnt <=#Tp 2'h3;
2006
      2'h3 : RxByteCnt <=#Tp 2'h0;
2007
    endcase
2008 38 mohor
  else
2009 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2010 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2011 38 mohor
end
2012
 
2013
 
2014
// Indicates how many bytes are valid within the last word
2015 40 mohor
always @ (posedge MRxClk or posedge Reset)
2016 38 mohor
begin
2017 40 mohor
  if(Reset)
2018 38 mohor
    RxValidBytes <=#Tp 2'h1;
2019
  else
2020 96 mohor
  if(RxValid & RxStartFrm)
2021 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2022 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2023
      2'h1 : RxValidBytes <=#Tp 2'h2;
2024
      2'h2 : RxValidBytes <=#Tp 2'h3;
2025
      2'h3 : RxValidBytes <=#Tp 2'h0;
2026
    endcase
2027 38 mohor
  else
2028 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2029 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2030
end
2031
 
2032
 
2033 40 mohor
always @ (posedge MRxClk or posedge Reset)
2034 38 mohor
begin
2035 40 mohor
  if(Reset)
2036
    RxDataLatched1       <=#Tp 24'h0;
2037 38 mohor
  else
2038 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2039 96 mohor
    if(RxStartFrm)
2040 40 mohor
    begin
2041 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2042 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2043
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2044
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2045
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2046
      endcase
2047
    end
2048
    else if (RxEnableWindow)
2049
    begin
2050 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2051 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2052
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2053
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2054 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2055
      endcase
2056
    end
2057 38 mohor
end
2058
 
2059 40 mohor
wire SetWriteRxDataToFifo;
2060 38 mohor
 
2061 40 mohor
// Assembling data that will be written to the rx_fifo
2062
always @ (posedge MRxClk or posedge Reset)
2063 38 mohor
begin
2064 40 mohor
  if(Reset)
2065
    RxDataLatched2 <=#Tp 32'h0;
2066 38 mohor
  else
2067 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2068 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2069 38 mohor
  else
2070 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2071 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2072 82 mohor
 
2073
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2074
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2075
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2076 40 mohor
    endcase
2077 38 mohor
end
2078
 
2079
 
2080 40 mohor
reg WriteRxDataToFifoSync1;
2081
reg WriteRxDataToFifoSync2;
2082 150 mohor
reg WriteRxDataToFifoSync3;
2083 38 mohor
 
2084
 
2085 40 mohor
// Indicating start of the reception process
2086 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2087
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2088
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2089 38 mohor
 
2090 150 mohor
always @ (posedge MRxClk or posedge Reset)
2091
begin
2092
  if(Reset)
2093
    WriteRxDataToFifo <=#Tp 1'b0;
2094
  else
2095
  if(SetWriteRxDataToFifo & ~RxAbort)
2096
    WriteRxDataToFifo <=#Tp 1'b1;
2097
  else
2098
  if(WriteRxDataToFifoSync2 | RxAbort)
2099
    WriteRxDataToFifo <=#Tp 1'b0;
2100
end
2101 40 mohor
 
2102 150 mohor
 
2103
 
2104
always @ (posedge WB_CLK_I or posedge Reset)
2105
begin
2106
  if(Reset)
2107
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2108
  else
2109
  if(WriteRxDataToFifo)
2110
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2111
  else
2112
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2113
end
2114
 
2115
always @ (posedge WB_CLK_I or posedge Reset)
2116
begin
2117
  if(Reset)
2118
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2119
  else
2120
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2121
end
2122
 
2123
always @ (posedge WB_CLK_I or posedge Reset)
2124
begin
2125
  if(Reset)
2126
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2127
  else
2128
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2129
end
2130
 
2131
wire WriteRxDataToFifo_wb;
2132
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2133
 
2134
 
2135 90 mohor
reg LatchedRxStartFrm;
2136
reg SyncRxStartFrm;
2137
reg SyncRxStartFrm_q;
2138 150 mohor
reg SyncRxStartFrm_q2;
2139 90 mohor
wire RxFifoReset;
2140 40 mohor
 
2141 90 mohor
always @ (posedge MRxClk or posedge Reset)
2142
begin
2143
  if(Reset)
2144
    LatchedRxStartFrm <=#Tp 0;
2145
  else
2146 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2147 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2148
  else
2149 150 mohor
  if(SyncRxStartFrm_q)
2150 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2151
end
2152
 
2153
 
2154
always @ (posedge WB_CLK_I or posedge Reset)
2155
begin
2156
  if(Reset)
2157
    SyncRxStartFrm <=#Tp 0;
2158
  else
2159
  if(LatchedRxStartFrm)
2160
    SyncRxStartFrm <=#Tp 1;
2161
  else
2162
    SyncRxStartFrm <=#Tp 0;
2163
end
2164
 
2165
 
2166
always @ (posedge WB_CLK_I or posedge Reset)
2167
begin
2168
  if(Reset)
2169
    SyncRxStartFrm_q <=#Tp 0;
2170
  else
2171
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2172
end
2173
 
2174 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2175
begin
2176
  if(Reset)
2177
    SyncRxStartFrm_q2 <=#Tp 0;
2178
  else
2179
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2180
end
2181 90 mohor
 
2182
 
2183 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2184 90 mohor
 
2185 150 mohor
 
2186 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2187 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2188
         .clk(WB_CLK_I),                                .reset(Reset),
2189 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2190 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2191 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2192 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2193 88 mohor
        );
2194 40 mohor
 
2195 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2196
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2197 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2198 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2199 40 mohor
 
2200
 
2201
// Generation of the end-of-frame signal
2202
always @ (posedge MRxClk or posedge Reset)
2203 38 mohor
begin
2204 40 mohor
  if(Reset)
2205 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2206 38 mohor
  else
2207 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2208 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2209 38 mohor
  else
2210 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2211 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2212 38 mohor
end
2213
 
2214 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2215
begin
2216
  if(Reset)
2217
    ShiftEndedSync1 <=#Tp 1'b0;
2218
  else
2219 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2220 40 mohor
end
2221 38 mohor
 
2222 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2223 38 mohor
begin
2224 40 mohor
  if(Reset)
2225
    ShiftEndedSync2 <=#Tp 1'b0;
2226 38 mohor
  else
2227 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2228 40 mohor
end
2229 38 mohor
 
2230 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2231
begin
2232
  if(Reset)
2233
    ShiftEndedSync3 <=#Tp 1'b0;
2234
  else
2235
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2236
    ShiftEndedSync3 <=#Tp 1'b1;
2237
  else
2238
  if(ShiftEnded)
2239
    ShiftEndedSync3 <=#Tp 1'b0;
2240
end
2241 38 mohor
 
2242 40 mohor
// Generation of the end-of-frame signal
2243
always @ (posedge WB_CLK_I or posedge Reset)
2244 38 mohor
begin
2245 40 mohor
  if(Reset)
2246
    ShiftEnded <=#Tp 1'b0;
2247 38 mohor
  else
2248 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2249 40 mohor
    ShiftEnded <=#Tp 1'b1;
2250 38 mohor
  else
2251 40 mohor
  if(RxStatusWrite)
2252
    ShiftEnded <=#Tp 1'b0;
2253 38 mohor
end
2254
 
2255 118 mohor
always @ (posedge MRxClk or posedge Reset)
2256
begin
2257
  if(Reset)
2258
    ShiftEndedSync_c1 <=#Tp 1'b0;
2259
  else
2260
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2261
end
2262 38 mohor
 
2263 118 mohor
always @ (posedge MRxClk or posedge Reset)
2264
begin
2265
  if(Reset)
2266
    ShiftEndedSync_c2 <=#Tp 1'b0;
2267
  else
2268
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2269
end
2270
 
2271 40 mohor
// Generation of the end-of-frame signal
2272
always @ (posedge MRxClk or posedge Reset)
2273 38 mohor
begin
2274 40 mohor
  if(Reset)
2275
    RxEnableWindow <=#Tp 1'b0;
2276 38 mohor
  else
2277 40 mohor
  if(RxStartFrm)
2278
    RxEnableWindow <=#Tp 1'b1;
2279 38 mohor
  else
2280 40 mohor
  if(RxEndFrm | RxAbort)
2281
    RxEnableWindow <=#Tp 1'b0;
2282 38 mohor
end
2283
 
2284
 
2285 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2286 38 mohor
begin
2287 40 mohor
  if(Reset)
2288
    RxAbortSync1 <=#Tp 1'b0;
2289 38 mohor
  else
2290 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2291 40 mohor
end
2292
 
2293
always @ (posedge WB_CLK_I or posedge Reset)
2294
begin
2295
  if(Reset)
2296
    RxAbortSync2 <=#Tp 1'b0;
2297 38 mohor
  else
2298 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2299 38 mohor
end
2300
 
2301 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2302
begin
2303
  if(Reset)
2304
    RxAbortSync3 <=#Tp 1'b0;
2305
  else
2306
    RxAbortSync3 <=#Tp RxAbortSync2;
2307
end
2308
 
2309
always @ (posedge WB_CLK_I or posedge Reset)
2310
begin
2311
  if(Reset)
2312
    RxAbortSync4 <=#Tp 1'b0;
2313
  else
2314
    RxAbortSync4 <=#Tp RxAbortSync3;
2315
end
2316
 
2317 40 mohor
always @ (posedge MRxClk or posedge Reset)
2318
begin
2319
  if(Reset)
2320
    RxAbortSyncb1 <=#Tp 1'b0;
2321
  else
2322
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2323
end
2324 38 mohor
 
2325 40 mohor
always @ (posedge MRxClk or posedge Reset)
2326 38 mohor
begin
2327 40 mohor
  if(Reset)
2328
    RxAbortSyncb2 <=#Tp 1'b0;
2329 38 mohor
  else
2330 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2331 38 mohor
end
2332
 
2333
 
2334 64 mohor
always @ (posedge MRxClk or posedge Reset)
2335
begin
2336
  if(Reset)
2337
    RxAbortLatched <=#Tp 1'b0;
2338
  else
2339 150 mohor
  if(RxAbortSyncb2)
2340
    RxAbortLatched <=#Tp 1'b0;
2341
  else
2342 64 mohor
  if(RxAbort)
2343
    RxAbortLatched <=#Tp 1'b1;
2344
end
2345 40 mohor
 
2346 64 mohor
 
2347 42 mohor
always @ (posedge MRxClk or posedge Reset)
2348
begin
2349
  if(Reset)
2350
    LatchedRxLength[15:0] <=#Tp 16'h0;
2351
  else
2352 150 mohor
  if(LoadRxStatus)
2353 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2354
end
2355
 
2356
 
2357 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2358 42 mohor
 
2359
always @ (posedge MRxClk or posedge Reset)
2360
begin
2361
  if(Reset)
2362
    RxStatusInLatched <=#Tp 'h0;
2363
  else
2364 150 mohor
  if(LoadRxStatus)
2365 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2366
end
2367
 
2368
 
2369 60 mohor
// Rx overrun
2370
always @ (posedge WB_CLK_I or posedge Reset)
2371
begin
2372
  if(Reset)
2373
    RxOverrun <=#Tp 1'b0;
2374
  else
2375
  if(RxStatusWrite)
2376
    RxOverrun <=#Tp 1'b0;
2377
  else
2378
  if(RxBufferFull & WriteRxDataToFifo_wb)
2379
    RxOverrun <=#Tp 1'b1;
2380
end
2381 48 mohor
 
2382 77 mohor
 
2383
 
2384
wire TxError;
2385
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2386
 
2387
wire RxError;
2388
 
2389 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2390 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2391
// AddressMiss is identifying that a frame was received because of the promiscous
2392
// mode and is not an error
2393 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2394
 
2395 77 mohor
// Tx Done Interrupt
2396
always @ (posedge WB_CLK_I or posedge Reset)
2397
begin
2398
  if(Reset)
2399
    TxB_IRQ <=#Tp 1'b0;
2400
  else
2401
  if(TxStatusWrite & TxIRQEn)
2402
    TxB_IRQ <=#Tp ~TxError;
2403
  else
2404
    TxB_IRQ <=#Tp 1'b0;
2405
end
2406
 
2407
 
2408
// Tx Error Interrupt
2409
always @ (posedge WB_CLK_I or posedge Reset)
2410
begin
2411
  if(Reset)
2412
    TxE_IRQ <=#Tp 1'b0;
2413
  else
2414
  if(TxStatusWrite & TxIRQEn)
2415
    TxE_IRQ <=#Tp TxError;
2416
  else
2417
    TxE_IRQ <=#Tp 1'b0;
2418
end
2419
 
2420
 
2421
// Rx Done Interrupt
2422
always @ (posedge WB_CLK_I or posedge Reset)
2423
begin
2424
  if(Reset)
2425
    RxB_IRQ <=#Tp 1'b0;
2426
  else
2427 270 mohor
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2428
    RxB_IRQ <=#Tp (~RxError);
2429 77 mohor
  else
2430
    RxB_IRQ <=#Tp 1'b0;
2431
end
2432
 
2433
 
2434
// Rx Error Interrupt
2435
always @ (posedge WB_CLK_I or posedge Reset)
2436
begin
2437
  if(Reset)
2438
    RxE_IRQ <=#Tp 1'b0;
2439
  else
2440 270 mohor
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2441 77 mohor
    RxE_IRQ <=#Tp RxError;
2442
  else
2443
    RxE_IRQ <=#Tp 1'b0;
2444
end
2445
 
2446
 
2447 166 mohor
// Busy Interrupt
2448 77 mohor
 
2449 166 mohor
reg Busy_IRQ_rck;
2450
reg Busy_IRQ_sync1;
2451
reg Busy_IRQ_sync2;
2452
reg Busy_IRQ_sync3;
2453
reg Busy_IRQ_syncb1;
2454
reg Busy_IRQ_syncb2;
2455 77 mohor
 
2456
 
2457 166 mohor
always @ (posedge MRxClk or posedge Reset)
2458
begin
2459
  if(Reset)
2460
    Busy_IRQ_rck <=#Tp 1'b0;
2461
  else
2462
  if(RxValid & RxStartFrm & ~RxReady)
2463
    Busy_IRQ_rck <=#Tp 1'b1;
2464
  else
2465
  if(Busy_IRQ_syncb2)
2466
    Busy_IRQ_rck <=#Tp 1'b0;
2467
end
2468 77 mohor
 
2469 166 mohor
always @ (posedge WB_CLK_I)
2470
begin
2471
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2472
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2473
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2474
end
2475
 
2476
always @ (posedge MRxClk)
2477
begin
2478
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2479
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2480
end
2481
 
2482
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2483
 
2484
 
2485 60 mohor
 
2486
 
2487
 
2488 38 mohor
endmodule

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