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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_macstatus.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2002/04/22 13:51:44  mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8  2002/02/18 10:40:17  mohor
// Small fixes.
//
// Revision 1.7  2002/02/15 17:07:39  mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6  2002/02/11 09:18:21  mohor
// Tx status is written back to the BD.
//
// Revision 1.5  2002/02/08 16:21:54  mohor
// Rx status is written back to the BD.
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
`include "timescale.v"
 
 
module eth_macstatus(
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
                      RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,
                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr
                    );
 
 
 
parameter Tp = 1;
 
 
input         MRxClk;
input         Reset;
input         RxCrcError;
input         MRxErr;
input         MRxDV;
 
input         RxStateSFD;
input   [1:0] RxStateData;
input         RxStatePreamble;
input         RxStateIdle;
input         Transmitting;
input  [15:0] RxByteCnt;
input         RxByteCntEq0;
input         RxByteCntGreat2;
input         RxByteCntMaxFrame;
input         ReceivedPauseFrm;
input   [3:0] MRxD;
input         Collision;
input   [5:0] CollValid;
input         r_RecSmall;
input  [15:0] r_MinFL;
input  [15:0] r_MaxFL;
input         r_HugEn;
input         StartTxDone;
input         StartTxAbort;
input   [3:0] RetryCnt;
input         MTxClk;
input         MaxCollisionOccured;
input         LateCollision;
input         StartDefer;
input         TxStartFrm;
input         StatePreamble;
input   [1:0] StateData;
input         CarrierSense;
input         TxUsedData;
 
 
output        ReceivedLengthOK;
output        ReceiveEnd;
output        ReceivedPacketGood;
output        InvalidSymbol;
output        LatchedCrcError;
output        RxLateCollision;
output        ShortFrame;
output        DribbleNibble;
output        ReceivedPacketTooBig;
output        LoadRxStatus;
output  [3:0] RetryCntLatched;
output        RetryLimit;
output        LateCollLatched;
output        DeferLatched;
output        CarrierSenseLost;
output        LatchedMRxErr;
 
 
reg           ReceiveEnd;
 
reg           LatchedCrcError;
reg           LatchedMRxErr;
reg           LoadRxStatus;
reg           InvalidSymbol;
reg     [3:0] RetryCntLatched;
reg           RetryLimit;
reg           LateCollLatched;
reg           DeferLatched;
reg           CarrierSenseLost;
 
wire          TakeSample;
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
 
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateSFD)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateData[0])
    LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
 
 
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedMRxErr <=#Tp 1'b0;
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
    LatchedMRxErr <=#Tp 1'b1;
  else
    LatchedMRxErr <=#Tp 1'b0;
end
 
 
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
 
 
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
 
 
 
 
 
// Time to take a sample
assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
                     RxStateData[0]  &  MRxDV & RxByteCntMaxFrame;
 
 
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LoadRxStatus <=#Tp 1'b0;
  else
    LoadRxStatus <=#Tp TakeSample;
end
 
 
 
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceiveEnd  <=#Tp 1'b0;
  else
    ReceiveEnd  <=#Tp LoadRxStatus;
end
 
 
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
 
 
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(LoadRxStatus & ~SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b1;
end
 
 
// Late Collision
 
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxLateCollision <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    RxLateCollision <=#Tp 1'b0;
  else
  if(Collision & (~RxColWindow | r_RecSmall))
    RxLateCollision <=#Tp 1'b1;
end
 
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxColWindow <=#Tp 1'b1;
  else
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
    RxColWindow <=#Tp 1'b0;
  else
  if(RxStateIdle)
    RxColWindow <=#Tp 1'b1;
end
 
 
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShortFrame <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ShortFrame <=#Tp 1'b0;
  else
  if(TakeSample)
    ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
 
 
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    DribbleNibble <=#Tp 1'b0;
  else
  if(RxStateSFD)
    DribbleNibble <=#Tp 1'b0;
  else
  if(~MRxDV & RxStateData[1])
    DribbleNibble <=#Tp 1'b1;
end
 
 
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(TakeSample)
    ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
 
 
 
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryCntLatched <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryCntLatched <=#Tp RetryCnt;
end
 
 
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryLimit <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryLimit <=#Tp MaxCollisionOccured;
end
 
 
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    LateCollLatched <=#Tp 1'b0;
  else
  if(StartTxDone | StartTxAbort)
    LateCollLatched <=#Tp LateCollision;
end
 
 
 
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    DeferLatched <=#Tp 1'b0;
  else
  if(StartDefer & TxUsedData)
    DeferLatched <=#Tp 1'b1;
  else
  if(TxStartFrm)
    DeferLatched <=#Tp 1'b0;
end
 
 
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    CarrierSenseLost <=#Tp 1'b0;
  else
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Collision)
    CarrierSenseLost <=#Tp 1'b1;
  else
  if(TxStartFrm)
    CarrierSenseLost <=#Tp 1'b0;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_macstatus.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	126	mohor	`// Revision 1.9 2002/04/22 13:51:44 mohor`
45			`// Short frame and ReceivedLengthOK were not detected correctly.`
46			`//`
47	101	mohor	`// Revision 1.8 2002/02/18 10:40:17 mohor`
48			`// Small fixes.`
49			`//`
50	70	mohor	`// Revision 1.7 2002/02/15 17:07:39 mohor`
51			`// Status was not written correctly when frames were discarted because of`
52			`// address mismatch.`
53			`//`
54	64	mohor	`// Revision 1.6 2002/02/11 09:18:21 mohor`
55			`// Tx status is written back to the BD.`
56			`//`
57	43	mohor	`// Revision 1.5 2002/02/08 16:21:54 mohor`
58			`// Rx status is written back to the BD.`
59			`//`
60	42	mohor	`// Revision 1.4 2002/01/23 10:28:16 mohor`
61			`// Link in the header changed.`
62			`//`
63	37	mohor	`// Revision 1.3 2001/10/19 08:43:51 mohor`
64			`// eth_timescale.v changed to timescale.v This is done because of the`
65			`// simulation of the few cores in a one joined project.`
66			`//`
67	22	mohor	`// Revision 1.2 2001/09/11 14:17:00 mohor`
68			`// Few little NCSIM warnings fixed.`
69			`//`
70	18	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
71			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
72			`// Include files fixed to contain no path.`
73			`// File names and module names changed ta have a eth_ prologue in the name.`
74			`// File eth_timescale.v is used to define timescale`
75			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
76			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
77			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
78			`// is done due to the ASIC tools.`
79			`//`
80	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
81			`// Directory structure changed. Files checked and joind together.`
82			`//`
83			`//`
84			`//`
85			`//`
86			`//`
87
88	22	mohor	`include "timescale.v"
89	15	mohor
90
91			`module eth_macstatus(`
92	42	mohor	`MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,`
93	15	mohor	`MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,`
94	42	mohor	`RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,`
95			`InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,`
96			`r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,`
97	43	mohor	`LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,`
98			`RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,`
99	126	mohor	`StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr`
100	15	mohor	`);`
101
102
103
104			`parameter Tp = 1;`
105
106
107			`input MRxClk;`
108			`input Reset;`
109			`input RxCrcError;`
110			`input MRxErr;`
111			`input MRxDV;`
112
113			`input RxStateSFD;`
114			`input [1:0] RxStateData;`
115			`input RxStatePreamble;`
116			`input RxStateIdle;`
117			`input Transmitting;`
118			`input [15:0] RxByteCnt;`
119			`input RxByteCntEq0;`
120			`input RxByteCntGreat2;`
121			`input RxByteCntMaxFrame;`
122			`input ReceivedPauseFrm;`
123	42	mohor	`input [3:0] MRxD;`
124			`input Collision;`
125			`input [5:0] CollValid;`
126			`input r_RecSmall;`
127			`input [15:0] r_MinFL;`
128			`input [15:0] r_MaxFL;`
129			`input r_HugEn;`
130	43	mohor	`input StartTxDone;`
131			`input StartTxAbort;`
132			`input [3:0] RetryCnt;`
133			`input MTxClk;`
134			`input MaxCollisionOccured;`
135			`input LateCollision;`
136			`input StartDefer;`
137			`input TxStartFrm;`
138			`input StatePreamble;`
139			`input [1:0] StateData;`
140			`input CarrierSense;`
141			`input TxUsedData;`
142	15	mohor
143	43	mohor
144	15	mohor	`output ReceivedLengthOK;`
145			`output ReceiveEnd;`
146			`output ReceivedPacketGood;`
147	42	mohor	`output InvalidSymbol;`
148			`output LatchedCrcError;`
149			`output RxLateCollision;`
150			`output ShortFrame;`
151			`output DribbleNibble;`
152			`output ReceivedPacketTooBig;`
153			`output LoadRxStatus;`
154	43	mohor	`output [3:0] RetryCntLatched;`
155			`output RetryLimit;`
156			`output LateCollLatched;`
157			`output DeferLatched;`
158			`output CarrierSenseLost;`
159	126	mohor	`output LatchedMRxErr;`
160	15	mohor
161	43	mohor
162	15	mohor	`reg ReceiveEnd;`
163
164			`reg LatchedCrcError;`
165			`reg LatchedMRxErr;`
166	42	mohor	`reg LoadRxStatus;`
167			`reg InvalidSymbol;`
168	43	mohor	`reg [3:0] RetryCntLatched;`
169			`reg RetryLimit;`
170			`reg LateCollLatched;`
171			`reg DeferLatched;`
172			`reg CarrierSenseLost;`
173	15	mohor
174			`wire TakeSample;`
175	42	mohor	`wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps`
176	15	mohor
177			`// Crc error`
178			`always @ (posedge MRxClk or posedge Reset)`
179			`begin`
180			`if(Reset)`
181			`LatchedCrcError <=#Tp 1'b0;`
182			`else`
183	42	mohor	`if(RxStateSFD)`
184			`LatchedCrcError <=#Tp 1'b0;`
185			`else`
186			`if(RxStateData[0])`
187			`LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;`
188	15	mohor	`end`
189
190
191			`// LatchedMRxErr`
192			`always @ (posedge MRxClk or posedge Reset)`
193			`begin`
194			`if(Reset)`
195			`LatchedMRxErr <=#Tp 1'b0;`
196			`else`
197	18	mohor	`if(MRxErr & MRxDV & (RxStatePreamble \| RxStateSFD \| (\|RxStateData) \| RxStateIdle & ~Transmitting))`
198	15	mohor	`LatchedMRxErr <=#Tp 1'b1;`
199	126	mohor	`else`
200			`LatchedMRxErr <=#Tp 1'b0;`
201	15	mohor	`end`
202
203
204			`// ReceivedPacketGood`
205	126	mohor	`assign ReceivedPacketGood = ~LatchedCrcError;`
206	15	mohor
207
208			`// ReceivedLengthOK`
209	101	mohor	`assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];`
210	15	mohor
211
212
213	42	mohor
214
215			`// Time to take a sample`
216			`assign TakeSample = \|RxStateData & ~MRxDV & RxByteCntGreat2 \|`
217			`RxStateData[0] & MRxDV & RxByteCntMaxFrame;`
218
219
220			`// LoadRxStatus`
221	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
222			`begin`
223			`if(Reset)`
224	42	mohor	`LoadRxStatus <=#Tp 1'b0;`
225	15	mohor	`else`
226	42	mohor	`LoadRxStatus <=#Tp TakeSample;`
227	15	mohor	`end`
228
229
230
231	42	mohor	`// ReceiveEnd`
232			`always @ (posedge MRxClk or posedge Reset)`
233			`begin`
234			`if(Reset)`
235			`ReceiveEnd <=#Tp 1'b0;`
236			`else`
237			`ReceiveEnd <=#Tp LoadRxStatus;`
238			`end`
239	15	mohor
240
241	42	mohor	`// Invalid Symbol received during 100Mbps mode`
242	126	mohor	`assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;`
243	42	mohor
244
245			`// InvalidSymbol`
246	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
247			`begin`
248			`if(Reset)`
249	42	mohor	`InvalidSymbol <=#Tp 1'b0;`
250	15	mohor	`else`
251	42	mohor	`if(LoadRxStatus & ~SetInvalidSymbol)`
252			`InvalidSymbol <=#Tp 1'b0;`
253			`else`
254			`if(SetInvalidSymbol)`
255			`InvalidSymbol <=#Tp 1'b1;`
256	15	mohor	`end`
257
258
259	42	mohor	`// Late Collision`
260	15	mohor
261	42	mohor	`reg RxLateCollision;`
262			`reg RxColWindow;`
263			`// Collision Window`
264	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
265			`begin`
266			`if(Reset)`
267	42	mohor	`RxLateCollision <=#Tp 1'b0;`
268	15	mohor	`else`
269	42	mohor	`if(LoadRxStatus)`
270			`RxLateCollision <=#Tp 1'b0;`
271			`else`
272			`if(Collision & (~RxColWindow \| r_RecSmall))`
273			`RxLateCollision <=#Tp 1'b1;`
274	15	mohor	`end`
275
276	42	mohor	`// Collision Window`
277			`always @ (posedge MRxClk or posedge Reset)`
278			`begin`
279			`if(Reset)`
280			`RxColWindow <=#Tp 1'b1;`
281			`else`
282			`if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])`
283			`RxColWindow <=#Tp 1'b0;`
284			`else`
285			`if(RxStateIdle)`
286			`RxColWindow <=#Tp 1'b1;`
287			`end`
288	15	mohor
289	42	mohor
290			`// ShortFrame`
291			`reg ShortFrame;`
292			`always @ (posedge MRxClk or posedge Reset)`
293			`begin`
294			`if(Reset)`
295			`ShortFrame <=#Tp 1'b0;`
296			`else`
297			`if(LoadRxStatus)`
298			`ShortFrame <=#Tp 1'b0;`
299			`else`
300			`if(TakeSample)`
301	101	mohor	`ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];`
302	42	mohor	`end`
303
304
305			`// DribbleNibble`
306			`reg DribbleNibble;`
307			`always @ (posedge MRxClk or posedge Reset)`
308			`begin`
309			`if(Reset)`
310			`DribbleNibble <=#Tp 1'b0;`
311			`else`
312			`if(RxStateSFD)`
313			`DribbleNibble <=#Tp 1'b0;`
314			`else`
315			`if(~MRxDV & RxStateData[1])`
316			`DribbleNibble <=#Tp 1'b1;`
317			`end`
318
319
320			`reg ReceivedPacketTooBig;`
321			`always @ (posedge MRxClk or posedge Reset)`
322			`begin`
323			`if(Reset)`
324			`ReceivedPacketTooBig <=#Tp 1'b0;`
325			`else`
326			`if(LoadRxStatus)`
327			`ReceivedPacketTooBig <=#Tp 1'b0;`
328			`else`
329			`if(TakeSample)`
330			`ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];`
331			`end`
332
333	43	mohor
334
335			`// Latched Retry counter for tx status`
336			`always @ (posedge MTxClk or posedge Reset)`
337			`begin`
338			`if(Reset)`
339			`RetryCntLatched <=#Tp 4'h0;`
340			`else`
341			`if(StartTxDone \| StartTxAbort)`
342			`RetryCntLatched <=#Tp RetryCnt;`
343			`end`
344
345
346			`// Latched Retransmission limit`
347			`always @ (posedge MTxClk or posedge Reset)`
348			`begin`
349			`if(Reset)`
350			`RetryLimit <=#Tp 4'h0;`
351			`else`
352			`if(StartTxDone \| StartTxAbort)`
353			`RetryLimit <=#Tp MaxCollisionOccured;`
354			`end`
355
356
357			`// Latched Late Collision`
358			`always @ (posedge MTxClk or posedge Reset)`
359			`begin`
360			`if(Reset)`
361			`LateCollLatched <=#Tp 1'b0;`
362			`else`
363			`if(StartTxDone \| StartTxAbort)`
364			`LateCollLatched <=#Tp LateCollision;`
365			`end`
366
367
368
369			`// Latched Defer state`
370			`always @ (posedge MTxClk or posedge Reset)`
371			`begin`
372			`if(Reset)`
373			`DeferLatched <=#Tp 1'b0;`
374			`else`
375			`if(StartDefer & TxUsedData)`
376			`DeferLatched <=#Tp 1'b1;`
377			`else`
378			`if(TxStartFrm)`
379			`DeferLatched <=#Tp 1'b0;`
380			`end`
381
382
383			`// CarrierSenseLost`
384			`always @ (posedge MTxClk or posedge Reset)`
385			`begin`
386			`if(Reset)`
387			`CarrierSenseLost <=#Tp 1'b0;`
388			`else`
389	64	mohor	`if((StatePreamble \| (\|StateData)) & ~CarrierSense & ~Collision)`
390	43	mohor	`CarrierSenseLost <=#Tp 1'b1;`
391			`else`
392			`if(TxStartFrm)`
393			`CarrierSenseLost <=#Tp 1'b0;`
394			`end`
395
396
397	15	mohor	`endmodule`

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