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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_transmitcontrol.v                                       ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1  2001/07/03 12:51:54  mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
 
 
`include "timescale.v"
 
 
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
                            TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
                            TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
                            ControlData, WillSendControlFrame, BlockTxDone
                           );
 
parameter Tp = 1;
 
 
input         MTxClk;
input         TxReset;
input         TxUsedDataIn;
input         TxUsedDataOut;
input         TxDoneIn;
input         TxAbortIn;
input         TxStartFrmIn;
input         TPauseRq;
input         TxUsedDataOutDetected;
input         TxFlow;
input         DlyCrcEn;
input  [15:0] TxPauseTV;
input  [47:0] MAC;
 
output        TxCtrlStartFrm;
output        TxCtrlEndFrm;
output        SendingCtrlFrm;
output        CtrlMux;
output [7:0]  ControlData;
output        WillSendControlFrame;
output        BlockTxDone;
 
reg           SendingCtrlFrm;
reg           CtrlMux;
reg           WillSendControlFrame;
reg    [3:0]  DlyCrcCnt;
reg    [5:0]  ByteCnt;
reg           ControlEnd_q;
reg    [7:0]  MuxedCtrlData;
reg           TxCtrlStartFrm;
reg           TxCtrlStartFrm_q;
reg           TxCtrlEndFrm;
reg    [7:0]  ControlData;
reg           TxUsedDataIn_q;
reg           BlockTxDone;
 
wire          IncrementDlyCrcCnt;
wire          ResetByteCnt;
wire          IncrementByteCnt;
wire          ControlEnd;
 
 
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    WillSendControlFrame <= #Tp 1'b0;
  else
  if(TxCtrlEndFrm & CtrlMux)
    WillSendControlFrame <= #Tp 1'b0;
  else
  if(TPauseRq & TxFlow)
    WillSendControlFrame <= #Tp 1'b1;
end
 
 
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxCtrlStartFrm <= #Tp 1'b0;
  else
  if(TxUsedDataIn_q & CtrlMux)
    TxCtrlStartFrm <= #Tp 1'b0;
  else
  if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
    TxCtrlStartFrm <= #Tp 1'b1;
end
 
 
 
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxCtrlEndFrm <= #Tp 1'b0;
  else
  if(ControlEnd | ControlEnd_q)
    TxCtrlEndFrm <= #Tp 1'b1;
  else
    TxCtrlEndFrm <= #Tp 1'b0;
end
 
 
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    CtrlMux <= #Tp 1'b0;
  else
  if(WillSendControlFrame & ~TxUsedDataOut)
    CtrlMux <= #Tp 1'b1;
  else
  if(TxDoneIn)
    CtrlMux <= #Tp 1'b0;
end
 
 
 
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    SendingCtrlFrm <= #Tp 1'b0;
  else
  if(WillSendControlFrame & TxCtrlStartFrm)
    SendingCtrlFrm <= #Tp 1'b1;
  else
  if(TxDoneIn)
    SendingCtrlFrm <= #Tp 1'b0;
end
 
 
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxUsedDataIn_q <= #Tp 1'b0;
  else
    TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
 
 
 
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    BlockTxDone <= #Tp 1'b0;
  else
  if(TxCtrlStartFrm)
    BlockTxDone <= #Tp 1'b1;
  else
  if(TxDoneIn)
    BlockTxDone <= #Tp 1'b0;
end
 
 
always @ (posedge MTxClk)
begin
  ControlEnd_q     <= #Tp ControlEnd;
  TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
 
 
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
 
 
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    DlyCrcCnt <= #Tp 4'h0;
  else
  if(ResetByteCnt)
    DlyCrcCnt <= #Tp 4'h0;
  else
  if(IncrementDlyCrcCnt)
    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
 
 
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
 
 
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    ByteCnt <= #Tp 6'h0;
  else
  if(ResetByteCnt)
    ByteCnt <= #Tp 6'h0;
  else
  if(IncrementByteCnt & (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])))
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
 
 
assign ControlEnd = ByteCnt[5:0] == 6'h22;
 
 
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
  case(ByteCnt)
    6'h0:    if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
               MuxedCtrlData[7:0] = 8'h01;                   // Reserved Multicast Address
             else
                                                         MuxedCtrlData[7:0] = 8'h0;
    6'h2:      MuxedCtrlData[7:0] = 8'h80;
    6'h4:      MuxedCtrlData[7:0] = 8'hC2;
    6'h6:      MuxedCtrlData[7:0] = 8'h00;
    6'h8:      MuxedCtrlData[7:0] = 8'h00;
    6'hA:      MuxedCtrlData[7:0] = 8'h01;
    6'hC:      MuxedCtrlData[7:0] = MAC[47:40];
    6'hE:      MuxedCtrlData[7:0] = MAC[39:32];
    6'h10:     MuxedCtrlData[7:0] = MAC[31:24];
    6'h12:     MuxedCtrlData[7:0] = MAC[23:16];
    6'h14:     MuxedCtrlData[7:0] = MAC[15:8];
    6'h16:     MuxedCtrlData[7:0] = MAC[7:0];
    6'h18:     MuxedCtrlData[7:0] = 8'h88;                   // Type/Length
    6'h1A:     MuxedCtrlData[7:0] = 8'h08;
    6'h1C:     MuxedCtrlData[7:0] = 8'h00;                   // Opcode
    6'h1E:     MuxedCtrlData[7:0] = 8'h01;
    6'h20:     MuxedCtrlData[7:0] = TxPauseTV[15:8];         // Pause timer value
    6'h22:     MuxedCtrlData[7:0] = TxPauseTV[7:0];
    default:   MuxedCtrlData[7:0] = 8'h0;
  endcase
end
 
 
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    ControlData[7:0] <= #Tp 8'h0;
  else
  if(~ByteCnt[0])
    ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
 
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_transmitcontrol.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	251	mohor	`// Revision 1.4 2002/01/23 10:28:16 mohor`
45			`// Link in the header changed.`
46			`//`
47	37	mohor	`// Revision 1.3 2001/10/19 08:43:51 mohor`
48			`// eth_timescale.v changed to timescale.v This is done because of the`
49			`// simulation of the few cores in a one joined project.`
50			`//`
51	22	mohor	`// Revision 1.2 2001/09/11 14:17:00 mohor`
52			`// Few little NCSIM warnings fixed.`
53			`//`
54	18	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
55			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
56			`// Include files fixed to contain no path.`
57			`// File names and module names changed ta have a eth_ prologue in the name.`
58			`// File eth_timescale.v is used to define timescale`
59			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
60			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
61			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
62			`// is done due to the ASIC tools.`
63			`//`
64	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
65			`// Directory structure changed. Files checked and joind together.`
66			`//`
67			`// Revision 1.1 2001/07/03 12:51:54 mohor`
68			`// Initial release of the MAC Control module.`
69			`//`
70			`//`
71			`//`
72			`//`
73			`//`
74			`//`
75
76
77	22	mohor	`include "timescale.v"
78	15	mohor
79
80			`module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,`
81			`TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,`
82			`TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,`
83	251	mohor	`ControlData, WillSendControlFrame, BlockTxDone`
84	15	mohor	`);`
85
86			`parameter Tp = 1;`
87
88
89			`input MTxClk;`
90			`input TxReset;`
91			`input TxUsedDataIn;`
92			`input TxUsedDataOut;`
93			`input TxDoneIn;`
94			`input TxAbortIn;`
95			`input TxStartFrmIn;`
96			`input TPauseRq;`
97			`input TxUsedDataOutDetected;`
98			`input TxFlow;`
99			`input DlyCrcEn;`
100			`input [15:0] TxPauseTV;`
101			`input [47:0] MAC;`
102
103			`output TxCtrlStartFrm;`
104			`output TxCtrlEndFrm;`
105			`output SendingCtrlFrm;`
106			`output CtrlMux;`
107			`output [7:0] ControlData;`
108			`output WillSendControlFrame;`
109	251	mohor	`output BlockTxDone;`
110	15	mohor
111			`reg SendingCtrlFrm;`
112			`reg CtrlMux;`
113			`reg WillSendControlFrame;`
114			`reg [3:0] DlyCrcCnt;`
115			`reg [5:0] ByteCnt;`
116			`reg ControlEnd_q;`
117			`reg [7:0] MuxedCtrlData;`
118			`reg TxCtrlStartFrm;`
119			`reg TxCtrlStartFrm_q;`
120			`reg TxCtrlEndFrm;`
121			`reg [7:0] ControlData;`
122			`reg TxUsedDataIn_q;`
123	251	mohor	`reg BlockTxDone;`
124	15	mohor
125			`wire IncrementDlyCrcCnt;`
126			`wire ResetByteCnt;`
127			`wire IncrementByteCnt;`
128			`wire ControlEnd;`
129
130
131			`// A command for Sending the control frame is active (latched)`
132			`always @ (posedge MTxClk or posedge TxReset)`
133			`begin`
134			`if(TxReset)`
135			`WillSendControlFrame <= #Tp 1'b0;`
136			`else`
137			`if(TxCtrlEndFrm & CtrlMux)`
138			`WillSendControlFrame <= #Tp 1'b0;`
139			`else`
140			`if(TPauseRq & TxFlow)`
141			`WillSendControlFrame <= #Tp 1'b1;`
142			`end`
143
144
145			`// Generation of the transmit control packet start frame`
146			`always @ (posedge MTxClk or posedge TxReset)`
147			`begin`
148			`if(TxReset)`
149			`TxCtrlStartFrm <= #Tp 1'b0;`
150			`else`
151			`if(TxUsedDataIn_q & CtrlMux)`
152			`TxCtrlStartFrm <= #Tp 1'b0;`
153			`else`
154	251	mohor	`if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn \| TxAbortIn \| TxStartFrmIn \| (~TxUsedDataOutDetected)))`
155	15	mohor	`TxCtrlStartFrm <= #Tp 1'b1;`
156			`end`
157
158
159
160			`// Generation of the transmit control packet end frame`
161			`always @ (posedge MTxClk or posedge TxReset)`
162			`begin`
163			`if(TxReset)`
164			`TxCtrlEndFrm <= #Tp 1'b0;`
165			`else`
166			`if(ControlEnd \| ControlEnd_q)`
167			`TxCtrlEndFrm <= #Tp 1'b1;`
168			`else`
169			`TxCtrlEndFrm <= #Tp 1'b0;`
170			`end`
171
172
173			`// Generation of the multiplexer signal (controls muxes for switching between`
174			`// normal and control packets)`
175			`always @ (posedge MTxClk or posedge TxReset)`
176			`begin`
177			`if(TxReset)`
178			`CtrlMux <= #Tp 1'b0;`
179			`else`
180			`if(WillSendControlFrame & ~TxUsedDataOut)`
181			`CtrlMux <= #Tp 1'b1;`
182			`else`
183			`if(TxDoneIn)`
184			`CtrlMux <= #Tp 1'b0;`
185			`end`
186
187
188
189			`// Generation of the Sending Control Frame signal (enables padding and CRC)`
190			`always @ (posedge MTxClk or posedge TxReset)`
191			`begin`
192			`if(TxReset)`
193			`SendingCtrlFrm <= #Tp 1'b0;`
194			`else`
195			`if(WillSendControlFrame & TxCtrlStartFrm)`
196			`SendingCtrlFrm <= #Tp 1'b1;`
197			`else`
198			`if(TxDoneIn)`
199			`SendingCtrlFrm <= #Tp 1'b0;`
200			`end`
201
202
203			`always @ (posedge MTxClk or posedge TxReset)`
204			`begin`
205			`if(TxReset)`
206			`TxUsedDataIn_q <= #Tp 1'b0;`
207			`else`
208			`TxUsedDataIn_q <= #Tp TxUsedDataIn;`
209			`end`
210
211
212	251	mohor
213			`// Generation of the signal that will block sending the Done signal to the eth_wishbone module`
214			`// While sending the control frame`
215			`always @ (posedge MTxClk or posedge TxReset)`
216			`begin`
217			`if(TxReset)`
218			`BlockTxDone <= #Tp 1'b0;`
219			`else`
220			`if(TxCtrlStartFrm)`
221			`BlockTxDone <= #Tp 1'b1;`
222			`else`
223			`if(TxDoneIn)`
224			`BlockTxDone <= #Tp 1'b0;`
225			`end`
226
227
228	15	mohor	`always @ (posedge MTxClk)`
229			`begin`
230			`ControlEnd_q <= #Tp ControlEnd;`
231			`TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;`
232			`end`
233
234
235			`assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];`
236
237
238			`// Delayed CRC counter`
239			`always @ (posedge MTxClk or posedge TxReset)`
240			`begin`
241			`if(TxReset)`
242			`DlyCrcCnt <= #Tp 4'h0;`
243			`else`
244			`if(ResetByteCnt)`
245			`DlyCrcCnt <= #Tp 4'h0;`
246			`else`
247			`if(IncrementDlyCrcCnt)`
248			`DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;`
249			`end`
250
251
252			`assign ResetByteCnt = TxReset \| (~TxCtrlStartFrm & (TxDoneIn \| TxAbortIn));`
253			`assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn \| TxUsedDataIn & ~ControlEnd);`
254
255
256			`// Byte counter`
257			`always @ (posedge MTxClk or posedge TxReset)`
258			`begin`
259			`if(TxReset)`
260			`ByteCnt <= #Tp 6'h0;`
261			`else`
262			`if(ResetByteCnt)`
263			`ByteCnt <= #Tp 6'h0;`
264			`else`
265	18	mohor	`if(IncrementByteCnt & (~DlyCrcEn \| DlyCrcEn & (&DlyCrcCnt[1:0])))`
266	15	mohor	`ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;`
267			`end`
268
269
270			`assign ControlEnd = ByteCnt[5:0] == 6'h22;`
271
272
273			`// Control data generation (goes to the TxEthMAC module)`
274			`always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)`
275			`begin`
276			`case(ByteCnt)`
277	18	mohor	`6'h0: if(~DlyCrcEn \| DlyCrcEn & (&DlyCrcCnt[1:0]))`
278	15	mohor	`MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address`
279			`else`
280			`MuxedCtrlData[7:0] = 8'h0;`
281			`6'h2: MuxedCtrlData[7:0] = 8'h80;`
282			`6'h4: MuxedCtrlData[7:0] = 8'hC2;`
283			`6'h6: MuxedCtrlData[7:0] = 8'h00;`
284			`6'h8: MuxedCtrlData[7:0] = 8'h00;`
285			`6'hA: MuxedCtrlData[7:0] = 8'h01;`
286			`6'hC: MuxedCtrlData[7:0] = MAC[47:40];`
287			`6'hE: MuxedCtrlData[7:0] = MAC[39:32];`
288			`6'h10: MuxedCtrlData[7:0] = MAC[31:24];`
289			`6'h12: MuxedCtrlData[7:0] = MAC[23:16];`
290			`6'h14: MuxedCtrlData[7:0] = MAC[15:8];`
291			`6'h16: MuxedCtrlData[7:0] = MAC[7:0];`
292			`6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length`
293			`6'h1A: MuxedCtrlData[7:0] = 8'h08;`
294			`6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode`
295			`6'h1E: MuxedCtrlData[7:0] = 8'h01;`
296			`6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value`
297			`6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];`
298			`default: MuxedCtrlData[7:0] = 8'h0;`
299			`endcase`
300			`end`
301
302
303			`// Latched Control data`
304			`always @ (posedge MTxClk or posedge TxReset)`
305			`begin`
306			`if(TxReset)`
307			`ControlData[7:0] <= #Tp 8'h0;`
308			`else`
309			`if(~ByteCnt[0])`
310			`ControlData[7:0] <= #Tp MuxedCtrlData[7:0];`
311			`end`
312
313
314
315			`endmodule`

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