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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_macstatus.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
`include "eth_timescale.v"
 
 
module eth_macstatus(
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, TransmitEnd, ReceivedPacketGood, RxCrcError,
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm
                    );
 
 
 
parameter Tp = 1;
 
 
input         MRxClk;
input         Reset;
input         RxCrcError;
input         MRxErr;
input         MRxDV;
 
input         RxStateSFD;
input   [1:0] RxStateData;
input         RxStatePreamble;
input         RxStateIdle;
input         Transmitting;
input  [15:0] RxByteCnt;
input         RxByteCntEq0;
input         RxByteCntGreat2;
input         RxByteCntMaxFrame;
input         ReceivedPauseFrm;
 
output        ReceivedLengthOK;
output        ReceiveEnd;
output        ReceivedPacketGood;
output        TransmitEnd;
 
reg           ReceiveEnd;
 
reg           LatchedCrcError;
reg           LatchedMRxErr;
reg           PreloadRxStatus;
reg    [15:0] LatchedRxByteCnt;
 
wire          TakeSample;
 
 
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedCrcError <=#Tp 1'b0;
  else
    begin
      if(RxStateSFD)
        LatchedCrcError <=#Tp 1'b0;
      else
      if(RxStateData[0])
        LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
    end
end
 
 
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedMRxErr <=#Tp 1'b0;
  else
  if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
    LatchedMRxErr <=#Tp 1'b0;
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | |RxStateData | RxStateIdle & ~Transmitting))
    LatchedMRxErr <=#Tp 1'b1;
end
 
 
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError & ~LatchedMRxErr;
 
 
// ReceivedLengthOK
assign ReceivedLengthOK = LatchedRxByteCnt[15:0] > 63 & LatchedRxByteCnt[15:0] < 1519;
 
 
 
// LatchedRxByteCnt[15:0]
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedRxByteCnt[15:0] <=#Tp 16'h0;
  else
    begin
      if(RxStateSFD)
        LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
      else
      if(RxStateData[0])
        LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
    end
end
 
 
 
// Time to take a sample
assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
                     RxStateData[0]  &  MRxDV & RxByteCntMaxFrame;
 
 
// PreloadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    PreloadRxStatus <=#Tp 1'b0;
  else
    PreloadRxStatus <=#Tp TakeSample;
end
 
 
 
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceiveEnd  <=#Tp 1'b0;
  else
    ReceiveEnd  <=#Tp PreloadRxStatus;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_macstatus.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.1 2001/07/30 21:23:42 mohor`
45			`// Directory structure changed. Files checked and joind together.`
46			`//`
47			`//`
48			`//`
49			`//`
50			`//`
51
52			`include "eth_timescale.v"
53
54
55			`module eth_macstatus(`
56			`MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, TransmitEnd, ReceivedPacketGood, RxCrcError,`
57			`MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,`
58			`RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm`
59			`);`
60
61
62
63			`parameter Tp = 1;`
64
65
66			`input MRxClk;`
67			`input Reset;`
68			`input RxCrcError;`
69			`input MRxErr;`
70			`input MRxDV;`
71
72			`input RxStateSFD;`
73			`input [1:0] RxStateData;`
74			`input RxStatePreamble;`
75			`input RxStateIdle;`
76			`input Transmitting;`
77			`input [15:0] RxByteCnt;`
78			`input RxByteCntEq0;`
79			`input RxByteCntGreat2;`
80			`input RxByteCntMaxFrame;`
81			`input ReceivedPauseFrm;`
82
83			`output ReceivedLengthOK;`
84			`output ReceiveEnd;`
85			`output ReceivedPacketGood;`
86			`output TransmitEnd;`
87
88			`reg ReceiveEnd;`
89
90			`reg LatchedCrcError;`
91			`reg LatchedMRxErr;`
92			`reg PreloadRxStatus;`
93			`reg [15:0] LatchedRxByteCnt;`
94
95			`wire TakeSample;`
96
97
98			`// Crc error`
99			`always @ (posedge MRxClk or posedge Reset)`
100			`begin`
101			`if(Reset)`
102			`LatchedCrcError <=#Tp 1'b0;`
103			`else`
104			`begin`
105			`if(RxStateSFD)`
106			`LatchedCrcError <=#Tp 1'b0;`
107			`else`
108			`if(RxStateData[0])`
109			`LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;`
110			`end`
111			`end`
112
113
114			`// LatchedMRxErr`
115			`always @ (posedge MRxClk or posedge Reset)`
116			`begin`
117			`if(Reset)`
118			`LatchedMRxErr <=#Tp 1'b0;`
119			`else`
120			`if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)`
121			`LatchedMRxErr <=#Tp 1'b0;`
122			`else`
123			`if(MRxErr & MRxDV & (RxStatePreamble \| RxStateSFD \| \|RxStateData \| RxStateIdle & ~Transmitting))`
124			`LatchedMRxErr <=#Tp 1'b1;`
125			`end`
126
127
128			`// ReceivedPacketGood`
129			`assign ReceivedPacketGood = ~LatchedCrcError & ~LatchedMRxErr;`
130
131
132			`// ReceivedLengthOK`
133			`assign ReceivedLengthOK = LatchedRxByteCnt[15:0] > 63 & LatchedRxByteCnt[15:0] < 1519;`
134
135
136
137			`// LatchedRxByteCnt[15:0]`
138			`always @ (posedge MRxClk or posedge Reset)`
139			`begin`
140			`if(Reset)`
141			`LatchedRxByteCnt[15:0] <=#Tp 16'h0;`
142			`else`
143			`begin`
144			`if(RxStateSFD)`
145			`LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];`
146			`else`
147			`if(RxStateData[0])`
148			`LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];`
149			`end`
150			`end`
151
152
153
154			`// Time to take a sample`
155			`assign TakeSample = \|RxStateData & ~MRxDV & RxByteCntGreat2 \|`
156			`RxStateData[0] & MRxDV & RxByteCntMaxFrame;`
157
158
159			`// PreloadRxStatus`
160			`always @ (posedge MRxClk or posedge Reset)`
161			`begin`
162			`if(Reset)`
163			`PreloadRxStatus <=#Tp 1'b0;`
164			`else`
165			`PreloadRxStatus <=#Tp TakeSample;`
166			`end`
167
168
169
170			`// ReceiveEnd`
171			`always @ (posedge MRxClk or posedge Reset)`
172			`begin`
173			`if(Reset)`
174			`ReceiveEnd <=#Tp 1'b0;`
175			`else`
176			`ReceiveEnd <=#Tp PreloadRxStatus;`
177			`end`
178
179
180			`endmodule`

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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_macstatus.v] - Blame information for rev 15