//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "eth_timescale.v"
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule