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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  tb_ethernet.v                                               ////

////                                                              ////

////  This file is part of the Ethernet IP core project           ////

////  http://www.opencores.org/projects/ethmac/                   ////

////                                                              ////

////  Author(s):                                                  ////

////      - Tadej Markovic, tadej@opencores.org                   ////

////      - Igor Mohor,     igorM@opencores.org                  ////

////                                                              ////

////  All additional information is available in the Readme.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2001, 2002 Authors                             ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.30  2003/10/17 07:45:17  markom

// mbist signals updated according to newest convention

//

// Revision 1.29  2003/08/20 12:06:24  mohor

// Artisan RAMs added.

//

// Revision 1.28  2003/01/31 15:58:27  mohor

// Tests test_mac_full_duplex_receive 4-7  fixed to proper BD.

//

// Revision 1.27  2003/01/30 13:38:15  mohor

// Underrun test fixed. Many other tests fixed.

//

// Revision 1.26  2003/01/22 19:40:10  tadejm

// Backup version. Not fully working.

//

// Revision 1.25  2002/11/27 16:21:55  mohor

// Full duplex control frames tested.

//

// Revision 1.24  2002/11/22 17:29:42  mohor

// Flow control test almost finished.

//

// Revision 1.23  2002/11/22 02:12:16  mohor

// test_mac_full_duplex_flow_control tests pretty much finished.

// TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL

// FRM. AT 4 TX BD ( 10Mbps ) finished.

// TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION

// TURNED OFF AT ONE RX BD ( 10Mbps ) finished.

//

// Revision 1.22  2002/11/21 13:56:50  mohor

// test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame

// finished.

//

// Revision 1.21  2002/11/19 20:27:45  mohor

// Temp version.

//

// Revision 1.20  2002/11/19 17:41:19  tadejm

// Just some updates.

//

// Revision 1.19  2002/11/14 13:12:47  tadejm

// Late collision is not reported any more.

//

// Revision 1.18  2002/10/18 17:03:34  tadejm

// Changed BIST scan signals.

//

// Revision 1.17  2002/10/18 13:58:22  tadejm

// Some code changed due to bug fixes.

//

// Revision 1.16  2002/10/09 13:16:51  tadejm

// Just back-up; not completed testbench and some testcases are not

// wotking properly yet.

//

// Revision 1.15  2002/09/20 14:29:12  tadej

// Full duplex tests modified and testbench bug repaired.

//

// Revision 1.14  2002/09/18 17:56:38  tadej

// Some additional reports added

//

// Revision 1.13  2002/09/16 17:53:49  tadej

// Full duplex test improved.

//

// Revision 1.12  2002/09/16 15:10:42  mohor

// MIIM test look better.

//

// Revision 1.11  2002/09/13 19:18:04  mohor

// Bench outputs data to display every 128 bytes.

//

// Revision 1.10  2002/09/13 18:44:29  mohor

// Beautiful tests merget together

//

// Revision 1.9  2002/09/13 18:41:45  mohor

// Rearanged testcases

//

// Revision 1.8  2002/09/13 14:50:15  mohor

// Bug in MIIM fixed.

//

// Revision 1.7  2002/09/13 12:29:14  mohor

// Headers changed.

//

// Revision 1.6  2002/09/13 11:57:20  mohor

// New testbench. Thanks to Tadej M - "The Spammer".

//

// Revision 1.2  2002/07/19 14:02:47  mohor

// Clock mrx_clk set to 2.5 MHz.

//

// Revision 1.1  2002/07/19 13:57:53  mohor

// Testing environment also includes traffic cop, memory interface and host

// interface.

//

//

//

//

//

`include "eth_phy_defines.v"

`include "wb_model_defines.v"

`include "tb_eth_defines.v"

`include "eth_defines.v"

`include "timescale.v"

module tb_ethernet();

reg           wb_clk;

reg           wb_rst;

wire          wb_int;

wire          mtx_clk;  // This goes to PHY

wire          mrx_clk;  // This goes to PHY

wire   [3:0]  MTxD;

wire          MTxEn;

wire          MTxErr;

wire   [3:0]  MRxD;     // This goes to PHY

wire          MRxDV;    // This goes to PHY

wire          MRxErr;   // This goes to PHY

wire          MColl;    // This goes to PHY

wire          MCrs;     // This goes to PHY

wire          Mdi_I;

wire          Mdo_O;

wire          Mdo_OE;

tri           Mdio_IO;

wire          Mdc_O;

parameter Tp = 1;

// Ethernet Slave Interface signals

wire [31:0] eth_sl_wb_adr;

wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;

wire  [3:0] eth_sl_wb_sel_i;

wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;

// Ethernet Master Interface signals

wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;

wire  [3:0] eth_ma_wb_sel_o;

wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;

wire  [2:0] eth_ma_wb_cti_o;

wire  [1:0] eth_ma_wb_bte_o;

// Connecting Ethernet top module

eth_top eth_top

(

  // WISHBONE common

  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),

  // WISHBONE slave

  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),

  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),

  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),

  // WISHBONE master

  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),

  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),

  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),

`ifdef ETH_WISHBONE_B3

  .m_wb_cti_o(eth_ma_wb_cti_o),     .m_wb_bte_o(eth_ma_wb_bte_o),

`endif

  //TX

  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),

  //RX

  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),

  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),

  // MIIM

  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),

  .int_o(wb_int)

  // Bist

`ifdef ETH_BIST

  ,

  .mbist_si_i       (1'b0),

  .mbist_so_o       (),

  .mbist_ctrl_i       (3'b001) // {enable, clock, reset}

`endif

);

// Connecting Ethernet PHY Module

assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;

assign Mdi_I   = Mdio_IO;

integer phy_log_file_desc;

eth_phy eth_phy

(

  // WISHBONE reset

  .m_rst_n_i(!wb_rst),

  // MAC TX

  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),

  // MAC RX

  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),

  .mcoll_o(MColl),        .mcrs_o(MCrs),

  // MIIM

  .mdc_i(Mdc_O),          .md_io(Mdio_IO),

  // SYSTEM

  .phy_log(phy_log_file_desc)

);

// Connecting WB Master as Host Interface

integer host_log_file_desc;

WB_MASTER_BEHAVIORAL wb_master

(

    .CLK_I(wb_clk),

    .RST_I(wb_rst),

    .TAG_I({`WB_TAG_WIDTH{1'b0}}),

    .TAG_O(),

    .ACK_I(eth_sl_wb_ack_o),

    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used

    .CYC_O(eth_sl_wb_cyc_i),

    .DAT_I(eth_sl_wb_dat_o),

    .DAT_O(eth_sl_wb_dat_i),

    .ERR_I(eth_sl_wb_err_o),

    .RTY_I(1'b0),  // inactive (1'b0)

    .SEL_O(eth_sl_wb_sel_i),

    .STB_O(eth_sl_wb_stb_i),

    .WE_O (eth_sl_wb_we_i),

    .CAB_O()       // NOT USED for now!

);

assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};

// Connecting WB Slave as Memory Interface Module

integer memory_log_file_desc;

WB_SLAVE_BEHAVIORAL wb_slave

(

    .CLK_I(wb_clk),

    .RST_I(wb_rst),

    .ACK_O(eth_ma_wb_ack_i),

    .ADR_I(eth_ma_wb_adr_o),

    .CYC_I(eth_ma_wb_cyc_o),

    .DAT_O(eth_ma_wb_dat_i),

    .DAT_I(eth_ma_wb_dat_o),

    .ERR_O(eth_ma_wb_err_i),

    .RTY_O(),      // NOT USED for now!

    .SEL_I(eth_ma_wb_sel_o),

    .STB_I(eth_ma_wb_stb_o),

    .WE_I (eth_ma_wb_we_o),

    .CAB_I(1'b0)

);

// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces

integer wb_s_mon_log_file_desc ;

integer wb_m_mon_log_file_desc ;

WB_BUS_MON wb_eth_slave_bus_mon

(

  // WISHBONE common

  .CLK_I(wb_clk),

  .RST_I(wb_rst),

  // WISHBONE slave

  .ACK_I(eth_sl_wb_ack_o),

  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),

  .CYC_O(eth_sl_wb_cyc_i),

  .DAT_I(eth_sl_wb_dat_o),

  .DAT_O(eth_sl_wb_dat_i),

  .ERR_I(eth_sl_wb_err_o),

  .RTY_I(1'b0),

  .SEL_O(eth_sl_wb_sel_i),

  .STB_O(eth_sl_wb_stb_i),

  .WE_O (eth_sl_wb_we_i),

  .TAG_I({`WB_TAG_WIDTH{1'b0}}),

`ifdef ETH_WISHBONE_B3

  .TAG_O({eth_ma_wb_cti_o, eth_ma_wb_bte_o}),

`else

  .TAG_O(5'h0),

`endif

  .CAB_O(1'b0),

`ifdef ETH_WISHBONE_B3

  .check_CTI          (1'b1),

`else

  .check_CTI          (1'b0),

`endif

  .log_file_desc (wb_s_mon_log_file_desc)

);

WB_BUS_MON wb_eth_master_bus_mon

(

  // WISHBONE common

  .CLK_I(wb_clk),

  .RST_I(wb_rst),

  // WISHBONE master

  .ACK_I(eth_ma_wb_ack_i),

  .ADDR_O(eth_ma_wb_adr_o),

  .CYC_O(eth_ma_wb_cyc_o),

  .DAT_I(eth_ma_wb_dat_i),

  .DAT_O(eth_ma_wb_dat_o),

  .ERR_I(eth_ma_wb_err_i),

  .RTY_I(1'b0),

  .SEL_O(eth_ma_wb_sel_o),

  .STB_O(eth_ma_wb_stb_o),

  .WE_O (eth_ma_wb_we_o),

  .TAG_I({`WB_TAG_WIDTH{1'b0}}),

  .TAG_O(5'h0),

  .CAB_O(1'b0),

  .check_CTI(1'b0), // NO need

  .log_file_desc(wb_m_mon_log_file_desc)

);

reg         StartTB;

integer     tb_log_file;

initial

begin

  tb_log_file = $fopen("../log/eth_tb.log");

  if (tb_log_file < 2)

  begin

    $display("*E Could not open/create testbench log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");

  $fdisplay(tb_log_file, " ");

  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");

  if (phy_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");

  $fdisplay(phy_log_file_desc, " ");

  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");

  if (memory_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");

  $fdisplay(memory_log_file_desc, " ");

  host_log_file_desc = $fopen("../log/eth_tb_host.log");

  if (host_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");

  $fdisplay(host_log_file_desc, " ");

  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");

  if (wb_s_mon_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");

  $fdisplay(wb_s_mon_log_file_desc, " ");

  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");

  $fdisplay(wb_s_mon_log_file_desc, " ");

  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");

  if (wb_m_mon_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");

  $fdisplay(wb_m_mon_log_file_desc, " ");

  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");

  $fdisplay(wb_m_mon_log_file_desc, " ");

  // Reset pulse

  wb_rst =  1'b1;

  #423 wb_rst =  1'b0;

  // Clear memories

  clear_memories;

  clear_buffer_descriptors;

  #423 StartTB  =  1'b1;

end

// Generating wb_clk clock

initial

begin

  wb_clk=0;

//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    

//  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    

//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    

//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    

  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    

//  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    

//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz

//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    

//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz

//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    

end

integer      tests_successfull;

integer      tests_failed;

reg [799:0]  test_name; // used for tb_log_file

reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master

reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master

reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds

reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK

reg          wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working

initial

begin

  wait(StartTB);  // Start of testbench

  // Initial global values

  tests_successfull = 0;

  tests_failed = 0;

  wbm_working = 0;

  wbm_init_waits = 4'h1;

  wbm_subseq_waits = 4'h3;

  wbs_waits = 4'h1;

  wbs_retries = 8'h2;

  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);

  // set DIFFERENT mrx_clk to mtx_clk!

//  eth_phy.set_mrx_equal_mtx = 1'b0;

  //  Call tests

  //  ----------

    test_access_to_mac_reg(0, 4);           // 0 - 4

    test_mii(0, 17);                        // 0 - 17

  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");

  eth_phy.carrier_sense_real_delay(0);

//    test_mac_full_duplex_transmit(0, 21);    // 0 - (21)

//    test_mac_full_duplex_receive(2, 2);     // 0 - 13

//    test_mac_full_duplex_flow_control(0, 4);  // 0 - 4

                                              // 4 is executed, everything is OK

//    test_mac_half_duplex_flow(0, 0);

  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");

  eth_phy.carrier_sense_real_delay(1);

  // Finish test's logs

  test_summary;

  $display("\n\n END of SIMULATION");

  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);

  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);

  $stop;

end

//////////////////////////////////////////////////////////////

// Test tasks

//////////////////////////////////////////////////////////////

task test_access_to_mac_reg;

  input  [31:0]  start_task;

  input  [31:0]  end_task;

  integer        bit_start_1;

  integer        bit_end_1;

  integer        bit_start_2;

  integer        bit_end_2;

  integer        num_of_reg;

  integer        i_addr;

  integer        i_data;

  integer        i_length;

  integer        tmp_data;

  reg    [31:0]  tx_bd_num;

  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;

  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;

  integer        i;

  integer        i1;

  integer        i2;

  integer        i3;

  integer        fail;

  integer        test_num;

  reg    [31:0]  addr;

  reg    [31:0]  data;

  reg     [3:0]  sel;

  reg     [3:0]  rand_sel;

  reg    [31:0]  data_max;

begin

// ACCESS TO MAC REGISTERS TEST

test_heading("ACCESS TO MAC REGISTERS TEST");

$display(" ");

$display("ACCESS TO MAC REGISTERS TEST");

fail = 0;

// reset MAC registers

hard_reset;

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  test_access_to_mac_reg:                                     ////

////                                                              ////

////  0: Byte selects on 3 32-bit RW registers.                   ////

////  1: Walking 1 with single cycles across MAC regs.            ////

////  2: Walking 1 with single cycles across MAC buffer descript. ////

////  3: Test max reg. values and reg. values after writing       ////

////     inverse reset values and hard reset of the MAC           ////

////  4: Test buffer desc. RAM preserving values after hard reset ////

////     of the MAC and resetting the logic                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)

begin

  ////////////////////////////////////////////////////////////////////

  ////                                                            ////

  ////  Byte selects on 4 32-bit RW registers.                    ////

  ////                                                            ////

  ////////////////////////////////////////////////////////////////////

  if (test_num == 0) // Walking 1 with single cycles across MAC regs.

  begin

    // TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )

    test_name   = "TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )";

    `TIME; $display("  TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )");

    data = 0;

    rand_sel = 0;

    sel = 0;

    for (i = 1; i <= 3; i = i + 1) // num of active byte selects at each register

    begin

      wbm_init_waits = 0;

      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses

      case (i)

      1:       i_addr = `ETH_MAC_ADDR0;

      2:       i_addr = `ETH_HASH_ADDR0;

      default: i_addr = `ETH_HASH_ADDR1;

      endcase

      addr = `ETH_BASE + i_addr;

      sel = 4'hF;

      wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);

      if (tmp_data !== 32'h0)

      begin

        fail = fail + 1;

        test_fail_num("Register default value is not ZERO", i_addr);

        `TIME;

        $display("Register default value is not ZERO - addr %h, tmp_data %h", addr, tmp_data);

      end

      for (i1 = 0; i1 <= 3; i1 = i1 + 1) // position of first active byte select

      begin

        case ({i, i1})

        10:      sel = 4'b0001; // data = 32'hFFFF_FF00;

        11:      sel = 4'b0010; // data = 32'hFFFF_00FF;

        12:      sel = 4'b0100; // data = 32'hFF00_FFFF;

        13:      sel = 4'b1000; // data = 32'h00FF_FFFF;

        20:      sel = 4'b0011; // data = 32'hFFFF_0000;

        21:      sel = 4'b0110; // data = 32'hFF00_00FF;

        22:      sel = 4'b1100; // data = 32'h0000_FFFF;

        23:      sel = 4'b1001; // data = 32'h00FF_FF00;

        30:      sel = 4'b0111; // data = 32'hFF00_0000;

        31:      sel = 4'b1110; // data = 32'h0000_00FF;

        32:      sel = 4'b1101; // data = 32'h0000_FF00;

        default: sel = 4'b1011; // data = 32'h00FF_0000;

        endcase

        // set value to 32'hFFFF_FFFF

        data = 32'hFFFF_FFFF;

        wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

        wait (wbm_working == 0);

        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

        if (tmp_data !== data)

        begin

          fail = fail + 1;

          test_fail_num("Register could not be written to FFFF_FFFF", i_addr);

          `TIME;

          $display("Register could not be written to FFFF_FFFF - addr %h, tmp_data %h", addr, tmp_data);

        end

        // write appropriate byte(s) to 0

        data = 32'h0;

        wbm_write(addr, data, sel, 1, wbm_init_waits, wbm_subseq_waits);

        wait (wbm_working == 0);

        if (i1[0])

          wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);

        else

          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

        data = {({8{~sel[3]}}), ({8{~sel[2]}}), ({8{~sel[1]}}), ({8{~sel[0]}})};

        if (tmp_data !== data)

        begin

          fail = fail + 1;

          test_fail_num("Wrong data read out form register", i_addr);

          `TIME;

          $display("Wrong data read out from register - addr %h, data %h, tmp_data %h, sel %b",

                   addr, data, tmp_data, sel);

        end

      end

    end

    if(fail == 0)

      test_ok;

    else

      fail = 0;    // Errors were reported previously