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///////////3///////////////////////////////////////////////////////////
////                                                              ////
////  tb_eth_top.v                                                ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2001/10/19 11:24:04  mohor
// Number of addresses (wb_adr_i) minimized.
//
// Revision 1.4  2001/10/19 08:46:53  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3  2001/09/24 14:55:49  mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2  2001/08/15 14:04:30  mohor
// Signal names changed on the top level for easier pad insertion (ASIC).
//
// Revision 1.1  2001/08/06 14:41:09  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:46:09  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
 
 
`include "eth_defines.v"
`include "timescale.v"
 
module tb_eth_top();
 
 
parameter Tp = 1;
 
 
reg           WB_CLK_I;
reg           WB_RST_I;
reg   [31:0]  WB_DAT_I;
 
reg   [31:0]  WB_ADR_I;
reg    [3:0]  WB_SEL_I;
reg           WB_WE_I;
reg           WB_CYC_I;
reg           WB_STB_I;
reg    [1:0]  WB_ACK_I;
 
wire  [31:0]  WB_DAT_O;
wire          WB_ACK_O;
wire          WB_ERR_O;
wire   [1:0]  WB_REQ_O;
wire   [1:0]  WB_ND_O;
wire          WB_RD_O;
 
reg           MTxClk;
wire   [3:0]  MTxD;
wire          MTxEn;
wire          MTxErr;
 
reg           MRxClk;
reg    [3:0]  MRxD;
reg           MRxDV;
reg           MRxErr;
reg           MColl;
reg           MCrs;
 
reg           Mdi_I;
wire          Mdo_O;
wire          Mdo_OE;
wire          Mdc_O;
 
 
 
reg GSR;
 
reg WishboneBusy;
reg StartTB;
reg [9:0] TxBDIndex;
reg [9:0] RxBDIndex;
 
 
 
// Connecting Ethernet top module
 
eth_top ethtop
(
  // WISHBONE common
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
 
  // WISHBONE slave
        .wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
        .wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
        .wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
 
  //TX
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
 
  //RX
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
 
  // MIIM
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
 
  .int_o()
);
 
 
 
 
 
 
 
initial
begin
  WB_CLK_I  =  1'b0;
  WB_DAT_I  = 32'h0;
  WB_ADR_I  = 32'h0;
  WB_SEL_I  =  4'h0;
  WB_WE_I   =  1'b0;
  WB_CYC_I  =  1'b0;
  WB_STB_I  =  1'b0;
  WB_ACK_I  =  2'h0;
  MTxClk    =  1'b0;
  MRxClk    =  1'b0;
  MRxD      =  4'h0;
  MRxDV     =  1'b0;
  MRxErr    =  1'b0;
  MColl     =  1'b0;
  MCrs      =  1'b0;
  Mdi_I     =  1'b0;
 
  WishboneBusy = 1'b0;
  TxBDIndex = 10'h0;
  RxBDIndex = 10'h0;
end
 
 
// Reset pulse
initial
begin
  GSR           =  1'b1;
  WB_RST_I      =  1'b1;
  #100 WB_RST_I =  1'b1;
  GSR           =  1'b1;
  #100 WB_RST_I =  1'b0;
  GSR           =  1'b0;
  #100 StartTB  =  1'b1;
end
 
 
assign glbl.GSR = GSR;
 
 
 
// Generating WB_CLK_I clock
always
begin
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
//  forever #100 WB_CLK_I = ~WB_CLK_I;
end
 
// Generating MTxClk clock
always
begin
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
//  #3 forever #200 MTxClk = ~MTxClk;
end
 
// Generating MRxClk clock
always
begin
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
//  #16 forever #250 MRxClk = ~MRxClk;
end
 
 
 
initial
begin
  wait(StartTB);  // Start of testbench
 
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
 
 
 
 
  SendPacket(16'h0015, 1'b0);
  SendPacket(16'h0043, 1'b1);   // Control frame
  SendPacket(16'h0025, 1'b0);
  SendPacket(16'h0045, 1'b0);
  SendPacket(16'h0025, 1'b0);
 
 
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
 
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
 
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
 
  #10000 $stop;
end
 
 
 
 
 
 
 
task WishboneWrite;
  input [31:0] Data;
  input [31:0] Address;
  integer ii;
 
  begin
    wait (~WishboneBusy);
    WishboneBusy = 1;
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = Address;
    WB_DAT_I = Data;
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
 
//    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
//    begin
//      @ (posedge WB_CLK_I);
//    end
 
//    if(ii==20)
//      begin
//        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)", 
//          Data, Address, $time);
//        #50 $stop;
//      end
 
    wait(WB_ACK_O);   // waiting for acknowledge response
 
    // Writing information about the access to the screen
    @ (posedge WB_CLK_I);
      if(~Address[11] & ~Address[10])
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
      else
      if(~Address[11] & Address[10])
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
          begin
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
            if(Data[9])
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
          end
        else
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
      else
        $write("\nWB write ??????????????     Data: 0x%x      Addr: 0x%0x", Data, Address);
    #1;
    WB_ADR_I = 32'hx;
    WB_DAT_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    #5 WishboneBusy = 0;
  end
endtask
 
 
task WishboneRead;
  input [31:0] Address;
  reg   [31:0] Data;
  integer ii;
 
  begin
    wait (~WishboneBusy);
    WishboneBusy = 1;
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = Address;
    WB_WE_I  = 1'b0;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
 
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
    begin
      @ (posedge WB_CLK_I);
      Data = WB_DAT_O;
    end
 
    if(ii==20)
      begin
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
          Address, $time);
        #50 $stop;
      end
 
    @ (posedge WB_CLK_I);
      if(~Address[11] & ~Address[10])
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
      else
      if(~Address[11] & Address[10])
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
          begin
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
          end
        else
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
      else
        $write("\nWB read  ?????????    Data: 0x%x      Addr: 0x%0x", Data, Address);
    #1;
    WB_ADR_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    #5 WishboneBusy = 0;
  end
endtask
 
 
 
 
task SendPacket;
  input [15:0]  Length;
  input         ControlFrame;
  reg           Wrap;
  reg [31:0]    TempAddr;
  reg [31:0]    TempData;
 
  begin
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
      Wrap = 1'b1;
    else
      Wrap = 1'b0;
 
    TempAddr = {22'h01, (TxBDIndex<<2)};
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
 
    #1;
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
      TxBDIndex = 0;
    else
      TxBDIndex = TxBDIndex + 1;
 
    fork
      begin
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
      end
 
      begin
        if(~ControlFrame)
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
      end
    join
  end
endtask
 
 
 
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  input [15:0] LengthRx;
  input        RxControlFrame;
  reg        WrapRx;
  reg [31:0] TempRxAddr;
  reg [31:0] TempRxData;
  reg abc;
  begin
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
      WrapRx = 1'b1;
    else
      WrapRx = 1'b0;
 
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
 
    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
 
    #1;
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
      RxBDIndex = 0;
    else
      RxBDIndex = RxBDIndex + 1;
 
    abc=1;
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
    abc=0;
    fork
      begin
        #200;
        if(RxControlFrame)
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
        else
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
      end
 
      begin
        if(RxControlFrame)
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
        else
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
      end
    join
  end
endtask
 
 
 
task WaitingForTxDMARequest;
  input [3:0] Delay;
  input [15:0] DMALength;
  integer pp;
  reg [7:0]a, b, c, d;
 
  for(pp=0; pp*4<DMALength; pp=pp+1)
  begin
    a = 4*pp[7:0]+3;
    b = 4*pp[7:0]+2;
    c = 4*pp[7:0]+1;
    d = 4*pp[7:0]  ;
    @ (posedge WB_REQ_O[0]);
    repeat(Delay) @(posedge WB_CLK_I);
 
    wait (~WishboneBusy);
    WishboneBusy = 1;
    #1;
    WB_DAT_I = {a, b, c, d};
//    WB_ADR_I = {20'h20, pp[11:0]};
    WB_ADR_I = {22'h02, pp[9:0]};
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
 
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
    WB_ACK_I[0] = 1'b1;
 
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = 32'hx;
    WB_DAT_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    WB_ACK_I[0] = 1'b0;
    #5 WishboneBusy = 0;
  end
endtask
 
 
task WaitingForRxDMARequest;
  input [3:0] Delay;
  input [15:0] DMALengthRx;
  integer rr;
 
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
  begin
    @ (posedge WB_REQ_O[1]);
    repeat(Delay) @(posedge WB_CLK_I);
 
    wait (~WishboneBusy);
    WishboneBusy = 1;
    #1;
//    WB_ADR_I = {20'h20, rr[11:0]};
    WB_ADR_I = {22'h02, rr[9:0]};
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
 
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
    WB_ACK_I[1] = 1'b1;
 
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    WB_ACK_I[1] = 1'b0;
    #5 WishboneBusy = 0;
  end
endtask
 
 
 
task GetDataOnMRxD;
  input [15:0] Len;
  integer tt;
 
  begin
    @ (posedge MRxClk);
    MRxDV=1'b1;
 
    for(tt=0; tt<15; tt=tt+1)
    begin
      MRxD=4'h5;              // preamble
      @ (posedge MRxClk);
    end
    MRxD=4'hd;                // SFD
 
    for(tt=0; tt<Len; tt=tt+1)
    begin
      @ (posedge MRxClk);
      MRxD=tt[3:0];
      @ (posedge MRxClk);
      MRxD=tt[7:4];
    end
    @ (posedge MRxClk);
    MRxDV=1'b0;
  end
endtask
 
 
task GetControlDataOnMRxD;
  input [15:0] Timer;
  reg [127:0] Packet;
  reg [127:0] Data;
  reg [31:0] Crc;
  integer tt;
 
  begin
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
  Crc = 32'h6014fe08; // not a correct value
 
    @ (posedge MRxClk);
    MRxDV=1'b1;
 
    for(tt=0; tt<15; tt=tt+1)
    begin
      MRxD=4'h5;              // preamble
      @ (posedge MRxClk);
    end
    MRxD=4'hd;                // SFD
 
    for(tt=0; tt<32; tt=tt+1)
    begin
      Data = Packet << (tt*4);
      @ (posedge MRxClk);
      MRxD=Data[127:124];
    end
 
    for(tt=0; tt<2; tt=tt+1)    // timer
    begin
      Data[15:0] = Timer << (tt*8);
      @ (posedge MRxClk);
      MRxD=Data[11:8];
      @ (posedge MRxClk);
      MRxD=Data[15:12];
    end
 
    for(tt=0; tt<42; tt=tt+1)   // padding
    begin
      Data[7:0] = 8'h0;
      @ (posedge MRxClk);
      MRxD=Data[3:0];
      @ (posedge MRxClk);
      MRxD=Data[3:0];
    end
 
    for(tt=0; tt<4; tt=tt+1)    // crc
    begin
      Data[31:0] = Crc << (tt*8);
      @ (posedge MRxClk);
      MRxD=Data[27:24];
      @ (posedge MRxClk);
      MRxD=Data[31:28];
    end
 
 
 
    @ (posedge MRxClk);
    MRxDV=1'b0;
  end
endtask
 
 
 
endmodule

Line No.	Rev	Author	Line
1	22	mohor	`///////////3///////////////////////////////////////////////////////////`
2	15	mohor	`//// ////`
3			`//// tb_eth_top.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	36	mohor	`// Revision 1.5 2001/10/19 11:24:04 mohor`
45			`// Number of addresses (wb_adr_i) minimized.`
46			`//`
47	23	mohor	`// Revision 1.4 2001/10/19 08:46:53 mohor`
48			`// eth_timescale.v changed to timescale.v This is done because of the`
49			`// simulation of the few cores in a one joined project.`
50			`//`
51	22	mohor	`// Revision 1.3 2001/09/24 14:55:49 mohor`
52			`// Defines changed (All precede with ETH_). Small changes because some`
53			`// tools generate warnings when two operands are together. Synchronization`
54			`// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC`
55			`// demands).`
56			`//`
57	19	mohor	`// Revision 1.2 2001/08/15 14:04:30 mohor`
58			`// Signal names changed on the top level for easier pad insertion (ASIC).`
59			`//`
60	17	mohor	`// Revision 1.1 2001/08/06 14:41:09 mohor`
61			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
62			`// Include files fixed to contain no path.`
63			`// File names and module names changed ta have a eth_ prologue in the name.`
64			`// File eth_timescale.v is used to define timescale`
65			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
66			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
67			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
68			`// is done due to the ASIC tools.`
69			`//`
70	15	mohor	`// Revision 1.1 2001/07/30 21:46:09 mohor`
71			`// Directory structure changed. Files checked and joind together.`
72			`//`
73			`//`
74			`//`
75			`//`
76			`//`
77
78
79
80			`include "eth_defines.v"
81	22	mohor	`include "timescale.v"
82	15	mohor
83			`module tb_eth_top();`
84
85
86			`parameter Tp = 1;`
87
88
89			`reg WB_CLK_I;`
90			`reg WB_RST_I;`
91			`reg [31:0] WB_DAT_I;`
92
93			`reg [31:0] WB_ADR_I;`
94			`reg [3:0] WB_SEL_I;`
95			`reg WB_WE_I;`
96			`reg WB_CYC_I;`
97			`reg WB_STB_I;`
98			`reg [1:0] WB_ACK_I;`
99
100			`wire [31:0] WB_DAT_O;`
101			`wire WB_ACK_O;`
102			`wire WB_ERR_O;`
103			`wire [1:0] WB_REQ_O;`
104			`wire [1:0] WB_ND_O;`
105			`wire WB_RD_O;`
106
107			`reg MTxClk;`
108			`wire [3:0] MTxD;`
109			`wire MTxEn;`
110			`wire MTxErr;`
111
112			`reg MRxClk;`
113			`reg [3:0] MRxD;`
114			`reg MRxDV;`
115			`reg MRxErr;`
116			`reg MColl;`
117			`reg MCrs;`
118
119			`reg Mdi_I;`
120			`wire Mdo_O;`
121			`wire Mdo_OE;`
122			`wire Mdc_O;`
123
124
125
126			`reg GSR;`
127
128			`reg WishboneBusy;`
129			`reg StartTB;`
130			`reg [9:0] TxBDIndex;`
131			`reg [9:0] RxBDIndex;`
132
133
134
135			`// Connecting Ethernet top module`
136
137			`eth_top ethtop`
138			`(`
139			`// WISHBONE common`
140	17	mohor	`.wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),`
141	15	mohor
142			`// WISHBONE slave`
143	23	mohor	`.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),`
144	17	mohor	`.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),`
145			`.wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),`
146	15	mohor
147			`//TX`
148	19	mohor	`.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),`
149	15	mohor
150			`//RX`
151	19	mohor	`.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),`
152	17	mohor	`.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),`
153	15	mohor
154			`// MIIM`
155	22	mohor	`.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),`
156
157			`.int_o()`
158	15	mohor	`);`
159
160
161
162
163
164
165
166			`initial`
167			`begin`
168			`WB_CLK_I = 1'b0;`
169	19	mohor	`WB_DAT_I = 32'h0;`
170			`WB_ADR_I = 32'h0;`
171			`WB_SEL_I = 4'h0;`
172			`WB_WE_I = 1'b0;`
173	15	mohor	`WB_CYC_I = 1'b0;`
174			`WB_STB_I = 1'b0;`
175			`WB_ACK_I = 2'h0;`
176			`MTxClk = 1'b0;`
177			`MRxClk = 1'b0;`
178			`MRxD = 4'h0;`
179			`MRxDV = 1'b0;`
180			`MRxErr = 1'b0;`
181			`MColl = 1'b0;`
182			`MCrs = 1'b0;`
183			`Mdi_I = 1'b0;`
184
185			`WishboneBusy = 1'b0;`
186			`TxBDIndex = 10'h0;`
187			`RxBDIndex = 10'h0;`
188			`end`
189
190
191			`// Reset pulse`
192			`initial`
193			`begin`
194	19	mohor	`GSR = 1'b1;`
195			`WB_RST_I = 1'b1;`
196	15	mohor	`#100 WB_RST_I = 1'b1;`
197			`GSR = 1'b1;`
198			`#100 WB_RST_I = 1'b0;`
199			`GSR = 1'b0;`
200			`#100 StartTB = 1'b1;`
201			`end`
202
203
204			`assign glbl.GSR = GSR;`
205
206
207
208			`// Generating WB_CLK_I clock`
209			`always`
210			`begin`
211	19	mohor	`// forever #5 WB_CLK_I = ~WB_CLK_I; // 2*5 ns -> 100.0 MHz`
212	15	mohor	`// forever #10 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 50.0 MHz`
213			`forever #15 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 33.3 MHz`
214			`// forever #18 WB_CLK_I = ~WB_CLK_I; // 2*18 ns -> 27.7 MHz`
215			`// forever #100 WB_CLK_I = ~WB_CLK_I;`
216			`end`
217
218			`// Generating MTxClk clock`
219			`always`
220			`begin`
221			`#3 forever #20 MTxClk = ~MTxClk; // 2*20 ns -> 25 MHz`
222			`// #3 forever #200 MTxClk = ~MTxClk;`
223			`end`
224
225			`// Generating MRxClk clock`
226			`always`
227			`begin`
228			`#16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz`
229			`// #16 forever #250 MRxClk = ~MRxClk;`
230			`end`
231
232
233
234			`initial`
235			`begin`
236			`wait(StartTB); // Start of testbench`
237
238	22	mohor	WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
239			WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
240	36	mohor	WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
241	22	mohor	WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
242			WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
243	15	mohor
244
245
246
247			`SendPacket(16'h0015, 1'b0);`
248			`SendPacket(16'h0043, 1'b1); // Control frame`
249			`SendPacket(16'h0025, 1'b0);`
250			`SendPacket(16'h0045, 1'b0);`
251			`SendPacket(16'h0025, 1'b0);`
252
253
254			`ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.`
255			`ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
256			`ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
257			`ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
258			`ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
259
260
261	22	mohor	WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
262	15	mohor
263	23	mohor	`WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register`
264			`WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register`
265			`WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register`
266			`WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register`
267			`WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register`
268	15	mohor
269	23	mohor	`WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register`
270			`WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register`
271			`WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register`
272			`WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register`
273			`WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register`
274	15	mohor
275			`#10000 $stop;`
276			`end`
277
278
279
280
281
282
283
284			`task WishboneWrite;`
285			`input [31:0] Data;`
286			`input [31:0] Address;`
287			`integer ii;`
288
289			`begin`
290			`wait (~WishboneBusy);`
291			`WishboneBusy = 1;`
292			`@ (posedge WB_CLK_I);`
293			`#1;`
294			`WB_ADR_I = Address;`
295			`WB_DAT_I = Data;`
296			`WB_WE_I = 1'b1;`
297			`WB_CYC_I = 1'b1;`
298			`WB_STB_I = 1'b1;`
299			`WB_SEL_I = 4'hf;`
300
301	19	mohor	`// for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles`
302			`// begin`
303			`// @ (posedge WB_CLK_I);`
304			`// end`
305	15	mohor
306	19	mohor	`// if(ii==20)`
307			`// begin`
308			`// $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",`
309			`// Data, Address, $time);`
310			`// #50 $stop;`
311			`// end`
312	15	mohor
313	19	mohor	`wait(WB_ACK_O); // waiting for acknowledge response`
314
315			`// Writing information about the access to the screen`
316	15	mohor	`@ (posedge WB_CLK_I);`
317	23	mohor	`if(~Address[11] & ~Address[10])`
318	22	mohor	`$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);`
319	15	mohor	`else`
320	23	mohor	`if(~Address[11] & Address[10])`
321	36	mohor	`if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)`
322	15	mohor	`begin`
323	22	mohor	`$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);`
324	23	mohor	`if(Data[9])`
325	15	mohor	`$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);`
326			`end`
327			`else`
328	22	mohor	`$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);`
329	15	mohor	`else`
330	22	mohor	`$write("\nWB write ?????????????? Data: 0x%x Addr: 0x%0x", Data, Address);`
331	15	mohor	`#1;`
332			`WB_ADR_I = 32'hx;`
333			`WB_DAT_I = 32'hx;`
334			`WB_WE_I = 1'bx;`
335			`WB_CYC_I = 1'b0;`
336			`WB_STB_I = 1'b0;`
337			`WB_SEL_I = 4'hx;`
338			`#5 WishboneBusy = 0;`
339			`end`
340			`endtask`
341
342
343			`task WishboneRead;`
344			`input [31:0] Address;`
345			`reg [31:0] Data;`
346			`integer ii;`
347
348			`begin`
349			`wait (~WishboneBusy);`
350			`WishboneBusy = 1;`
351			`@ (posedge WB_CLK_I);`
352			`#1;`
353			`WB_ADR_I = Address;`
354			`WB_WE_I = 1'b0;`
355			`WB_CYC_I = 1'b1;`
356			`WB_STB_I = 1'b1;`
357			`WB_SEL_I = 4'hf;`
358
359			`for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles`
360			`begin`
361			`@ (posedge WB_CLK_I);`
362			`Data = WB_DAT_O;`
363			`end`
364
365			`if(ii==20)`
366			`begin`
367			`$display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",`
368			`Address, $time);`
369			`#50 $stop;`
370			`end`
371
372			`@ (posedge WB_CLK_I);`
373	23	mohor	`if(~Address[11] & ~Address[10])`
374	22	mohor	`$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);`
375	15	mohor	`else`
376	23	mohor	`if(~Address[11] & Address[10])`
377	36	mohor	`if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)`
378	15	mohor	`begin`
379	22	mohor	`$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);`
380	15	mohor	`end`
381			`else`
382	22	mohor	`$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);`
383	15	mohor	`else`
384	22	mohor	`$write("\nWB read ????????? Data: 0x%x Addr: 0x%0x", Data, Address);`
385	15	mohor	`#1;`
386			`WB_ADR_I = 32'hx;`
387			`WB_WE_I = 1'bx;`
388			`WB_CYC_I = 1'b0;`
389			`WB_STB_I = 1'b0;`
390			`WB_SEL_I = 4'hx;`
391			`#5 WishboneBusy = 0;`
392			`end`
393			`endtask`
394
395
396
397
398			`task SendPacket;`
399			`input [15:0] Length;`
400			`input ControlFrame;`
401			`reg Wrap;`
402			`reg [31:0] TempAddr;`
403			`reg [31:0] TempData;`
404
405			`begin`
406			`if(TxBDIndex == 3) // Only 4 buffer descriptors are used`
407			`Wrap = 1'b1;`
408			`else`
409			`Wrap = 1'b0;`
410
411	23	mohor	`TempAddr = {22'h01, (TxBDIndex<<2)};`
412	22	mohor	`TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1`
413	15	mohor
414			`#1;`
415			`if(TxBDIndex == 3) // Only 4 buffer descriptors are used`
416			`TxBDIndex = 0;`
417			`else`
418			`TxBDIndex = TxBDIndex + 1;`
419
420			`fork`
421			`begin`
422			`WishboneWrite(TempData, TempAddr); // Writing status to TxBD`
423			`end`
424
425			`begin`
426			`if(~ControlFrame)`
427			`WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength`
428			`end`
429			`join`
430			`end`
431			`endtask`
432
433
434
435			`task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
436			`input [15:0] LengthRx;`
437			`input RxControlFrame;`
438			`reg WrapRx;`
439			`reg [31:0] TempRxAddr;`
440			`reg [31:0] TempRxData;`
441			`reg abc;`
442			`begin`
443			`if(RxBDIndex == 3) // Only 4 buffer descriptors are used`
444			`WrapRx = 1'b1;`
445			`else`
446			`WrapRx = 1'b0;`
447
448	36	mohor	`TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};`
449	15	mohor
450	22	mohor	`TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0`
451	15	mohor
452			`#1;`
453			`if(RxBDIndex == 3) // Only 4 buffer descriptors are used`
454			`RxBDIndex = 0;`
455			`else`
456			`RxBDIndex = RxBDIndex + 1;`
457
458			`abc=1;`
459			`WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD`
460			`abc=0;`
461			`fork`
462			`begin`
463			`#200;`
464			`if(RxControlFrame)`
465			`GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.`
466			`else`
467			`GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals`
468			`end`
469
470			`begin`
471			`if(RxControlFrame)`
472			`WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.`
473			`else`
474			`WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength`
475			`end`
476			`join`
477			`end`
478			`endtask`
479
480
481
482			`task WaitingForTxDMARequest;`
483			`input [3:0] Delay;`
484			`input [15:0] DMALength;`
485			`integer pp;`
486			`reg [7:0]a, b, c, d;`
487
488			`for(pp=0; pp*4<DMALength; pp=pp+1)`
489			`begin`
490			`a = 4*pp[7:0]+3;`
491			`b = 4*pp[7:0]+2;`
492			`c = 4*pp[7:0]+1;`
493			`d = 4*pp[7:0] ;`
494			`@ (posedge WB_REQ_O[0]);`
495			`repeat(Delay) @(posedge WB_CLK_I);`
496
497			`wait (~WishboneBusy);`
498			`WishboneBusy = 1;`
499			`#1;`
500			`WB_DAT_I = {a, b, c, d};`

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