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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_transmitcontrol.v                                       ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1  2001/07/03 12:51:54  mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
 
 
`include "eth_timescale.v"
 
 
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
                            TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
                            TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
                            ControlData, WillSendControlFrame
                           );
 
parameter Tp = 1;
 
 
input         MTxClk;
input         TxReset;
input         TxUsedDataIn;
input         TxUsedDataOut;
input         TxDoneIn;
input         TxAbortIn;
input         TxStartFrmIn;
input         TPauseRq;
input         TxUsedDataOutDetected;
input         TxFlow;
input         DlyCrcEn;
input  [15:0] TxPauseTV;
input  [47:0] MAC;
 
output        TxCtrlStartFrm;
output        TxCtrlEndFrm;
output        SendingCtrlFrm;
output        CtrlMux;
output [7:0]  ControlData;
output        WillSendControlFrame;
 
reg           SendingCtrlFrm;
reg           CtrlMux;
reg           WillSendControlFrame;
reg    [3:0]  DlyCrcCnt;
reg    [5:0]  ByteCnt;
reg           ControlEnd_q;
reg    [7:0]  MuxedCtrlData;
reg           TxCtrlStartFrm;
reg           TxCtrlStartFrm_q;
reg           TxCtrlEndFrm;
reg    [7:0]  ControlData;
reg           TxUsedDataIn_q;
 
wire          IncrementDlyCrcCnt;
wire          ResetByteCnt;
wire          IncrementByteCnt;
wire          ControlEnd;
 
 
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    WillSendControlFrame <= #Tp 1'b0;
  else
  if(TxCtrlEndFrm & CtrlMux)
    WillSendControlFrame <= #Tp 1'b0;
  else
  if(TPauseRq & TxFlow)
    WillSendControlFrame <= #Tp 1'b1;
end
 
 
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxCtrlStartFrm <= #Tp 1'b0;
  else
  if(TxUsedDataIn_q & CtrlMux)
    TxCtrlStartFrm <= #Tp 1'b0;
  else
  if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | ~TxUsedDataOutDetected))
    TxCtrlStartFrm <= #Tp 1'b1;
end
 
 
 
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxCtrlEndFrm <= #Tp 1'b0;
  else
  if(ControlEnd | ControlEnd_q)
    TxCtrlEndFrm <= #Tp 1'b1;
  else
    TxCtrlEndFrm <= #Tp 1'b0;
end
 
 
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    CtrlMux <= #Tp 1'b0;
  else
  if(WillSendControlFrame & ~TxUsedDataOut)
    CtrlMux <= #Tp 1'b1;
  else
  if(TxDoneIn)
    CtrlMux <= #Tp 1'b0;
end
 
 
 
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    SendingCtrlFrm <= #Tp 1'b0;
  else
  if(WillSendControlFrame & TxCtrlStartFrm)
    SendingCtrlFrm <= #Tp 1'b1;
  else
  if(TxDoneIn)
    SendingCtrlFrm <= #Tp 1'b0;
end
 
 
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxUsedDataIn_q <= #Tp 1'b0;
  else
    TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
 
 
always @ (posedge MTxClk)
begin
  ControlEnd_q     <= #Tp ControlEnd;
  TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
 
 
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
 
 
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    DlyCrcCnt <= #Tp 4'h0;
  else
  if(ResetByteCnt)
    DlyCrcCnt <= #Tp 4'h0;
  else
  if(IncrementDlyCrcCnt)
    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
 
 
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
 
 
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    ByteCnt <= #Tp 6'h0;
  else
  if(ResetByteCnt)
    ByteCnt <= #Tp 6'h0;
  else
  if(IncrementByteCnt & (~DlyCrcEn | DlyCrcEn & &DlyCrcCnt[1:0]))
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
 
 
assign ControlEnd = ByteCnt[5:0] == 6'h22;
 
 
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
  case(ByteCnt)
    6'h0:    if(~DlyCrcEn | DlyCrcEn & &DlyCrcCnt[1:0])
               MuxedCtrlData[7:0] = 8'h01;                   // Reserved Multicast Address
             else
                                                         MuxedCtrlData[7:0] = 8'h0;
    6'h2:      MuxedCtrlData[7:0] = 8'h80;
    6'h4:      MuxedCtrlData[7:0] = 8'hC2;
    6'h6:      MuxedCtrlData[7:0] = 8'h00;
    6'h8:      MuxedCtrlData[7:0] = 8'h00;
    6'hA:      MuxedCtrlData[7:0] = 8'h01;
    6'hC:      MuxedCtrlData[7:0] = MAC[47:40];
    6'hE:      MuxedCtrlData[7:0] = MAC[39:32];
    6'h10:     MuxedCtrlData[7:0] = MAC[31:24];
    6'h12:     MuxedCtrlData[7:0] = MAC[23:16];
    6'h14:     MuxedCtrlData[7:0] = MAC[15:8];
    6'h16:     MuxedCtrlData[7:0] = MAC[7:0];
    6'h18:     MuxedCtrlData[7:0] = 8'h88;                   // Type/Length
    6'h1A:     MuxedCtrlData[7:0] = 8'h08;
    6'h1C:     MuxedCtrlData[7:0] = 8'h00;                   // Opcode
    6'h1E:     MuxedCtrlData[7:0] = 8'h01;
    6'h20:     MuxedCtrlData[7:0] = TxPauseTV[15:8];         // Pause timer value
    6'h22:     MuxedCtrlData[7:0] = TxPauseTV[7:0];
    default:   MuxedCtrlData[7:0] = 8'h0;
  endcase
end
 
 
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    ControlData[7:0] <= #Tp 8'h0;
  else
  if(~ByteCnt[0])
    ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
 
 
 
endmodule

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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_transmitcontrol.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.1 2001/07/30 21:23:42 mohor`
45			`// Directory structure changed. Files checked and joind together.`
46			`//`
47			`// Revision 1.1 2001/07/03 12:51:54 mohor`
48			`// Initial release of the MAC Control module.`
49			`//`
50			`//`
51			`//`
52			`//`
53			`//`
54			`//`
55
56
57			`include "eth_timescale.v"
58
59
60			`module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,`
61			`TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,`
62			`TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,`
63			`ControlData, WillSendControlFrame`
64			`);`
65
66			`parameter Tp = 1;`
67
68
69			`input MTxClk;`
70			`input TxReset;`
71			`input TxUsedDataIn;`
72			`input TxUsedDataOut;`
73			`input TxDoneIn;`
74			`input TxAbortIn;`
75			`input TxStartFrmIn;`
76			`input TPauseRq;`
77			`input TxUsedDataOutDetected;`
78			`input TxFlow;`
79			`input DlyCrcEn;`
80			`input [15:0] TxPauseTV;`
81			`input [47:0] MAC;`
82
83			`output TxCtrlStartFrm;`
84			`output TxCtrlEndFrm;`
85			`output SendingCtrlFrm;`
86			`output CtrlMux;`
87			`output [7:0] ControlData;`
88			`output WillSendControlFrame;`
89
90			`reg SendingCtrlFrm;`
91			`reg CtrlMux;`
92			`reg WillSendControlFrame;`
93			`reg [3:0] DlyCrcCnt;`
94			`reg [5:0] ByteCnt;`
95			`reg ControlEnd_q;`
96			`reg [7:0] MuxedCtrlData;`
97			`reg TxCtrlStartFrm;`
98			`reg TxCtrlStartFrm_q;`
99			`reg TxCtrlEndFrm;`
100			`reg [7:0] ControlData;`
101			`reg TxUsedDataIn_q;`
102
103			`wire IncrementDlyCrcCnt;`
104			`wire ResetByteCnt;`
105			`wire IncrementByteCnt;`
106			`wire ControlEnd;`
107
108
109			`// A command for Sending the control frame is active (latched)`
110			`always @ (posedge MTxClk or posedge TxReset)`
111			`begin`
112			`if(TxReset)`
113			`WillSendControlFrame <= #Tp 1'b0;`
114			`else`
115			`if(TxCtrlEndFrm & CtrlMux)`
116			`WillSendControlFrame <= #Tp 1'b0;`
117			`else`
118			`if(TPauseRq & TxFlow)`
119			`WillSendControlFrame <= #Tp 1'b1;`
120			`end`
121
122
123			`// Generation of the transmit control packet start frame`
124			`always @ (posedge MTxClk or posedge TxReset)`
125			`begin`
126			`if(TxReset)`
127			`TxCtrlStartFrm <= #Tp 1'b0;`
128			`else`
129			`if(TxUsedDataIn_q & CtrlMux)`
130			`TxCtrlStartFrm <= #Tp 1'b0;`
131			`else`
132			`if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn \| TxAbortIn \| TxStartFrmIn \| ~TxUsedDataOutDetected))`
133			`TxCtrlStartFrm <= #Tp 1'b1;`
134			`end`
135
136
137
138			`// Generation of the transmit control packet end frame`
139			`always @ (posedge MTxClk or posedge TxReset)`
140			`begin`
141			`if(TxReset)`
142			`TxCtrlEndFrm <= #Tp 1'b0;`
143			`else`
144			`if(ControlEnd \| ControlEnd_q)`
145			`TxCtrlEndFrm <= #Tp 1'b1;`
146			`else`
147			`TxCtrlEndFrm <= #Tp 1'b0;`
148			`end`
149
150
151			`// Generation of the multiplexer signal (controls muxes for switching between`
152			`// normal and control packets)`
153			`always @ (posedge MTxClk or posedge TxReset)`
154			`begin`
155			`if(TxReset)`
156			`CtrlMux <= #Tp 1'b0;`
157			`else`
158			`if(WillSendControlFrame & ~TxUsedDataOut)`
159			`CtrlMux <= #Tp 1'b1;`
160			`else`
161			`if(TxDoneIn)`
162			`CtrlMux <= #Tp 1'b0;`
163			`end`
164
165
166
167			`// Generation of the Sending Control Frame signal (enables padding and CRC)`
168			`always @ (posedge MTxClk or posedge TxReset)`
169			`begin`
170			`if(TxReset)`
171			`SendingCtrlFrm <= #Tp 1'b0;`
172			`else`
173			`if(WillSendControlFrame & TxCtrlStartFrm)`
174			`SendingCtrlFrm <= #Tp 1'b1;`
175			`else`
176			`if(TxDoneIn)`
177			`SendingCtrlFrm <= #Tp 1'b0;`
178			`end`
179
180
181			`always @ (posedge MTxClk or posedge TxReset)`
182			`begin`
183			`if(TxReset)`
184			`TxUsedDataIn_q <= #Tp 1'b0;`
185			`else`
186			`TxUsedDataIn_q <= #Tp TxUsedDataIn;`
187			`end`
188
189
190			`always @ (posedge MTxClk)`
191			`begin`
192			`ControlEnd_q <= #Tp ControlEnd;`
193			`TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;`
194			`end`
195
196
197			`assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];`
198
199
200			`// Delayed CRC counter`
201			`always @ (posedge MTxClk or posedge TxReset)`
202			`begin`
203			`if(TxReset)`
204			`DlyCrcCnt <= #Tp 4'h0;`
205			`else`
206			`if(ResetByteCnt)`
207			`DlyCrcCnt <= #Tp 4'h0;`
208			`else`
209			`if(IncrementDlyCrcCnt)`
210			`DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;`
211			`end`
212
213
214			`assign ResetByteCnt = TxReset \| (~TxCtrlStartFrm & (TxDoneIn \| TxAbortIn));`
215			`assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn \| TxUsedDataIn & ~ControlEnd);`
216
217
218			`// Byte counter`
219			`always @ (posedge MTxClk or posedge TxReset)`
220			`begin`
221			`if(TxReset)`
222			`ByteCnt <= #Tp 6'h0;`
223			`else`
224			`if(ResetByteCnt)`
225			`ByteCnt <= #Tp 6'h0;`
226			`else`
227			`if(IncrementByteCnt & (~DlyCrcEn \| DlyCrcEn & &DlyCrcCnt[1:0]))`
228			`ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;`
229			`end`
230
231
232			`assign ControlEnd = ByteCnt[5:0] == 6'h22;`
233
234
235			`// Control data generation (goes to the TxEthMAC module)`
236			`always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)`
237			`begin`
238			`case(ByteCnt)`
239			`6'h0: if(~DlyCrcEn \| DlyCrcEn & &DlyCrcCnt[1:0])`
240			`MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address`
241			`else`
242			`MuxedCtrlData[7:0] = 8'h0;`
243			`6'h2: MuxedCtrlData[7:0] = 8'h80;`
244			`6'h4: MuxedCtrlData[7:0] = 8'hC2;`
245			`6'h6: MuxedCtrlData[7:0] = 8'h00;`
246			`6'h8: MuxedCtrlData[7:0] = 8'h00;`
247			`6'hA: MuxedCtrlData[7:0] = 8'h01;`
248			`6'hC: MuxedCtrlData[7:0] = MAC[47:40];`
249			`6'hE: MuxedCtrlData[7:0] = MAC[39:32];`
250			`6'h10: MuxedCtrlData[7:0] = MAC[31:24];`
251			`6'h12: MuxedCtrlData[7:0] = MAC[23:16];`
252			`6'h14: MuxedCtrlData[7:0] = MAC[15:8];`
253			`6'h16: MuxedCtrlData[7:0] = MAC[7:0];`
254			`6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length`
255			`6'h1A: MuxedCtrlData[7:0] = 8'h08;`
256			`6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode`
257			`6'h1E: MuxedCtrlData[7:0] = 8'h01;`
258			`6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value`
259			`6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];`
260			`default: MuxedCtrlData[7:0] = 8'h0;`
261			`endcase`
262			`end`
263
264
265			`// Latched Control data`
266			`always @ (posedge MTxClk or posedge TxReset)`
267			`begin`
268			`if(TxReset)`
269			`ControlData[7:0] <= #Tp 8'h0;`
270			`else`
271			`if(~ByteCnt[0])`
272			`ControlData[7:0] <= #Tp MuxedCtrlData[7:0];`
273			`end`
274
275
276
277			`endmodule`