URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_8/] [rtl/] [verilog/] [eth_macstatus.v] - Blame information for rev 338

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_macstatus.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2002/09/04 18:38:03  mohor
// CarrierSenseLost status is not set when working in loopback mode.
//
// Revision 1.10  2002/07/25 18:17:46  mohor
// InvalidSymbol generation changed.
//
// Revision 1.9  2002/04/22 13:51:44  mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8  2002/02/18 10:40:17  mohor
// Small fixes.
//
// Revision 1.7  2002/02/15 17:07:39  mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6  2002/02/11 09:18:21  mohor
// Tx status is written back to the BD.
//
// Revision 1.5  2002/02/08 16:21:54  mohor
// Rx status is written back to the BD.
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
`include "timescale.v"
 
 
module eth_macstatus(
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
                      RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,
                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
                      r_FullD
                    );
 
 
 
parameter Tp = 1;
 
 
input         MRxClk;
input         Reset;
input         RxCrcError;
input         MRxErr;
input         MRxDV;
 
input         RxStateSFD;
input   [1:0] RxStateData;
input         RxStatePreamble;
input         RxStateIdle;
input         Transmitting;
input  [15:0] RxByteCnt;
input         RxByteCntEq0;
input         RxByteCntGreat2;
input         RxByteCntMaxFrame;
input         ReceivedPauseFrm;
input   [3:0] MRxD;
input         Collision;
input   [5:0] CollValid;
input         r_RecSmall;
input  [15:0] r_MinFL;
input  [15:0] r_MaxFL;
input         r_HugEn;
input         StartTxDone;
input         StartTxAbort;
input   [3:0] RetryCnt;
input         MTxClk;
input         MaxCollisionOccured;
input         LateCollision;
input         StartDefer;
input         TxStartFrm;
input         StatePreamble;
input   [1:0] StateData;
input         CarrierSense;
input         TxUsedData;
input         Loopback;
input         r_FullD;
 
 
output        ReceivedLengthOK;
output        ReceiveEnd;
output        ReceivedPacketGood;
output        InvalidSymbol;
output        LatchedCrcError;
output        RxLateCollision;
output        ShortFrame;
output        DribbleNibble;
output        ReceivedPacketTooBig;
output        LoadRxStatus;
output  [3:0] RetryCntLatched;
output        RetryLimit;
output        LateCollLatched;
output        DeferLatched;
output        CarrierSenseLost;
output        LatchedMRxErr;
 
 
reg           ReceiveEnd;
 
reg           LatchedCrcError;
reg           LatchedMRxErr;
reg           LoadRxStatus;
reg           InvalidSymbol;
reg     [3:0] RetryCntLatched;
reg           RetryLimit;
reg           LateCollLatched;
reg           DeferLatched;
reg           CarrierSenseLost;
 
wire          TakeSample;
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
 
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateSFD)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateData[0])
    LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
 
 
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedMRxErr <=#Tp 1'b0;
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
    LatchedMRxErr <=#Tp 1'b1;
  else
    LatchedMRxErr <=#Tp 1'b0;
end
 
 
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
 
 
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
 
 
 
 
 
// Time to take a sample
assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
                     RxStateData[0]  &  MRxDV & RxByteCntMaxFrame;
 
 
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LoadRxStatus <=#Tp 1'b0;
  else
    LoadRxStatus <=#Tp TakeSample;
end
 
 
 
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceiveEnd  <=#Tp 1'b0;
  else
    ReceiveEnd  <=#Tp LoadRxStatus;
end
 
 
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
 
 
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(LoadRxStatus & ~SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b1;
end
 
 
// Late Collision
 
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxLateCollision <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    RxLateCollision <=#Tp 1'b0;
  else
  if(Collision & (~RxColWindow | r_RecSmall))
    RxLateCollision <=#Tp 1'b1;
end
 
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxColWindow <=#Tp 1'b1;
  else
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
    RxColWindow <=#Tp 1'b0;
  else
  if(RxStateIdle)
    RxColWindow <=#Tp 1'b1;
end
 
 
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShortFrame <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ShortFrame <=#Tp 1'b0;
  else
  if(TakeSample)
    ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
 
 
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    DribbleNibble <=#Tp 1'b0;
  else
  if(RxStateSFD)
    DribbleNibble <=#Tp 1'b0;
  else
  if(~MRxDV & RxStateData[1])
    DribbleNibble <=#Tp 1'b1;
end
 
 
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(TakeSample)
    ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
 
 
 
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryCntLatched <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryCntLatched <=#Tp RetryCnt;
end
 
 
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryLimit <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryLimit <=#Tp MaxCollisionOccured;
end
 
 
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    LateCollLatched <=#Tp 1'b0;
  else
  if(StartTxDone | StartTxAbort)
    LateCollLatched <=#Tp LateCollision;
end
 
 
 
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    DeferLatched <=#Tp 1'b0;
  else
  if(StartDefer & TxUsedData)
    DeferLatched <=#Tp 1'b1;
  else
  if(TxStartFrm)
    DeferLatched <=#Tp 1'b0;
end
 
 
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    CarrierSenseLost <=#Tp 1'b0;
  else
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
    CarrierSenseLost <=#Tp 1'b1;
  else
  if(TxStartFrm)
    CarrierSenseLost <=#Tp 1'b0;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_macstatus.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11	168	mohor	`//// All additional information is available in the Readme.txt ////`
12	15	mohor	`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16	168	mohor	`//// Copyright (C) 2001, 2002 Authors ////`
17	15	mohor	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	168	mohor	`// Revision 1.11 2002/09/04 18:38:03 mohor`
45			`// CarrierSenseLost status is not set when working in loopback mode.`
46			`//`
47	146	mohor	`// Revision 1.10 2002/07/25 18:17:46 mohor`
48			`// InvalidSymbol generation changed.`
49			`//`
50	126	mohor	`// Revision 1.9 2002/04/22 13:51:44 mohor`
51			`// Short frame and ReceivedLengthOK were not detected correctly.`
52			`//`
53	101	mohor	`// Revision 1.8 2002/02/18 10:40:17 mohor`
54			`// Small fixes.`
55			`//`
56	70	mohor	`// Revision 1.7 2002/02/15 17:07:39 mohor`
57			`// Status was not written correctly when frames were discarted because of`
58			`// address mismatch.`
59			`//`
60	64	mohor	`// Revision 1.6 2002/02/11 09:18:21 mohor`
61			`// Tx status is written back to the BD.`
62			`//`
63	43	mohor	`// Revision 1.5 2002/02/08 16:21:54 mohor`
64			`// Rx status is written back to the BD.`
65			`//`
66	42	mohor	`// Revision 1.4 2002/01/23 10:28:16 mohor`
67			`// Link in the header changed.`
68			`//`
69	37	mohor	`// Revision 1.3 2001/10/19 08:43:51 mohor`
70			`// eth_timescale.v changed to timescale.v This is done because of the`
71			`// simulation of the few cores in a one joined project.`
72			`//`
73	22	mohor	`// Revision 1.2 2001/09/11 14:17:00 mohor`
74			`// Few little NCSIM warnings fixed.`
75			`//`
76	18	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
77			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
78			`// Include files fixed to contain no path.`
79			`// File names and module names changed ta have a eth_ prologue in the name.`
80			`// File eth_timescale.v is used to define timescale`
81			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
82			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
83			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
84			`// is done due to the ASIC tools.`
85			`//`
86	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
87			`// Directory structure changed. Files checked and joind together.`
88			`//`
89			`//`
90			`//`
91			`//`
92			`//`
93
94	22	mohor	`include "timescale.v"
95	15	mohor
96
97			`module eth_macstatus(`
98	42	mohor	`MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,`
99	15	mohor	`MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,`
100	42	mohor	`RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,`
101			`InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,`
102			`r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,`
103	43	mohor	`LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,`
104			`RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,`
105	168	mohor	`StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,`
106			`r_FullD`
107	15	mohor	`);`
108
109
110
111			`parameter Tp = 1;`
112
113
114			`input MRxClk;`
115			`input Reset;`
116			`input RxCrcError;`
117			`input MRxErr;`
118			`input MRxDV;`
119
120			`input RxStateSFD;`
121			`input [1:0] RxStateData;`
122			`input RxStatePreamble;`
123			`input RxStateIdle;`
124			`input Transmitting;`
125			`input [15:0] RxByteCnt;`
126			`input RxByteCntEq0;`
127			`input RxByteCntGreat2;`
128			`input RxByteCntMaxFrame;`
129			`input ReceivedPauseFrm;`
130	42	mohor	`input [3:0] MRxD;`
131			`input Collision;`
132			`input [5:0] CollValid;`
133			`input r_RecSmall;`
134			`input [15:0] r_MinFL;`
135			`input [15:0] r_MaxFL;`
136			`input r_HugEn;`
137	43	mohor	`input StartTxDone;`
138			`input StartTxAbort;`
139			`input [3:0] RetryCnt;`
140			`input MTxClk;`
141			`input MaxCollisionOccured;`
142			`input LateCollision;`
143			`input StartDefer;`
144			`input TxStartFrm;`
145			`input StatePreamble;`
146			`input [1:0] StateData;`
147			`input CarrierSense;`
148			`input TxUsedData;`
149	146	mohor	`input Loopback;`
150	168	mohor	`input r_FullD;`
151	15	mohor
152	43	mohor
153	15	mohor	`output ReceivedLengthOK;`
154			`output ReceiveEnd;`
155			`output ReceivedPacketGood;`
156	42	mohor	`output InvalidSymbol;`
157			`output LatchedCrcError;`
158			`output RxLateCollision;`
159			`output ShortFrame;`
160			`output DribbleNibble;`
161			`output ReceivedPacketTooBig;`
162			`output LoadRxStatus;`
163	43	mohor	`output [3:0] RetryCntLatched;`
164			`output RetryLimit;`
165			`output LateCollLatched;`
166			`output DeferLatched;`
167			`output CarrierSenseLost;`
168	126	mohor	`output LatchedMRxErr;`
169	15	mohor
170	43	mohor
171	15	mohor	`reg ReceiveEnd;`
172
173			`reg LatchedCrcError;`
174			`reg LatchedMRxErr;`
175	42	mohor	`reg LoadRxStatus;`
176			`reg InvalidSymbol;`
177	43	mohor	`reg [3:0] RetryCntLatched;`
178			`reg RetryLimit;`
179			`reg LateCollLatched;`
180			`reg DeferLatched;`
181			`reg CarrierSenseLost;`
182	15	mohor
183			`wire TakeSample;`
184	42	mohor	`wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps`
185	15	mohor
186			`// Crc error`
187			`always @ (posedge MRxClk or posedge Reset)`
188			`begin`
189			`if(Reset)`
190			`LatchedCrcError <=#Tp 1'b0;`
191			`else`
192	42	mohor	`if(RxStateSFD)`
193			`LatchedCrcError <=#Tp 1'b0;`
194			`else`
195			`if(RxStateData[0])`
196			`LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;`
197	15	mohor	`end`
198
199
200			`// LatchedMRxErr`
201			`always @ (posedge MRxClk or posedge Reset)`
202			`begin`
203			`if(Reset)`
204			`LatchedMRxErr <=#Tp 1'b0;`
205			`else`
206	18	mohor	`if(MRxErr & MRxDV & (RxStatePreamble \| RxStateSFD \| (\|RxStateData) \| RxStateIdle & ~Transmitting))`
207	15	mohor	`LatchedMRxErr <=#Tp 1'b1;`
208	126	mohor	`else`
209			`LatchedMRxErr <=#Tp 1'b0;`
210	15	mohor	`end`
211
212
213			`// ReceivedPacketGood`
214	126	mohor	`assign ReceivedPacketGood = ~LatchedCrcError;`
215	15	mohor
216
217			`// ReceivedLengthOK`
218	101	mohor	`assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];`
219	15	mohor
220
221
222	42	mohor
223
224			`// Time to take a sample`
225			`assign TakeSample = \|RxStateData & ~MRxDV & RxByteCntGreat2 \|`
226			`RxStateData[0] & MRxDV & RxByteCntMaxFrame;`
227
228
229			`// LoadRxStatus`
230	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
231			`begin`
232			`if(Reset)`
233	42	mohor	`LoadRxStatus <=#Tp 1'b0;`
234	15	mohor	`else`
235	42	mohor	`LoadRxStatus <=#Tp TakeSample;`
236	15	mohor	`end`
237
238
239
240	42	mohor	`// ReceiveEnd`
241			`always @ (posedge MRxClk or posedge Reset)`
242			`begin`
243			`if(Reset)`
244			`ReceiveEnd <=#Tp 1'b0;`
245			`else`
246			`ReceiveEnd <=#Tp LoadRxStatus;`
247			`end`
248	15	mohor
249
250	42	mohor	`// Invalid Symbol received during 100Mbps mode`
251	126	mohor	`assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;`
252	42	mohor
253
254			`// InvalidSymbol`
255	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
256			`begin`
257			`if(Reset)`
258	42	mohor	`InvalidSymbol <=#Tp 1'b0;`
259	15	mohor	`else`
260	42	mohor	`if(LoadRxStatus & ~SetInvalidSymbol)`
261			`InvalidSymbol <=#Tp 1'b0;`
262			`else`
263			`if(SetInvalidSymbol)`
264			`InvalidSymbol <=#Tp 1'b1;`
265	15	mohor	`end`
266
267
268	42	mohor	`// Late Collision`
269	15	mohor
270	42	mohor	`reg RxLateCollision;`
271			`reg RxColWindow;`
272			`// Collision Window`
273	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
274			`begin`
275			`if(Reset)`
276	42	mohor	`RxLateCollision <=#Tp 1'b0;`
277	15	mohor	`else`
278	42	mohor	`if(LoadRxStatus)`
279			`RxLateCollision <=#Tp 1'b0;`
280			`else`
281			`if(Collision & (~RxColWindow \| r_RecSmall))`
282			`RxLateCollision <=#Tp 1'b1;`
283	15	mohor	`end`
284
285	42	mohor	`// Collision Window`
286			`always @ (posedge MRxClk or posedge Reset)`
287			`begin`
288			`if(Reset)`
289			`RxColWindow <=#Tp 1'b1;`
290			`else`
291			`if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])`
292			`RxColWindow <=#Tp 1'b0;`
293			`else`
294			`if(RxStateIdle)`
295			`RxColWindow <=#Tp 1'b1;`
296			`end`
297	15	mohor
298	42	mohor
299			`// ShortFrame`
300			`reg ShortFrame;`
301			`always @ (posedge MRxClk or posedge Reset)`
302			`begin`
303			`if(Reset)`
304			`ShortFrame <=#Tp 1'b0;`
305			`else`
306			`if(LoadRxStatus)`
307			`ShortFrame <=#Tp 1'b0;`
308			`else`
309			`if(TakeSample)`
310	101	mohor	`ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];`
311	42	mohor	`end`
312
313
314			`// DribbleNibble`
315			`reg DribbleNibble;`
316			`always @ (posedge MRxClk or posedge Reset)`
317			`begin`
318			`if(Reset)`
319			`DribbleNibble <=#Tp 1'b0;`
320			`else`
321			`if(RxStateSFD)`
322			`DribbleNibble <=#Tp 1'b0;`
323			`else`
324			`if(~MRxDV & RxStateData[1])`
325			`DribbleNibble <=#Tp 1'b1;`
326			`end`
327
328
329			`reg ReceivedPacketTooBig;`
330			`always @ (posedge MRxClk or posedge Reset)`
331			`begin`
332			`if(Reset)`
333			`ReceivedPacketTooBig <=#Tp 1'b0;`
334			`else`
335			`if(LoadRxStatus)`
336			`ReceivedPacketTooBig <=#Tp 1'b0;`
337			`else`
338			`if(TakeSample)`
339			`ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];`
340			`end`
341
342	43	mohor
343
344			`// Latched Retry counter for tx status`
345			`always @ (posedge MTxClk or posedge Reset)`
346			`begin`
347			`if(Reset)`
348			`RetryCntLatched <=#Tp 4'h0;`
349			`else`
350			`if(StartTxDone \| StartTxAbort)`
351			`RetryCntLatched <=#Tp RetryCnt;`
352			`end`
353
354
355			`// Latched Retransmission limit`
356			`always @ (posedge MTxClk or posedge Reset)`
357			`begin`
358			`if(Reset)`
359			`RetryLimit <=#Tp 4'h0;`
360			`else`
361			`if(StartTxDone \| StartTxAbort)`
362			`RetryLimit <=#Tp MaxCollisionOccured;`
363			`end`
364
365
366			`// Latched Late Collision`
367			`always @ (posedge MTxClk or posedge Reset)`
368			`begin`
369			`if(Reset)`
370			`LateCollLatched <=#Tp 1'b0;`
371			`else`
372			`if(StartTxDone \| StartTxAbort)`
373			`LateCollLatched <=#Tp LateCollision;`
374			`end`
375
376
377
378			`// Latched Defer state`
379			`always @ (posedge MTxClk or posedge Reset)`
380			`begin`
381			`if(Reset)`
382			`DeferLatched <=#Tp 1'b0;`
383			`else`
384			`if(StartDefer & TxUsedData)`
385			`DeferLatched <=#Tp 1'b1;`
386			`else`
387			`if(TxStartFrm)`
388			`DeferLatched <=#Tp 1'b0;`
389			`end`
390
391
392			`// CarrierSenseLost`
393			`always @ (posedge MTxClk or posedge Reset)`
394			`begin`
395			`if(Reset)`
396			`CarrierSenseLost <=#Tp 1'b0;`
397			`else`
398	168	mohor	`if((StatePreamble \| (\|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)`
399	43	mohor	`CarrierSenseLost <=#Tp 1'b1;`
400			`else`
401			`if(TxStartFrm)`
402			`CarrierSenseLost <=#Tp 1'b0;`
403			`end`
404
405
406	15	mohor	`endmodule`

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_8/] [rtl/] [verilog/] [eth_macstatus.v] - Blame information for rev 338