OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [eth_memory.v] - Blame information for rev 346

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_memory.v                                                ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 116 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001, 2002 Authors                             ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
//
45
//
46
//
47
//
48
 
49
`include "tb_eth_defines.v"
50
`include "timescale.v"
51
 
52
module eth_memory
53
(
54
  wb_clk_i, wb_rst_i, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
55
  wb_stb_i, wb_ack_o, wb_err_o, wb_dat_o, wb_dat_i
56
);
57
 
58
parameter Tp=1;
59
 
60
input         wb_clk_i, wb_rst_i;
61
input  [31:0] wb_adr_i, wb_dat_i;
62
input   [3:0] wb_sel_i;
63
input         wb_we_i, wb_cyc_i, wb_stb_i;
64
 
65
output        wb_ack_o, wb_err_o;
66
output [31:0] wb_dat_o;
67
 
68
reg           wb_ack_o, wb_err_o;
69
reg    [31:0] wb_dat_o;
70
 
71
reg     [7:0] memory0 [0:65535];
72
reg     [7:0] memory1 [0:65535];
73
reg     [7:0] memory2 [0:65535];
74
reg     [7:0] memory3 [0:65535];
75
 
76
integer memory_log;
77
 
78
// Reset pulse
79
initial
80
begin
81
  memory_log = $fopen("eth_memory.log");
82
  wb_ack_o = 0;
83
  wb_err_o = 0;
84
end
85
 
86
 
87
always @ (posedge wb_clk_i)
88
begin
89
  if(wb_cyc_i & wb_stb_i)
90
    begin
91
      repeat(1) @ (posedge wb_clk_i);     // Waiting 3 clock cycles before ack is set
92
        begin                             // (you can add some random function here)
93
          #1;
94
          wb_ack_o = 1'b1;
95
          if(~wb_we_i)
96
            begin
97
              if(wb_adr_i[1:0] == 2'b00)       // word access
98
                begin
99
                  wb_dat_o[31:24] = memory3[wb_adr_i[17:2]];
100
                  wb_dat_o[23:16] = memory2[wb_adr_i[17:2]];
101
                  wb_dat_o[15:08] = memory1[wb_adr_i[17:2]];
102
                  wb_dat_o[07:00] = memory0[wb_adr_i[17:2]];
103
                end
104
              else if(wb_adr_i[1:0] == 2'b10)       // half access
105
                begin
106
                  wb_dat_o[31:24] = 0;
107
                  wb_dat_o[23:16] = 0;
108
                  wb_dat_o[15:08] = memory1[wb_adr_i[17:2]];
109
                  wb_dat_o[07:00] = memory0[wb_adr_i[17:2]];
110
                end
111
              else if(wb_adr_i[1:0] == 2'b01)       // byte access
112
                begin
113
                  wb_dat_o[31:24] = 0;
114
                  wb_dat_o[23:16] = memory2[wb_adr_i[17:2]];
115
                  wb_dat_o[15:08] = 0;
116
                  wb_dat_o[07:00] = 0;
117
                end
118
              else if(wb_adr_i[1:0] == 2'b11)       // byte access
119
                begin
120
                  wb_dat_o[31:24] = 0;
121
                  wb_dat_o[23:16] = 0;
122
                  wb_dat_o[15:08] = 0;
123
                  wb_dat_o[07:00] = memory0[wb_adr_i[17:2]];
124
                end
125
 
126
              $fdisplay(memory_log, "(%0t)(%m)wb_read (0x%0x) = 0x%0x", $time, wb_adr_i, wb_dat_o);
127
            end
128
          else
129
            begin
130
              $fdisplay(memory_log, "(%0t)(%m)wb_write (0x%0x) = 0x%0x", $time, wb_adr_i, wb_dat_i);
131
              if(wb_sel_i[0])
132
                memory0[wb_adr_i[17:2]] = wb_dat_i[7:0];
133
              if(wb_sel_i[1])
134
                memory1[wb_adr_i[17:2]] = wb_dat_i[15:8];
135
              if(wb_sel_i[2])
136
                memory2[wb_adr_i[17:2]] = wb_dat_i[23:16];
137
              if(wb_sel_i[3])
138
                memory3[wb_adr_i[17:2]] = wb_dat_i[31:24];
139
            end
140
        end
141
      @ (posedge wb_clk_i);
142
      wb_ack_o <=#Tp 1'b0;
143
    end
144
end
145
 
146
 
147
 
148
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.