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[/] [ethmac/] [trunk/] [bench/] [verilog/] [eth_phy_defines.v] - Blame information for rev 346

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name: eth_phy_defines.v                                ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Tadej Markovic, tadej@opencores.org                   ////
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////                                                              ////
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////  All additional information is available in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2002,  Authors                                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2002/09/13 11:57:20  mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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//
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//
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// Address of PHY device (LXT971A)
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`define ETH_PHY_ADDR                 5'h01
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// LED/Configuration pins on PHY device - see the specification, page 26, table 8
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// Initial set of bits 13, 12 and 8 of Control Register
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`define LED_CFG1                     1'b0
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`define LED_CFG2                     1'b0
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`define LED_CFG3                     1'b1
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// Supported speeds and physical ports - see the specification, page 67, table 41
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// Set bits 15 to 9 of Status Register
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`define SUPPORTED_SPEED_AND_PORT     7'h3F
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// Extended status register (address 15)
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// Set bit 8 of Status Register
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`define EXTENDED_STATUS              1'b0
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// Default status bits - see the specification, page 67, table 41
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// Set bits 6 to 0 of Status Register
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`define DEFAULT_STATUS               7'h09
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// PHY ID 1 number - see the specification, page 68, table 42
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// Set bits of Phy Id Register 1
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`define PHY_ID1                      16'h0013
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// PHY ID 2 number - see the specification, page 68, table 43
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// Set bits 15 to 10 of Phy Id Register 2
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`define PHY_ID2                      6'h1E
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// Manufacturer MODEL number - see the specification, page 68, table 43
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// Set bits 9 to 4 of Phy Id Register 2
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`define MAN_MODEL_NUM                6'h0E
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// Manufacturer REVISION number - see the specification, page 68, table 43
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// Set bits 3 to 0 of Phy Id Register 2
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`define MAN_REVISION_NUM             4'h2
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