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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_defines.v] - Blame information for rev 346

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  tb_eth_defines.v                                            ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is available in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.10  2002/11/19 20:27:46  mohor
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// Temp version.
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//
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// Revision 1.9  2002/10/09 13:16:51  tadejm
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// Just back-up; not completed testbench and some testcases are not
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// wotking properly yet.
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//
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// Revision 1.8  2002/09/13 18:41:45  mohor
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// Rearanged testcases
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//
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// Revision 1.7  2002/09/13 12:29:14  mohor
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// Headers changed.
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//
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// Revision 1.6  2002/09/13 11:57:20  mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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// Revision 1.3  2002/07/19 13:57:53  mohor
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// Testing environment also includes traffic cop, memory interface and host
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// interface.
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//
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// Revision 1.2  2002/05/03 10:22:17  mohor
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// TX_BUF_BASE changed.
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//
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// Revision 1.1  2002/03/19 12:53:54  mohor
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// Some defines that are used in testbench only were moved to tb_eth_defines.v
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// file.
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//
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//
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//
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//
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//`define VERBOSE                       // if log files of device modules are written
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`define MULTICAST_XFR          0
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`define UNICAST_XFR            1
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`define BROADCAST_XFR          2
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`define UNICAST_WRONG_XFR      3
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`define ETH_BASE              32'hd0000000
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`define ETH_WIDTH             32'h800
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`define MEMORY_BASE           32'h2000
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`define MEMORY_WIDTH          32'h10000
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`define TX_BUF_BASE           `MEMORY_BASE
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`define RX_BUF_BASE           `MEMORY_BASE + 32'h8000
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`define TX_BD_BASE            `ETH_BASE + 32'h00000400
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`define RX_BD_BASE            `ETH_BASE + 32'h00000600
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/* Tx BD */
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`define ETH_TX_BD_READY    32'h8000 /* Tx BD Ready */
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`define ETH_TX_BD_IRQ      32'h4000 /* Tx BD IRQ Enable */
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`define ETH_TX_BD_WRAP     32'h2000 /* Tx BD Wrap (last BD) */
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`define ETH_TX_BD_PAD      32'h1000 /* Tx BD Pad Enable */
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`define ETH_TX_BD_CRC      32'h0800 /* Tx BD CRC Enable */
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`define ETH_TX_BD_UNDERRUN 32'h0100 /* Tx BD Underrun Status */
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`define ETH_TX_BD_RETRY    32'h00F0 /* Tx BD Retry Status */
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`define ETH_TX_BD_RETLIM   32'h0008 /* Tx BD Retransmission Limit Status */
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`define ETH_TX_BD_LATECOL  32'h0004 /* Tx BD Late Collision Status */
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`define ETH_TX_BD_DEFER    32'h0002 /* Tx BD Defer Status */
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`define ETH_TX_BD_CARRIER  32'h0001 /* Tx BD Carrier Sense Lost Status */
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/* Rx BD */
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`define ETH_RX_BD_EMPTY    32'h8000 /* Rx BD Empty */
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`define ETH_RX_BD_IRQ      32'h4000 /* Rx BD IRQ Enable */
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`define ETH_RX_BD_WRAP     32'h2000 /* Rx BD Wrap (last BD) */
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`define ETH_RX_BD_MISS     32'h0080 /* Rx BD Miss Status */
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`define ETH_RX_BD_OVERRUN  32'h0040 /* Rx BD Overrun Status */
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`define ETH_RX_BD_INVSIMB  32'h0020 /* Rx BD Invalid Symbol Status */
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`define ETH_RX_BD_DRIBBLE  32'h0010 /* Rx BD Dribble Nibble Status */
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`define ETH_RX_BD_TOOLONG  32'h0008 /* Rx BD Too Long Status */
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`define ETH_RX_BD_SHORT    32'h0004 /* Rx BD Too Short Frame Status */
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`define ETH_RX_BD_CRCERR   32'h0002 /* Rx BD CRC Error Status */
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`define ETH_RX_BD_LATECOL  32'h0001 /* Rx BD Late Collision Status */
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/* Register space */
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`define ETH_MODER      `ETH_BASE + 32'h00       /* Mode Register */
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`define ETH_INT        `ETH_BASE + 32'h04       /* Interrupt Source Register */
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`define ETH_INT_MASK   `ETH_BASE + 32'h08 /* Interrupt Mask Register */
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`define ETH_IPGT       `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */
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`define ETH_IPGR1      `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */
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`define ETH_IPGR2      `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */
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`define ETH_PACKETLEN  `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */
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`define ETH_COLLCONF   `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */
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`define ETH_TX_BD_NUM  `ETH_BASE + 32'h20 /* Transmit Buffer Descriptor Number Register */
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`define ETH_CTRLMODER  `ETH_BASE + 32'h24 /* Control Module Mode Register */
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`define ETH_MIIMODER   `ETH_BASE + 32'h28 /* MII Mode Register */
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`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */
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`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */
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`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */
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`define ETH_MIIRX_DATA `ETH_BASE + 32'h38 /* MII Receive Data Register */
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`define ETH_MIISTATUS  `ETH_BASE + 32'h3C /* MII Status Register */
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`define ETH_MAC_ADDR0  `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
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`define ETH_MAC_ADDR1  `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
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`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
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`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
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`define ETH_TX_CTRL    `ETH_BASE + 32'h50 /* Tx Control Register */
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/* MODER Register */
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`define ETH_MODER_RXEN     32'h00000001 /* Receive Enable  */
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`define ETH_MODER_TXEN     32'h00000002 /* Transmit Enable */
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`define ETH_MODER_NOPRE    32'h00000004 /* No Preamble  */
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`define ETH_MODER_BRO      32'h00000008 /* Reject Broadcast */
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`define ETH_MODER_IAM      32'h00000010 /* Use Individual Hash */
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`define ETH_MODER_PRO      32'h00000020 /* Promiscuous (receive all) */
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`define ETH_MODER_IFG      32'h00000040 /* Min. IFG not required */
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`define ETH_MODER_LOOPBCK  32'h00000080 /* Loop Back */
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`define ETH_MODER_NOBCKOF  32'h00000100 /* No Backoff */
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`define ETH_MODER_EXDFREN  32'h00000200 /* Excess Defer */
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`define ETH_MODER_FULLD    32'h00000400 /* Full Duplex */
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`define ETH_MODER_RST      32'h00000800 /* Reset MAC */
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`define ETH_MODER_DLYCRCEN 32'h00001000 /* Delayed CRC Enable */
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`define ETH_MODER_CRCEN    32'h00002000 /* CRC Enable */
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`define ETH_MODER_HUGEN    32'h00004000 /* Huge Enable */
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`define ETH_MODER_PAD      32'h00008000 /* Pad Enable */
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`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */
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/* Interrupt Source Register */
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`define ETH_INT_TXB        32'h00000001 /* Transmit Buffer IRQ */
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`define ETH_INT_TXE        32'h00000002 /* Transmit Error IRQ */
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`define ETH_INT_RXB        32'h00000004 /* Receive Buffer IRQ */
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`define ETH_INT_RXE        32'h00000008 /* Receive Error IRQ */
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`define ETH_INT_BUSY       32'h00000010 /* Busy IRQ */
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`define ETH_INT_TXC        32'h00000020 /* Transmit Control Frame IRQ */
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`define ETH_INT_RXC        32'h00000040 /* Received Control Frame IRQ */
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/* Interrupt Mask Register */
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`define ETH_INT_MASK_TXB   32'h00000001 /* Transmit Buffer IRQ Mask */
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`define ETH_INT_MASK_TXE   32'h00000002 /* Transmit Error IRQ Mask */
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`define ETH_INT_MASK_RXF   32'h00000004 /* Receive Frame IRQ Mask */
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`define ETH_INT_MASK_RXE   32'h00000008 /* Receive Error IRQ Mask */
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`define ETH_INT_MASK_BUSY  32'h00000010 /* Busy IRQ Mask */
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`define ETH_INT_MASK_TXC   32'h00000020 /* Transmit Control Frame IRQ Mask */
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`define ETH_INT_MASK_RXC   32'h00000040 /* Received Control Frame IRQ Mask */
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/* Control Module Mode Register */
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`define ETH_CTRLMODER_PASSALL 32'h00000001 /* Pass Control Frames */
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`define ETH_CTRLMODER_RXFLOW  32'h00000002 /* Receive Control Flow Enable */
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`define ETH_CTRLMODER_TXFLOW  32'h00000004 /* Transmit Control Flow Enable */
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/* MII Mode Register */
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`define ETH_MIIMODER_CLKDIV   32'h000000FF /* Clock Divider */
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`define ETH_MIIMODER_NOPRE    32'h00000100 /* No Preamble */
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`define ETH_MIIMODER_RST      32'h00000200 /* MIIM Reset */
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/* MII Command Register */
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`define ETH_MIICOMMAND_SCANSTAT  32'h00000001 /* Scan Status */
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`define ETH_MIICOMMAND_RSTAT     32'h00000002 /* Read Status */
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`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
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/* MII Address Register */
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`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */
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`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */
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/* MII Status Register */
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`define ETH_MIISTATUS_LINKFAIL    0 /* Link Fail bit */
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`define ETH_MIISTATUS_BUSY        1 /* MII Busy bit */
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`define ETH_MIISTATUS_NVALID      2 /* Data in MII Status Register is invalid bit */
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/* TX Control Register */
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`define ETH_TX_CTRL_TXPAUSERQ     32'h10000 /* Send PAUSE request */
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`define TIME $display("  Time: %0t", $time)

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