OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Blame information for rev 356

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 157 mohor
 
2
 
3
 
4
 
5
 
6
 
7
 
8
 
9
Please use tb_ethernet.v for testbench. Testbench will soon be
10
updated.
11
 
12
 
13
 
14
 
15
 
16
 
17
 
18
 
19
 
20
 
21
 
22
 
23
 
24 66 mohor
//////////////////////////////////////////////////////////////////////
25 15 mohor
////                                                              ////
26
////  tb_eth_top.v                                                ////
27
////                                                              ////
28
////  This file is part of the Ethernet IP core project           ////
29 346 olof
////  http://www.opencores.org/project,ethmac                     ////
30 15 mohor
////                                                              ////
31
////  Author(s):                                                  ////
32
////      - Igor Mohor (igorM@opencores.org)                      ////
33
////                                                              ////
34
////  All additional information is avaliable in the Readme.txt   ////
35
////  file.                                                       ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
////                                                              ////
39
//// Copyright (C) 2001 Authors                                   ////
40
////                                                              ////
41
//// This source file may be used and distributed without         ////
42
//// restriction provided that this copyright statement is not    ////
43
//// removed from the file and that any derivative work contains  ////
44
//// the original copyright notice and the associated disclaimer. ////
45
////                                                              ////
46
//// This source file is free software; you can redistribute it   ////
47
//// and/or modify it under the terms of the GNU Lesser General   ////
48
//// Public License as published by the Free Software Foundation; ////
49
//// either version 2.1 of the License, or (at your option) any   ////
50
//// later version.                                               ////
51
////                                                              ////
52
//// This source is distributed in the hope that it will be       ////
53
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
54
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
55
//// PURPOSE.  See the GNU Lesser General Public License for more ////
56
//// details.                                                     ////
57
////                                                              ////
58
//// You should have received a copy of the GNU Lesser General    ////
59
//// Public License along with this source; if not, download it   ////
60
//// from http://www.opencores.org/lgpl.shtml                     ////
61
////                                                              ////
62
//////////////////////////////////////////////////////////////////////
63
//
64
// CVS Revision History
65
//
66
// $Log: not supported by cvs2svn $
67 157 mohor
// Revision 1.13  2002/05/03 10:25:01  mohor
68
// Testbench supports unaligned accesses.
69
//
70 108 mohor
// Revision 1.12  2002/02/26 17:01:09  mohor
71
// Small fixes for external/internal DMA missmatches.
72
//
73 80 mohor
// Revision 1.11  2002/02/16 13:06:59  mohor
74
// EXTERNAL_DMA used instead of WISHBONE_DMA.
75
//
76 67 mohor
// Revision 1.10  2002/02/16 07:22:15  mohor
77
// Testbench fixed, code simplified, unused signals removed.
78
//
79 66 mohor
// Revision 1.9  2002/02/14 20:14:38  billditt
80
// Added separate tests for Multicast, Unicast, Broadcast
81
//
82
// Revision 1.8  2002/02/12 20:24:00  mohor
83
// HASH0 and HASH1 register read/write added.
84
//
85 49 mohor
// Revision 1.7  2002/02/06 14:11:35  mohor
86
// non-DMA host interface added. Select the right configutation in eth_defines.
87
//
88 41 mohor
// Revision 1.6  2001/12/08 12:36:00  mohor
89
// TX_BD_NUM register added instead of the RB_BD_ADDR.
90
//
91 36 mohor
// Revision 1.5  2001/10/19 11:24:04  mohor
92
// Number of addresses (wb_adr_i) minimized.
93
//
94 23 mohor
// Revision 1.4  2001/10/19 08:46:53  mohor
95
// eth_timescale.v changed to timescale.v This is done because of the
96
// simulation of the few cores in a one joined project.
97
//
98 22 mohor
// Revision 1.3  2001/09/24 14:55:49  mohor
99
// Defines changed (All precede with ETH_). Small changes because some
100
// tools generate warnings when two operands are together. Synchronization
101
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
102
// demands).
103
//
104 19 mohor
// Revision 1.2  2001/08/15 14:04:30  mohor
105
// Signal names changed on the top level for easier pad insertion (ASIC).
106
//
107 17 mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
108
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
109
// Include files fixed to contain no path.
110
// File names and module names changed ta have a eth_ prologue in the name.
111
// File eth_timescale.v is used to define timescale
112
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
113
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
114
// and Mdo_OE. The bidirectional signal must be created on the top level. This
115
// is done due to the ASIC tools.
116
//
117 15 mohor
// Revision 1.1  2001/07/30 21:46:09  mohor
118
// Directory structure changed. Files checked and joind together.
119
//
120
//
121
//
122
//
123
//
124
 
125
 
126
 
127 108 mohor
`include "tb_eth_defines.v"
128 356 olof
`include "ethmac_defines.v"
129 22 mohor
`include "timescale.v"
130 15 mohor
 
131
module tb_eth_top();
132
 
133
 
134
parameter Tp = 1;
135
 
136
 
137
reg           WB_CLK_I;
138
reg           WB_RST_I;
139
reg   [31:0]  WB_DAT_I;
140
 
141
reg   [31:0]  WB_ADR_I;
142
reg    [3:0]  WB_SEL_I;
143
reg           WB_WE_I;
144
reg           WB_CYC_I;
145
reg           WB_STB_I;
146
 
147
wire  [31:0]  WB_DAT_O;
148
wire          WB_ACK_O;
149
wire          WB_ERR_O;
150 41 mohor
reg    [1:0]  WB_ACK_I;
151
 
152
// WISHBONE master
153
wire    [31:0]    m_wb_adr_o;
154
wire     [3:0]    m_wb_sel_o;
155
wire              m_wb_we_o;
156
reg     [31:0]    m_wb_dat_i;
157
wire    [31:0]    m_wb_dat_o;
158
wire              m_wb_cyc_o;
159
wire              m_wb_stb_o;
160
reg               m_wb_ack_i;
161
reg               m_wb_err_i;
162 15 mohor
 
163
reg           MTxClk;
164
wire   [3:0]  MTxD;
165
wire          MTxEn;
166
wire          MTxErr;
167
 
168
reg           MRxClk;
169
reg    [3:0]  MRxD;
170
reg           MRxDV;
171
reg           MRxErr;
172
reg           MColl;
173
reg           MCrs;
174
 
175
reg           Mdi_I;
176
wire          Mdo_O;
177
wire          Mdo_OE;
178
wire          Mdc_O;
179
 
180
 
181 108 mohor
reg [7:0] memory0 [0:65535];
182
reg [7:0] memory1 [0:65535];
183
reg [7:0] memory2 [0:65535];
184
reg [7:0] memory3 [0:65535];
185 15 mohor
 
186
reg WishboneBusy;
187
reg StartTB;
188
reg [9:0] TxBDIndex;
189
reg [9:0] RxBDIndex;
190
 
191 108 mohor
reg LogEnable;
192
 
193 41 mohor
  integer mcd1;
194
  integer mcd2;
195 15 mohor
 
196 157 mohor
reg [5:0] g_last_txbd;
197
 
198 15 mohor
// Connecting Ethernet top module
199
 
200
eth_top ethtop
201
(
202
  // WISHBONE common
203 17 mohor
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
204 15 mohor
 
205
  // WISHBONE slave
206 23 mohor
        .wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
207 80 mohor
        .wb_stb_i(WB_STB_I),       .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O),
208 41 mohor
 
209
// WISHBONE master
210
  .m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
211
  .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
212
  .m_wb_err_i(m_wb_err_i),
213 15 mohor
 
214
  //TX
215 19 mohor
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
216 15 mohor
 
217
  //RX
218 19 mohor
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
219 157 mohor
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
220 15 mohor
 
221
  // MIIM
222 108 mohor
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
223 22 mohor
 
224
  .int_o()
225 15 mohor
);
226
 
227
 
228 157 mohor
bench_cop i_bench_cop
229
(
230
  // WISHBONE common
231
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
232 15 mohor
 
233 157 mohor
  // WISHBONE slave
234
        .wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
235
        .wb_stb_i(WB_STB_I),       .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O),
236
 
237
// WISHBONE master
238
  .m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
239
  .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
240
  .m_wb_err_i(m_wb_err_i),
241 15 mohor
 
242 157 mohor
  //TX
243
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
244 15 mohor
 
245 157 mohor
  //RX
246
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
247
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
248
 
249
  // MIIM
250
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
251
 
252
  .int_o()
253
);
254 15 mohor
 
255
 
256 157 mohor
 
257
 
258
 
259
 
260
 
261 15 mohor
initial
262
begin
263
  WB_CLK_I  =  1'b0;
264 19 mohor
  WB_DAT_I  = 32'h0;
265
  WB_ADR_I  = 32'h0;
266
  WB_SEL_I  =  4'h0;
267
  WB_WE_I   =  1'b0;
268 15 mohor
  WB_CYC_I  =  1'b0;
269
  WB_STB_I  =  1'b0;
270 41 mohor
 
271
  m_wb_ack_i = 0;
272
  m_wb_err_i = 0;
273 15 mohor
  MTxClk    =  1'b0;
274
  MRxClk    =  1'b0;
275
  MRxD      =  4'h0;
276
  MRxDV     =  1'b0;
277
  MRxErr    =  1'b0;
278
  MColl     =  1'b0;
279
  MCrs      =  1'b0;
280
  Mdi_I     =  1'b0;
281
 
282
  WishboneBusy = 1'b0;
283
  TxBDIndex = 10'h0;
284
  RxBDIndex = 10'h0;
285 108 mohor
  LogEnable = 1'b1;
286 157 mohor
  g_last_txbd = 6'h0;
287 15 mohor
end
288
 
289
 
290
// Reset pulse
291
initial
292
begin
293 41 mohor
  mcd1 = $fopen("ethernet_tx.log");
294
  mcd2 = $fopen("ethernet_rx.log");
295
  WB_RST_I =  1'b1;
296 15 mohor
  #100 WB_RST_I =  1'b0;
297
  #100 StartTB  =  1'b1;
298
end
299
 
300
 
301
 
302
// Generating WB_CLK_I clock
303
always
304
begin
305 41 mohor
//  forever #2.5 WB_CLK_I = ~WB_CLK_I;  // 2*2.5 ns -> 200.0 MHz    
306 19 mohor
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
307 15 mohor
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
308 157 mohor
  forever #12.5 WB_CLK_I = ~WB_CLK_I;  // 2*12.5 ns -> 40 MHz    
309 108 mohor
//  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
310 157 mohor
//  forever #20 WB_CLK_I = ~WB_CLK_I;  // 2*20 ns -> 25 MHz    
311 41 mohor
//  forever #25 WB_CLK_I = ~WB_CLK_I;  // 2*25 ns -> 20.0 MHz
312 108 mohor
//  forever #31.25 WB_CLK_I = ~WB_CLK_I;  // 2*31.25 ns -> 16.0 MHz    
313 41 mohor
//  forever #50 WB_CLK_I = ~WB_CLK_I;  // 2*50 ns -> 10.0 MHz
314
//  forever #55 WB_CLK_I = ~WB_CLK_I;  // 2*55 ns ->  9.1 MHz    
315 15 mohor
end
316
 
317
// Generating MTxClk clock
318
always
319
begin
320 108 mohor
//  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
321
  #3 forever #200 MTxClk = ~MTxClk;   // 2*200 ns -> 2.5 MHz
322 15 mohor
end
323
 
324
// Generating MRxClk clock
325
always
326
begin
327 108 mohor
//  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
328 157 mohor
  #16 forever #200 MRxClk = ~MRxClk;   // 2*200 ns -> 2.5 MHz
329
//  #16 forever #62.5 MRxClk = ~MRxClk;   // 2*62.5 ns -> 8 MHz       // just for testing purposes
330 15 mohor
end
331
 
332 157 mohor
 
333 15 mohor
initial
334
begin
335
  wait(StartTB);  // Start of testbench
336
 
337 157 mohor
  // Reset eth MAC core
338 22 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
339
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
340 15 mohor
 
341 157 mohor
  InitializeMemory;
342 15 mohor
 
343 157 mohor
// Select which test you want to run:
344
  //  TestTxAndRx;
345
    TestFullDuplex;
346
  //  TestUnicast;
347
  //  TestBroadcast;
348
  //  TestMulticast;
349 15 mohor
end
350 157 mohor
 
351
task TestTxAndRx;
352 15 mohor
 
353 157 mohor
 integer ii, jj;
354
 integer data_in, bd, pointer;
355 15 mohor
 
356 157 mohor
 begin
357
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
358
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
359
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
360 15 mohor
 
361 157 mohor
//  WishboneWrite(32'h0000a06b, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, CrcEn, Pad en, half duplex, 
362
  WishboneWrite(32'h0000a46b, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, CrcEn, Pad en, full duplex, 
363
//  WishboneWrite(32'h0001a06b, {26'h0, `ETH_MODER_ADR<<2});     // r_RecSmall, RxEn, Txen, CrcEn, Pad en, half duplex, 
364
                                                               // r_IPG, promisc On, reject broadcast 
365 15 mohor
 
366 157 mohor
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
367 15 mohor
 
368 157 mohor
  WishboneWrite(32'h00000002, {26'h0, `ETH_MAC_ADDR1_ADR<<2}); // MAC = 000203040506
369
  WishboneWrite(32'h03040506, {26'h0, `ETH_MAC_ADDR0_ADR<<2});
370 15 mohor
 
371 157 mohor
/*
372
// Just few reads
373
  WishboneRead({26'h0, `ETH_MODER_ADR<<2}, data_in);       // Read from ETH_MODER register
374
  WishboneRead({26'h0, `ETH_TX_BD_NUM_ADR<<2}, data_in);       // Read from ETH_TX_BD_NUM_ADR register
375
  WishboneRead({26'h0, `ETH_MAC_ADDR1_ADR<<2}, data_in);       // Read from ETH_MAC_ADDR1_ADR register
376
  WishboneRead({26'h0, `ETH_MAC_ADDR0_ADR<<2}, data_in);       // Read from ETH_MAC_ADDR0_ADR register
377
*/
378 15 mohor
 
379
 
380
 
381 19 mohor
 
382 157 mohor
    for(jj=0; jj<8; jj=jj+4)
383
    begin
384
      WishboneWriteData(`TX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
385
    end
386 15 mohor
 
387 157 mohor
    for(jj=0; jj<8; jj=jj+4)
388 15 mohor
    begin
389 157 mohor
      WishboneWriteData(`RX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
390 15 mohor
    end
391
 
392 157 mohor
//  SendPacketX(16'h0064, 1'b0, 2'h3);
393
//  SendPacketX(16'h0064, 1'b0, 2'h2);
394
//  SendPacketX(16'h0064, 1'b0, 2'h1);
395
//  SendPacketX(16'h0064, 1'b0, 2'h0);
396
//  SendPacket(16'h0064, 1'b0);
397
//  SendPacket(16'h0011, 1'b0);
398
//  SendPacket(16'h0012, 1'b0);
399 15 mohor
 
400 157 mohor
fork
401
  begin
402
/*
403
  SendPacketX(16'h0064, 1'b0, 2'h1);
404
  SendPacketX(16'h0064, 1'b0, 2'h2);
405
  SendPacketX(16'h0064, 1'b0, 2'h3);
406
  SendPacketX(16'h0064, 1'b0, 2'h0);
407
*/
408
//    SendPacketX(16'h264, 1'b0, 2'h3);
409
//    SendPacketX(16'h64, 1'b0, 2'h3);
410
//    SendPacketX(16'h104, 1'b0, 2'h3);
411 15 mohor
  end
412
 
413
  begin
414 157 mohor
    ReceivePacketX(16'h0040, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
415
    ReceivePacketX(16'h0041, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
416
    ReceivePacketX(16'h0042, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
417
    ReceivePacketX(16'h0043, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
418
    ReceivePacketX(16'h0044, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
419
  end
420 15 mohor
 
421 157 mohor
//  begin
422
//    for(ii=0; ii<10000; ii=ii+1)
423
//      begin
424
//        WishboneRead({22'h01, 10'b0}, data_in);  // read back
425
//        #100;
426
//      end
427
//  end
428
//join
429 15 mohor
 
430 157 mohor
//fork
431
/*
432
  begin
433
    repeat(4)
434 15 mohor
      begin
435 157 mohor
        wait(tb_eth_top.ethtop.wishbone.TxStatusWrite);   // wait until tx status is written
436
        @ (posedge WB_CLK_I)
437
        #1;
438 15 mohor
      end
439
  end
440 157 mohor
*/
441
  begin
442
    wait(tb_eth_top.ethtop.wishbone.RxStatusWrite);   // wait until rx status is written
443
  end
444 15 mohor
 
445 157 mohor
join
446 15 mohor
 
447
 
448 157 mohor
/*
449
  SendPacket(16'h0013, 1'b0);
450
  SendPacket(16'h0014, 1'b0);
451 15 mohor
 
452 157 mohor
  SendPacket(16'h0030, 1'b0);
453
  SendPacket(16'h0031, 1'b0);
454
  SendPacket(16'h0032, 1'b0);
455
  SendPacket(16'h0033, 1'b0);
456
  SendPacket(16'h0025, 1'b0);
457
  SendPacket(16'h0045, 1'b0);
458
  SendPacket(16'h0025, 1'b0);
459
  SendPacket(16'h0017, 1'b0);
460
*/
461 15 mohor
 
462 157 mohor
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h3);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
463
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h2);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
464
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h1);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
465
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
466 15 mohor
 
467 157 mohor
//  ReceivePacket(16'h0050, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
468
//  ReceivePacket(16'h0051, 1'b0, `UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
469
//  ReceivePacket(16'h0052, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
470
//  ReceivePacket(16'h0053, 1'b0, `BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
471
//  ReceivePacket(16'h0054, 1'b0, `UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
472
//  ReceivePacket(16'h0055, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
473
//  ReceivePacket(16'h0056, 1'b0, `UNICAST_WRONG_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
474 15 mohor
 
475
 
476 157 mohor
  repeat(1000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
477 15 mohor
 
478 157 mohor
//  WishboneRead({24'h04, (8'h0<<2)}, RxBD);       // Read from TxBD register
479
//  WishboneRead({24'h04, (8'h1<<2)}, RxBD);       // Read from TxBD register
480
//  WishboneRead({24'h04, (8'h2<<2)}, RxBD);       // Read from TxBD register
481
//  WishboneRead({24'h04, (8'h3<<2)}, RxBD);       // Read from TxBD register
482
//  WishboneRead({24'h04, (8'h4<<2)}, RxBD);       // Read from TxBD register
483 15 mohor
 
484 157 mohor
  for(jj=0; jj<3; jj=jj+1)    // How many TxBD do we want to read?
485 15 mohor
  begin
486 157 mohor
 
487
      WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd);       // Read from TxBD
488
      $display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, jj, bd);
489
      if(~bd[15]) // Ready = 0?
490
        begin
491
          WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2+1'h1)<<2)}, pointer);  // Read TxBD pointer
492
          $display("\t\t\tRead TxBDPointer 0x=%x", pointer);
493
          $write("\t\t\tData:");
494
          for(ii=0; ii<bd[31:16]; ii=ii+4)
495
            begin
496
              WishboneReadData({pointer[31:2], 2'h0}+ii, data_in);        // Read data from Tx Pointer
497
              $write("\t0x%x", data_in);
498
            end
499
        end
500 15 mohor
  end
501
 
502
 
503 157 mohor
  for(jj=0; jj<3; jj=jj+1)    // How many RxBD do we want to read?
504 15 mohor
  begin
505 157 mohor
 
506
      WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2)<<2)}, bd);       // Read from RxBD
507
      $display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, jj, bd);
508
      if(~bd[15]) // Empty = 0?
509
        begin
510
          WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2+1'h1)<<2)}, pointer);  // Read RxBD pointer
511
          $display("\t\t\tRead RxBDPointer 0x=%x", pointer);
512
          $write("\t\t\tData:");
513
          for(ii=0; ii<bd[31:16]+4; ii=ii+4)
514
            begin
515
              WishboneReadData({pointer[31:2], 2'h0} + ii, data_in);        // Read data from Rx Pointer
516
              $write("\t0x%x", data_in);
517
            end
518
        end
519 15 mohor
  end
520
 
521 157 mohor
  WishboneRead({22'h01, (10'h81<<2)}, data_in);       // Read from RxBD register
522
  WishboneRead({22'h01, (10'h82<<2)}, data_in);       // Read from RxBD register
523
  WishboneRead({22'h01, (10'h83<<2)}, data_in);       // Read from RxBD register
524
  WishboneRead({22'h01, (10'h84<<2)}, data_in);       // Read from RxBD register
525
  WishboneRead({22'h01, (10'h85<<2)}, data_in);       // Read from RxBD register
526
  WishboneRead({22'h01, (10'h86<<2)}, data_in);       // Read from RxBD register
527
  WishboneRead({22'h01, (10'h87<<2)}, data_in);       // Read from RxBD register
528 15 mohor
 
529
 
530
 
531 157 mohor
  #100000 $stop;
532
 end
533
endtask //TestTxAndRx
534 15 mohor
 
535
 
536
 
537
 
538
 
539 157 mohor
task TestFullDuplex;
540 108 mohor
 
541
 integer ii, jj;
542
 integer data_in, bd, pointer;
543 157 mohor
 integer addr;
544 108 mohor
 
545 51 billditt
 begin
546 66 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
547
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
548
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
549 51 billditt
 
550 157 mohor
  WishboneWrite(32'h0000a40b, {26'h0, `ETH_MODER_ADR<<2});     // CrcEn, Pad en, full duplex, reject broadcast, RxEn, TxEn
551 51 billditt
 
552 108 mohor
  WishboneWrite(32'h00000002, {26'h0, `ETH_MAC_ADDR1_ADR<<2}); // MAC = 000203040506
553
  WishboneWrite(32'h03040506, {26'h0, `ETH_MAC_ADDR0_ADR<<2});
554
 
555 157 mohor
  initialize_txbd(5);
556
  initialize_rxbd(6);
557
 
558
  send_packet(48'h000123456789, 16'h0064);
559 108 mohor
 
560 157 mohor
 
561
  /*
562
  for(ii=0; ii<12; ii=ii+1) begin
563
    addr = 32'h400 + ii*4;
564
    WishboneRead(addr, data_in);
565
    $display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, ii, data_in);
566
  end
567 108 mohor
 
568 157 mohor
  for(ii=0; ii<14; ii=ii+1) begin
569
    addr = 32'h600 + ii*4;
570
    WishboneRead(addr, data_in);
571
    $display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, ii, data_in);
572
  end
573
  */
574 108 mohor
 
575 157 mohor
//  WishboneRead({22'h01, 10'b0}, data_in);  // read back
576
//  WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd);       // Read from TxBD
577
 
578
/*
579
  for(jj=0; jj<8; jj=jj+4)
580
    WishboneWriteData(`TX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
581 108 mohor
 
582 157 mohor
  for(jj=0; jj<8; jj=jj+4)
583
    WishboneWriteData(`RX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
584 108 mohor
 
585
 
586
fork
587
  begin
588 157 mohor
  SendPacketX(16'h0064, 1'b0, 2'h1);
589
  SendPacketX(16'h0065, 1'b0, 2'h2);
590
  SendPacketX(16'h0066, 1'b0, 2'h3);
591
  SendPacketX(16'h0067, 1'b0, 2'h0);
592 108 mohor
  end
593
 
594
  begin
595
    ReceivePacketX(16'h0040, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
596 157 mohor
    ReceivePacketX(16'h0041, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
597
    ReceivePacketX(16'h0042, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
598
    ReceivePacketX(16'h0043, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
599
    ReceivePacketX(16'h0044, 1'b0, `UNICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
600 108 mohor
  end
601 157 mohor
*/
602 108 mohor
 
603 157 mohor
//fork
604
/*
605 108 mohor
  begin
606 157 mohor
    repeat(4)
607
      begin
608
        wait(tb_eth_top.ethtop.wishbone.TxStatusWrite);   // wait until tx status is written
609
        @ (posedge WB_CLK_I)
610
        #1;
611
      end
612 108 mohor
  end
613 157 mohor
*/
614
 
615
/*
616 108 mohor
  begin
617
    wait(tb_eth_top.ethtop.wishbone.RxStatusWrite);   // wait until rx status is written
618
  end
619 157 mohor
 
620 108 mohor
join
621 157 mohor
*/
622 108 mohor
 
623
/*
624 51 billditt
  SendPacket(16'h0013, 1'b0);
625
  SendPacket(16'h0014, 1'b0);
626 15 mohor
 
627 51 billditt
  SendPacket(16'h0030, 1'b0);
628
  SendPacket(16'h0031, 1'b0);
629
  SendPacket(16'h0032, 1'b0);
630
  SendPacket(16'h0033, 1'b0);
631
  SendPacket(16'h0025, 1'b0);
632 108 mohor
  SendPacket(16'h0045, 1'b0);
633 51 billditt
  SendPacket(16'h0025, 1'b0);
634
  SendPacket(16'h0017, 1'b0);
635 108 mohor
*/
636 41 mohor
 
637 108 mohor
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h3);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
638
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h2);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
639
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h1);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
640
//  ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
641 41 mohor
 
642 108 mohor
//  ReceivePacket(16'h0050, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
643
//  ReceivePacket(16'h0051, 1'b0, `UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
644
//  ReceivePacket(16'h0052, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
645
//  ReceivePacket(16'h0053, 1'b0, `BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
646
//  ReceivePacket(16'h0054, 1'b0, `UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
647
//  ReceivePacket(16'h0055, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
648
//  ReceivePacket(16'h0056, 1'b0, `UNICAST_WRONG_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
649 49 mohor
 
650 51 billditt
 
651 108 mohor
  repeat(1000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
652 51 billditt
 
653 108 mohor
//  WishboneRead({24'h04, (8'h0<<2)}, RxBD);       // Read from TxBD register
654
//  WishboneRead({24'h04, (8'h1<<2)}, RxBD);       // Read from TxBD register
655
//  WishboneRead({24'h04, (8'h2<<2)}, RxBD);       // Read from TxBD register
656
//  WishboneRead({24'h04, (8'h3<<2)}, RxBD);       // Read from TxBD register
657
//  WishboneRead({24'h04, (8'h4<<2)}, RxBD);       // Read from TxBD register
658 66 mohor
 
659 157 mohor
/*
660 108 mohor
  for(jj=0; jj<3; jj=jj+1)    // How many TxBD do we want to read?
661
  begin
662
 
663
      WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd);       // Read from TxBD
664
      $display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, jj, bd);
665
      if(~bd[15]) // Ready = 0?
666
        begin
667
          WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2+1'h1)<<2)}, pointer);  // Read TxBD pointer
668
          $display("\t\t\tRead TxBDPointer 0x=%x", pointer);
669
          $write("\t\t\tData:");
670
          for(ii=0; ii<bd[31:16]; ii=ii+4)
671
            begin
672
              WishboneReadData({pointer[31:2], 2'h0}+ii, data_in);        // Read data from Tx Pointer
673
              $write("\t0x%x", data_in);
674
            end
675
        end
676
  end
677
 
678
 
679
  for(jj=0; jj<3; jj=jj+1)    // How many RxBD do we want to read?
680
  begin
681
 
682
      WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2)<<2)}, bd);       // Read from RxBD
683
      $display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, jj, bd);
684
      if(~bd[15]) // Empty = 0?
685
        begin
686
          WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2+1'h1)<<2)}, pointer);  // Read RxBD pointer
687
          $display("\t\t\tRead RxBDPointer 0x=%x", pointer);
688
          $write("\t\t\tData:");
689
          for(ii=0; ii<bd[31:16]+4; ii=ii+4)
690
            begin
691
              WishboneReadData({pointer[31:2], 2'h0} + ii, data_in);        // Read data from Rx Pointer
692
              $write("\t0x%x", data_in);
693
            end
694
        end
695
  end
696
 
697
  WishboneRead({22'h01, (10'h81<<2)}, data_in);       // Read from RxBD register
698
  WishboneRead({22'h01, (10'h82<<2)}, data_in);       // Read from RxBD register
699
  WishboneRead({22'h01, (10'h83<<2)}, data_in);       // Read from RxBD register
700
  WishboneRead({22'h01, (10'h84<<2)}, data_in);       // Read from RxBD register
701
  WishboneRead({22'h01, (10'h85<<2)}, data_in);       // Read from RxBD register
702
  WishboneRead({22'h01, (10'h86<<2)}, data_in);       // Read from RxBD register
703
  WishboneRead({22'h01, (10'h87<<2)}, data_in);       // Read from RxBD register
704 157 mohor
*/
705 108 mohor
 
706
 
707 51 billditt
  #100000 $stop;
708 66 mohor
 end
709 157 mohor
endtask //TestFullDuplex
710 51 billditt
 
711 66 mohor
 
712 157 mohor
 
713
task initialize_txbd;
714
  input [6:0] txbd_num;
715
 
716
  integer i, j;
717
  integer bd_status_addr, buf_addr, bd_ptr_addr;
718
 
719
  for(i=0; i<txbd_num; i=i+1) begin
720
    buf_addr = `TX_BUF_BASE + i * 32'h600;
721
    bd_status_addr = `TX_BD_BASE + i * 8;
722
    bd_ptr_addr = bd_status_addr + 4;
723
 
724
    // Initializing BD - status
725
    if(i==txbd_num-1)
726
      WishboneWrite(32'h00007800, bd_status_addr);  // last BD: + WRAP
727
    else
728
      WishboneWrite(32'h00005800, bd_status_addr);  // IRQ + PAD + CRC
729
 
730
    WishboneWrite(buf_addr, bd_ptr_addr);   // Initializing BD - pointer
731
  end
732
endtask // initialize_txbd
733
 
734
 
735
task initialize_rxbd;
736
  input [6:0] rxbd_num;
737
 
738
  integer i, j;
739
  integer bd_status_addr, buf_addr, bd_ptr_addr;
740
 
741
  for(i=0; i<rxbd_num; i=i+1) begin
742
    buf_addr = `RX_BUF_BASE + i * 32'h600;
743
    bd_status_addr = `RX_BD_BASE + i * 8;
744
    bd_ptr_addr = bd_status_addr + 4;
745
 
746
    // Initializing BD - status
747
    if(i==rxbd_num-1)
748
      WishboneWrite(32'h0000e000, bd_status_addr);  // last BD: + WRAP
749
    else
750
      WishboneWrite(32'h0000c000, bd_status_addr);  // IRQ + PAD + CRC
751
 
752
    WishboneWrite(buf_addr, bd_ptr_addr);   // Initializing BD - pointer
753
  end
754
endtask // initialize_rxbd
755
 
756
 
757
 
758
 
759
 
760
 
761 108 mohor
reg [7:0] LateCollisionCounter;
762
reg EnableCollisionCounter;
763
// Making a late collision
764
 
765
initial
766
EnableCollisionCounter =0;  // Collision = OFF
767
 
768
always @ (posedge MTxClk)
769
begin
770
  if(tb_eth_top.ethtop.wishbone.TxStartFrm)
771
    begin
772
      LateCollisionCounter = 0;
773
    end
774
  else
775
  if(EnableCollisionCounter)
776
    LateCollisionCounter = LateCollisionCounter + 1;
777
end
778
 
779
// Making a late collision
780
always @ (posedge MTxClk)
781
begin
782
  if(LateCollisionCounter==0)
783
    MColl = 0;
784
  else
785
  if(LateCollisionCounter==150)
786
    MColl = 1;
787
  else
788
  if(LateCollisionCounter==155)
789
    begin
790
      MColl = 0;
791
      MCrs = 0;
792
      EnableCollisionCounter=0;
793
      LateCollisionCounter=1;
794
    end
795
end
796
 
797
 
798
// Switching Carrier Sense ON and OFF
799
always @ (posedge MTxClk)
800
begin
801
  wait(tb_eth_top.ethtop.wishbone.TxStartFrm);
802
  MCrs=1;
803
  wait(tb_eth_top.ethtop.wishbone.TxEndFrm || !MCrs);
804
  MCrs=0;
805
end
806
 
807
 
808 51 billditt
task TestUnicast;
809 108 mohor
 
810
 integer ii, jj;
811
 integer data_in, bd, pointer;
812
 
813 51 billditt
 begin
814
  $display("\nBegin TestUnicast \n");
815
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
816
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
817
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
818 108 mohor
  WishboneWrite(32'h0000204b, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, CrcEn, no Pad, r_IFG, promisc off, broadcast off
819
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
820 51 billditt
 
821 66 mohor
  $display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
822 51 billditt
 
823 66 mohor
  ReceivePacket(16'h0014, 1'b0,`UNICAST_XFR);
824 51 billditt
 
825 108 mohor
  WishboneWrite(32'h03040506, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address 
826
  WishboneWrite(32'h00000002, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
827 51 billditt
 
828
  $display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
829
 
830 66 mohor
  ReceivePacket(16'h0015, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
831 108 mohor
  ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR);  // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
832 66 mohor
  ReceivePacket(16'h0017, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
833 108 mohor
  ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR);  // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
834
  ReceivePacket(16'h0019, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
835 41 mohor
 
836
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
837
 
838 108 mohor
  WishboneRead({26'h0, `ETH_MODER_ADR}, data_in);   // Read from MODER register
839 41 mohor
 
840 108 mohor
  WishboneRead({22'h01, (10'h80<<2)}, data_in);       // Read from RxBD register
841
  WishboneRead({22'h01, (10'h81<<2)}, data_in);       // Read from RxBD register
842
  WishboneRead({22'h01, (10'h82<<2)}, data_in);       // Read from RxBD register
843
  WishboneRead({22'h01, (10'h83<<2)}, data_in);       // Read from RxBD register
844
  WishboneRead({22'h01, (10'h84<<2)}, data_in);       // Read from RxBD register
845
  WishboneRead({22'h01, (10'h85<<2)}, data_in);       // Read from RxBD register
846
  WishboneRead({22'h01, (10'h86<<2)}, data_in);       // Read from RxBD register
847
  WishboneRead({22'h01, (10'h87<<2)}, data_in);       // Read from RxBD register
848
  WishboneRead({22'h01, (10'h88<<2)}, data_in);       // Read from RxBD register
849
  WishboneRead({22'h01, (10'h89<<2)}, data_in);       // Read from RxBD register
850
 
851
 
852
  for(jj=0; jj<5; jj=jj+1)    // How many RxBD do we want to read?
853
  begin
854
 
855
      WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2)<<2)}, bd);       // Read from RxBD
856
      $display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, jj, bd);
857
      if(~bd[15]) // Empty = 0?
858
        begin
859
          WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2+1'h1)<<2)}, pointer);  // Read RxBD pointer
860
          $display("\t\t\tRead RxBDPointer 0x=%x", pointer);
861
          $write("\t\t\tData:");
862
          for(ii=0; ii<bd[31:16]+4; ii=ii+4)
863
            begin
864
              WishboneReadData({pointer[31:2], 2'h0} + ii, data_in);        // Read data from Rx Pointer
865
              $write("\t0x%x", data_in);
866
            end
867
        end
868
  end
869
 
870
 
871 51 billditt
 
872
  #100000 $stop;
873
  $display("\nEnd TestUnicast \n");
874
end
875
endtask //TestUnicast
876 41 mohor
 
877 51 billditt
task TestMulticast;
878 108 mohor
 
879
  integer data_in;
880
 
881 51 billditt
 begin
882
  $display("\nBegin TestMulticast \n");
883
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
884
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
885
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
886 66 mohor
  WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, CrcEn, No Pad, r_IFG, promiscuos off, broadcast enable
887
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
888 51 billditt
 
889 66 mohor
  $display("\n This Multicast packet will be rejected by Hash Filter\n");
890 51 billditt
 
891 66 mohor
  ReceivePacket(16'h0014, 1'b0,`MULTICAST_XFR);
892 51 billditt
 
893
  WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
894 108 mohor
  WishboneRead({26'h0, `ETH_HASH1_ADR, 2'h0}, data_in);  // read back
895 51 billditt
 
896
  $display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
897
 
898 66 mohor
  ReceivePacket(16'h0015, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
899
  ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
900
  ReceivePacket(16'h0017, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
901
  ReceivePacket(16'h0018, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
902 51 billditt
 
903
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
904
 
905 108 mohor
  WishboneRead({26'h0, `ETH_MODER_ADR}, data_in);   // Read from MODER register
906 51 billditt
 
907 108 mohor
  WishboneRead({22'h01, (10'h80<<2)}, data_in);       // Read from RxBD register
908
  WishboneRead({22'h01, (10'h81<<2)}, data_in);       // Read from RxBD register
909
  WishboneRead({22'h01, (10'h82<<2)}, data_in);       // Read from RxBD register
910
  WishboneRead({22'h01, (10'h83<<2)}, data_in);       // Read from RxBD register
911
  WishboneRead({22'h01, (10'h84<<2)}, data_in);       // Read from RxBD register
912
  WishboneRead({22'h01, (10'h85<<2)}, data_in);       // Read from RxBD register
913
  WishboneRead({22'h01, (10'h86<<2)}, data_in);       // Read from RxBD register
914
  WishboneRead({22'h01, (10'h87<<2)}, data_in);       // Read from RxBD register
915
 
916 66 mohor
  $display("\nEnd TestMulticast \n");
917 108 mohor
  #100000 $stop;
918 41 mohor
end
919 51 billditt
endtask //TestMulticast
920 41 mohor
 
921
 
922 51 billditt
task TestBroadcast;
923 108 mohor
 
924
  integer data_in;
925
 
926 51 billditt
 begin
927 66 mohor
  $display("\n\n\nBegin TestBroadcast");
928 51 billditt
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
929
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
930
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
931 41 mohor
 
932 66 mohor
  WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0});     // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
933
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
934 51 billditt
 
935 66 mohor
  $display("\nThis Broadcast packet will be rejected, r_BRO = 1");
936
  ReceivePacket(16'h0014, 1'b0,`BROADCAST_XFR);
937 51 billditt
 
938 66 mohor
  $display("\nSet r_Bro = 0, resend packet");
939
  WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0});  // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
940
  ReceivePacket(16'h0015, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
941 51 billditt
 
942 66 mohor
  $display("\n This Broadcast packet will be rejected, r_BRO = 1");
943
  WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0});     // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
944
  ReceivePacket(16'h0016, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
945
  ReceivePacket(16'h0017, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
946 51 billditt
 
947 66 mohor
  $display("\n Set r_Bro = 0, resend packet");
948
  WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0});  // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
949
  ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
950 51 billditt
 
951
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
952
 
953 108 mohor
  WishboneRead({26'h0, `ETH_MODER_ADR}, data_in);   // Read from MODER register
954 51 billditt
 
955 108 mohor
  WishboneRead({22'h01, (10'h80<<2)}, data_in);       // Read from RxBD register
956
  WishboneRead({22'h01, (10'h81<<2)}, data_in);       // Read from RxBD register
957
  WishboneRead({22'h01, (10'h82<<2)}, data_in);       // Read from RxBD register
958
  WishboneRead({22'h01, (10'h83<<2)}, data_in);       // Read from RxBD register
959
  WishboneRead({22'h01, (10'h84<<2)}, data_in);       // Read from RxBD register
960
  WishboneRead({22'h01, (10'h85<<2)}, data_in);       // Read from RxBD register
961
  WishboneRead({22'h01, (10'h86<<2)}, data_in);       // Read from RxBD register
962
  WishboneRead({22'h01, (10'h87<<2)}, data_in);       // Read from RxBD register
963 51 billditt
 
964
  #100000 $stop;
965
  $display("\nEnd TestBroadcast \n");
966
end
967
endtask //TestBroadcast
968
 
969
 
970 41 mohor
always @ (posedge WB_CLK_I)
971
begin
972
  if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
973
    begin
974 157 mohor
      repeat(2) @ (posedge WB_CLK_I);
975 41 mohor
        begin
976 66 mohor
          m_wb_ack_i <=#Tp 1'b1;
977 41 mohor
          if(~m_wb_we_o)
978
            begin
979 108 mohor
              #Tp;
980
              if(m_wb_adr_o[1:0] == 2'b00)       // word access
981
                begin
982
                  m_wb_dat_i[31:24] = memory3[{m_wb_adr_o[31:2], 2'h0}];
983
                  m_wb_dat_i[23:16] = memory2[{m_wb_adr_o[31:2], 2'h0}];
984
                  m_wb_dat_i[15:08] = memory1[{m_wb_adr_o[31:2], 2'h0}];
985
                  m_wb_dat_i[07:00] = memory0[{m_wb_adr_o[31:2], 2'h0}];
986
                end
987
              else if(m_wb_adr_o[1:0] == 2'b10)       // half access
988
                begin
989
                  m_wb_dat_i[31:24] = 0;
990
                  m_wb_dat_i[23:16] = 0;
991
                  m_wb_dat_i[15:08] = memory1[{m_wb_adr_o[31:2], 2'h0}];
992
                  m_wb_dat_i[07:00] = memory0[{m_wb_adr_o[31:2], 2'h0}];
993
                end
994
              else if(m_wb_adr_o[1:0] == 2'b01)       // byte access
995
                begin
996
                  m_wb_dat_i[31:24] = 0;
997
                  m_wb_dat_i[23:16] = memory2[{m_wb_adr_o[31:2], 2'h0}];
998
                  m_wb_dat_i[15:08] = 0;
999
                  m_wb_dat_i[07:00] = 0;
1000
                end
1001
              else if(m_wb_adr_o[1:0] == 2'b11)       // byte access
1002
                begin
1003
                  m_wb_dat_i[31:24] = 0;
1004
                  m_wb_dat_i[23:16] = 0;
1005
                  m_wb_dat_i[15:08] = 0;
1006
                  m_wb_dat_i[07:00] = memory0[{m_wb_adr_o[31:2], 2'h0}];
1007
                end
1008
 
1009 41 mohor
              $fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
1010
            end
1011
          else
1012 108 mohor
            begin
1013
              $fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
1014
              if(m_wb_sel_o[0])
1015
                memory0[m_wb_adr_o] = m_wb_dat_o[7:0];
1016
              if(m_wb_sel_o[1])
1017
                memory1[m_wb_adr_o] = m_wb_dat_o[15:8];
1018
              if(m_wb_sel_o[2])
1019
                memory2[m_wb_adr_o] = m_wb_dat_o[23:16];
1020
              if(m_wb_sel_o[3])
1021
                memory3[m_wb_adr_o] = m_wb_dat_o[31:24];
1022
            end
1023 41 mohor
        end
1024
      @ (posedge WB_CLK_I);
1025
      m_wb_ack_i <=#Tp 1'b0;
1026
    end
1027
end
1028
 
1029 108 mohor
 
1030
 
1031
// Detecting ram_oe and ram_we being active at the same time
1032 41 mohor
always @ (posedge WB_CLK_I)
1033
begin
1034 108 mohor
  if(tb_eth_top.ethtop.wishbone.ram_we & tb_eth_top.ethtop.wishbone.ram_oe)
1035
    begin
1036
      $display("\n\n(%0t)ERROR: ram_we and ram_oe both activated at the same time", $time);
1037
      #1000;
1038
      $stop;
1039
    end
1040 41 mohor
end
1041
 
1042 108 mohor
 
1043
 
1044
 
1045 41 mohor
always @ (posedge WB_CLK_I)
1046
  if(tb_eth_top.ethtop.wishbone.RxStatusWrite)
1047
    $fdisplay(mcd2, "");  // newline added
1048
 
1049
task WishboneWrite;
1050
  input [31:0] Data;
1051
  input [31:0] Address;
1052
  integer ii;
1053
 
1054
  begin
1055
    wait (~WishboneBusy);
1056
    WishboneBusy = 1;
1057
    @ (posedge WB_CLK_I);
1058
    #1;
1059
    WB_ADR_I = Address;
1060
    WB_DAT_I = Data;
1061
    WB_WE_I  = 1'b1;
1062
    WB_CYC_I = 1'b1;
1063
    WB_STB_I = 1'b1;
1064
    WB_SEL_I = 4'hf;
1065
 
1066
 
1067
    wait(WB_ACK_O);   // waiting for acknowledge response
1068
 
1069
    // Writing information about the access to the screen
1070
    @ (posedge WB_CLK_I);
1071 108 mohor
    if(LogEnable)
1072
    begin
1073 41 mohor
      if(~Address[11] & ~Address[10])
1074
        $write("\n(%0t) Write to register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, Data, Address);
1075
      else
1076
      if(~Address[11] & Address[10])
1077
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
1078
          begin
1079
            $write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
1080 66 mohor
            if(Address[9:2] == tb_eth_top.ethtop.r_TxBDNum-2'h2)
1081
              $write("(%0t) Send Control packet\n", $time);
1082 41 mohor
          end
1083
        else
1084
          $write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
1085
      else
1086
        $write("\n(%0t) WB write ??????????????     Data: 0x%x      Addr: 0x%0x", $time, Data, Address);
1087 108 mohor
    end
1088
 
1089 41 mohor
    #1;
1090
    WB_ADR_I = 32'hx;
1091
    WB_DAT_I = 32'hx;
1092
    WB_WE_I  = 1'bx;
1093
    WB_CYC_I = 1'b0;
1094
    WB_STB_I = 1'b0;
1095
    WB_SEL_I = 4'hx;
1096
    #5 WishboneBusy = 0;
1097
  end
1098
endtask
1099
 
1100
 
1101
task WishboneRead;
1102
  input [31:0] Address;
1103 108 mohor
  output[31:0] data;
1104 41 mohor
 
1105
  begin
1106
    wait (~WishboneBusy);
1107
    WishboneBusy = 1;
1108
    @ (posedge WB_CLK_I);
1109
    #1;
1110
    WB_ADR_I = Address;
1111
    WB_WE_I  = 1'b0;
1112
    WB_CYC_I = 1'b1;
1113
    WB_STB_I = 1'b1;
1114
    WB_SEL_I = 4'hf;
1115 108 mohor
    #3;
1116 41 mohor
    wait(WB_ACK_O);   // waiting for acknowledge response
1117
    @ (posedge WB_CLK_I);
1118 108 mohor
      data = WB_DAT_O;
1119 41 mohor
      if(~Address[11] & ~Address[10])
1120 108 mohor
//        $write("\n(%0t) Read from register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, WB_DAT_O, Address);
1121
        $write("\n(%0t) Read from register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, data, Address);
1122 41 mohor
      else
1123
      if(~Address[11] & Address[10])
1124
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
1125 108 mohor
//          ; //$write("\n(%0t) Read from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
1126
          ; //$write("\n(%0t) Read from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, data, Address);
1127 41 mohor
        else
1128 108 mohor
//          ;//$write("\n(%0t) Read from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
1129
          ;//$write("\n(%0t) Read from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, data, Address);
1130 41 mohor
      else
1131 108 mohor
//        $write("\n(%0t) WB read  ?????????    Data: 0x%x      Addr: 0x%0x", $time, WB_DAT_O, Address);
1132
        $write("\n(%0t) WB read  ?????????    Data: 0x%x      Addr: 0x%0x", $time, data, Address);
1133 41 mohor
    #1;
1134
    WB_ADR_I = 32'hx;
1135
    WB_WE_I  = 1'bx;
1136
    WB_CYC_I = 1'b0;
1137
    WB_STB_I = 1'b0;
1138
    WB_SEL_I = 4'hx;
1139
    #5 WishboneBusy = 0;
1140
  end
1141
endtask
1142
 
1143
 
1144
 
1145 108 mohor
task WishboneReadData;
1146
  input [31:0] Address;
1147
  output[31:0] data;
1148 41 mohor
 
1149 108 mohor
  begin
1150
    @ (posedge WB_CLK_I);
1151
    data = {memory3[Address], memory2[Address], memory1[Address], memory0[Address]};
1152
    #5;
1153
  end
1154
endtask
1155
 
1156
 
1157
task WishboneWriteData;
1158
  input [31:0] Address;
1159
  input [31:0] data;
1160
  input [3:0]  Select;
1161
 
1162
  begin
1163
    @ (posedge WB_CLK_I);
1164
    if(Select[0])
1165
      memory0[Address] = data[7:0];
1166
    if(Select[1])
1167
      memory1[Address] = data[15:8];
1168
    if(Select[2])
1169
      memory2[Address] = data[23:16];
1170
    if(Select[3])
1171
      memory3[Address] = data[31:24];
1172
//    $display("\n(%0t) Write data to memory (Data: 0x%x, Addr: 0x%0x)", $time, data, Address);
1173
    #5;
1174
  end
1175
endtask
1176
 
1177
 
1178
 
1179
 
1180 41 mohor
task SendPacket;
1181
  input [15:0]  Length;
1182
  input         ControlFrame;
1183
  reg           Wrap;
1184
  reg [31:0]    TempAddr;
1185
  reg [31:0]    TempData;
1186 108 mohor
  reg [31:0]    kk;
1187 41 mohor
 
1188
  begin
1189
//    if(TxBDIndex == 6)    // Only 3 buffer descriptors are used 
1190
//      Wrap = 1'b1;
1191
//    else
1192
      Wrap = 1'b0;    // At the moment no wrap bit is set
1193
 
1194
 
1195 108 mohor
    // Writing data to buffer
1196
    for(kk=0; kk<Length; kk=kk+4)
1197
    begin
1198
      TempAddr = `TX_BUF_BASE + TxBDIndex * 32'h600 + kk;
1199
      TempData = {kk[7:0], kk[7:0]+2'h1, kk[7:0]+2'h2, kk[7:0]+2'h3};
1200
      WishboneWriteData(TempAddr, TempData, 4'hf); // Writing Data to buffer that is pointed by the BD
1201
    end
1202
 
1203 41 mohor
 
1204 108 mohor
    // Writing buffer pointer
1205
    TempAddr = {22'h01, ((TxBDIndex*2'h2 + 1'b1)<<2)};
1206
    TempData = `TX_BUF_BASE + TxBDIndex * 32'h600; // 1536 bytes is reserved for one frame
1207
    WishboneWrite(TempData, TempAddr); // Writing Tx pointer
1208 41 mohor
 
1209 108 mohor
    TempAddr = {22'h01, ((TxBDIndex*2'h2)<<2)};
1210 41 mohor
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
1211
 
1212
    #1;
1213
//    if(TxBDIndex == 6)    // Only 4 buffer descriptors are used
1214
//      TxBDIndex = 0;
1215
//    else
1216 108 mohor
      TxBDIndex = TxBDIndex + 1;
1217 41 mohor
 
1218
    WishboneWrite(TempData, TempAddr); // Writing status to TxBD
1219
  end
1220
endtask
1221
 
1222
 
1223
 
1224 108 mohor
task SendPacketX;
1225
  input [15:0]  Length;
1226
  input         ControlFrame;
1227
  input  [1:0]  AddrOffset;
1228
  reg           Wrap;
1229
  reg [31:0]    TempAddr;
1230
  reg [31:0]    TempData;
1231
  reg [31:0]    kk;
1232
  reg  [3:0]    Select;
1233
 
1234
  begin
1235
    Wrap = 1'b0;
1236
 
1237
    case(AddrOffset)
1238
      2'h0 : Select = 4'hf;
1239
      2'h1 : Select = 4'h7;
1240
      2'h2 : Select = 4'h3;
1241
      2'h3 : Select = 4'h1;
1242
    endcase
1243
 
1244
    // Writing data to buffer
1245
    for(kk=0; kk<Length+4; kk=kk+4)   // Length+4 is because we might start up to 3 bytes later
1246
    begin
1247
      if(kk>0)
1248
        Select = 4'hf;
1249
      TempAddr = `TX_BUF_BASE + TxBDIndex * 32'h600 + kk;
1250
      TempData = {kk[7:0]+3'h1, kk[7:0]+3'h2, kk[7:0]+3'h3, kk[7:0]+3'h4};
1251
      WishboneWriteData(TempAddr, TempData, Select); // Writing Data to buffer that is pointed by the BD
1252
    end
1253
 
1254
 
1255
    // Writing buffer pointer
1256
    TempAddr = {22'h01, ((TxBDIndex*2'h2 + 1'b1)<<2)};
1257
    TempData = `TX_BUF_BASE + TxBDIndex * 32'h600 + AddrOffset; // 1536 bytes is reserved for one frame
1258
    WishboneWrite(TempData, TempAddr); // Writing Tx pointer
1259
 
1260
    TempAddr = {22'h01, ((TxBDIndex*2'h2)<<2)};
1261
    TempData = {Length[15:0], 1'b1, 1'b1, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready, interrupt and Wrap = 1
1262
 
1263
    #1;
1264
    if(Wrap)
1265
      TxBDIndex = 0;
1266
    else
1267
      TxBDIndex = TxBDIndex + 1;
1268
 
1269
    WishboneWrite(TempData, TempAddr); // Writing status to TxBD
1270
  end
1271
endtask
1272
 
1273
 
1274 157 mohor
task send_packet;
1275
  input [47:0] dest_addr;
1276
  input [15:0] length;
1277 108 mohor
 
1278 157 mohor
  reg [31:0] BD, ptr;
1279
  reg [31:0] i;
1280
  reg [2:0]  increment;
1281
 
1282
  reg [31:0]    TempAddr;
1283
  reg [31:0]    TempData;
1284
  reg [15:0]    kk;
1285
  reg  [3:0]    Select;
1286
 
1287
  begin
1288
    bd_status_addr = `TX_BD_BASE + g_last_txbd * 8;
1289
 
1290
    mama
1291
    WishboneRead(bd_status_addr, BD);           // Read BD
1292
    WishboneRead(bd_status_addr+4, ptr);        // Read buffer pointer
1293
 
1294
    case(ptr[1:0])
1295
      2'h0 : begin Select = 4'hf; increment = 3'h4 end
1296
      2'h1 : begin Select = 4'h7; increment = 3'h3 end
1297
      2'h2 : begin Select = 4'h3; increment = 3'h2 end
1298
      2'h3 : begin Select = 4'h1; increment = 3'h1 end
1299
    endcase
1300
 
1301
    // Writing data to buffer
1302
    for(i=ptr; i<(length+ptr); i=i+increment)   // (i=0; i<length; i=i+increment)
1303
    begin
1304
      if(i>ptr)   // After first write all accesses are word accesses
1305
        begin Select = 4'hf; increment=3'h4; end
1306
 
1307
      TempAddr = `TX_BUF_BASE + TxBDIndex * 32'h600 + kk;
1308
      TempData = {i[7:0]+3'h1, i[7:0]+3'h2, i[7:0]+3'h3, i[7:0]+3'h4};
1309
mama
1310
      WishboneWriteData(TempAddr, TempData, Select); // Writing Data to buffer that is pointed by the BD
1311
    end
1312
 
1313
 
1314
    // Writing buffer pointer
1315
    TempAddr = {22'h01, ((TxBDIndex*2'h2 + 1'b1)<<2)};
1316
    TempData = `TX_BUF_BASE + TxBDIndex * 32'h600 + AddrOffset; // 1536 bytes is reserved for one frame
1317
    WishboneWrite(TempData, TempAddr); // Writing Tx pointer
1318
 
1319
    TempAddr = {22'h01, ((TxBDIndex*2'h2)<<2)};
1320
    TempData = {length[15:0], 1'b1, 1'b1, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready, interrupt and Wrap = 1
1321
 
1322
    #1;
1323
    if(Wrap)
1324
      TxBDIndex = 0;
1325
    else
1326
      TxBDIndex = TxBDIndex + 1;
1327
 
1328
    WishboneWrite(TempData, TempAddr); // Writing status to TxBD
1329
 
1330
    if(BD & 32'h2000)     // Wrap bit set ?
1331
      g_last_txbd = 0;
1332
    else
1333
      g_last_txbd = g_last_txbd+1;
1334
 
1335
  end
1336
endtask // send_packet
1337
 
1338
 
1339 41 mohor
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
1340
  input [15:0] LengthRx;
1341
  input        RxControlFrame;
1342 51 billditt
  input [31:0] TransferType;  //Broadcast,Unicast,Multicast
1343 41 mohor
  reg        WrapRx;
1344
  reg [31:0] TempRxAddr;
1345 108 mohor
//  reg [31:0] TempRxData;
1346
  integer TempRxData;
1347 41 mohor
  reg abc;
1348
  begin
1349
//    if(RxBDIndex == 6)    // Only 3 buffer descriptors are used
1350
//      WrapRx = 1'b1;
1351
//    else
1352
      WrapRx = 1'b0;
1353
 
1354 108 mohor
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex*2'h2 + 1'b1)<<2)};
1355
    TempRxData = `RX_BUF_BASE + RxBDIndex * 32'h600; // 1536 bytes is reserved for one frame
1356 41 mohor
    WishboneWrite(TempRxData, TempRxAddr); // Writing Rx pointer
1357
 
1358 108 mohor
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex*2'h2)<<2)};
1359 41 mohor
    TempRxData = {16'h0, 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
1360
 
1361
    #1;
1362
//    if(RxBDIndex == 6)    // Only 4 buffer descriptors are used
1363
//      RxBDIndex = 0;
1364
//    else
1365 108 mohor
      RxBDIndex = RxBDIndex + 1;
1366 41 mohor
 
1367
    abc=1;
1368
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
1369
    abc=0;
1370
 
1371
      begin
1372
        #200;
1373
        if(RxControlFrame)
1374
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
1375
        else
1376 66 mohor
          GetDataOnMRxD(LengthRx, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
1377 41 mohor
      end
1378
 
1379
  end
1380
endtask
1381
 
1382
 
1383 108 mohor
task ReceivePacketX;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
1384
  input [15:0] LengthRx;
1385
  input        RxControlFrame;
1386
  input [31:0] TransferType;  //Broadcast,Unicast,Multicast
1387
  input  [1:0]  AddrOffset;
1388
  reg        WrapRx;
1389
  reg [31:0] TempRxAddr;
1390
  integer TempRxData;
1391
  reg abc;
1392
  begin
1393
    WrapRx = 1'b0;
1394
 
1395
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex*2'h2 + 1'b1)<<2)};
1396
    TempRxData = `RX_BUF_BASE + RxBDIndex * 32'h600 + AddrOffset; // 1536 bytes is reserved for one frame
1397
    WishboneWrite(TempRxData, TempRxAddr); // Writing Rx pointer
1398
 
1399
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex*2'h2)<<2)};
1400
    TempRxData = {16'h0, 1'b1, 1'b1, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready, interrupt and WrapRx = 1 or 0
1401
 
1402
    #1;
1403
      RxBDIndex = RxBDIndex + 1;
1404
 
1405
    abc=1;
1406
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
1407
    abc=0;
1408
 
1409
      begin
1410
        #200;
1411
        if(RxControlFrame)
1412
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
1413
        else
1414
          GetDataOnMRxD(LengthRx, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
1415
      end
1416
 
1417
  end
1418
endtask
1419
 
1420
 
1421 41 mohor
task GetDataOnMRxD;
1422
  input [15:0] Len;
1423 51 billditt
  input [31:0] TransferType;
1424 41 mohor
  integer tt;
1425
 
1426
  begin
1427
    @ (posedge MRxClk);
1428
    MRxDV=1'b1;
1429
 
1430
    for(tt=0; tt<15; tt=tt+1)
1431
    begin
1432
      MRxD=4'h5;              // preamble
1433
      @ (posedge MRxClk);
1434
    end
1435
    MRxD=4'hd;                // SFD
1436 51 billditt
 
1437
  for(tt=1; tt<(Len+1); tt=tt+1)
1438
 
1439 41 mohor
    begin
1440 51 billditt
 
1441 41 mohor
      @ (posedge MRxClk);
1442 51 billditt
          if(TransferType == `UNICAST_XFR && tt == 1)
1443
           MRxD= 4'h0;   // Unicast transfer
1444
          else if(TransferType == `BROADCAST_XFR && tt < 7)
1445
           MRxD = 4'hf;
1446
          else
1447
       MRxD=tt[3:0]; // Multicast transfer
1448 66 mohor
 
1449
    @ (posedge MRxClk);
1450 51 billditt
 
1451
           if(TransferType == `BROADCAST_XFR && tt < 7)
1452
            MRxD = 4'hf;
1453
          else
1454
        MRxD=tt[7:4];
1455 41 mohor
    end
1456 51 billditt
 
1457 41 mohor
    @ (posedge MRxClk);
1458
    MRxDV=1'b0;
1459
  end
1460
endtask
1461
 
1462
 
1463
task GetControlDataOnMRxD;
1464
  input [15:0] Timer;
1465
  reg [127:0] Packet;
1466
  reg [127:0] Data;
1467
  reg [31:0] Crc;
1468
  integer tt;
1469
 
1470
  begin
1471 66 mohor
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
1472 41 mohor
  Crc = 32'h6014fe08; // not a correct value
1473
 
1474
    @ (posedge MRxClk);
1475
    MRxDV=1'b1;
1476
 
1477
    for(tt=0; tt<15; tt=tt+1)
1478
    begin
1479
      MRxD=4'h5;              // preamble
1480
      @ (posedge MRxClk);
1481
    end
1482
    MRxD=4'hd;                // SFD
1483
 
1484
    for(tt=0; tt<32; tt=tt+1)
1485
    begin
1486
      Data = Packet << (tt*4);
1487
      @ (posedge MRxClk);
1488
      MRxD=Data[127:124];
1489
    end
1490
 
1491
    for(tt=0; tt<2; tt=tt+1)    // timer
1492
    begin
1493
      Data[15:0] = Timer << (tt*8);
1494
      @ (posedge MRxClk);
1495
      MRxD=Data[11:8];
1496
      @ (posedge MRxClk);
1497
      MRxD=Data[15:12];
1498
    end
1499
 
1500
    for(tt=0; tt<42; tt=tt+1)   // padding
1501
    begin
1502
      Data[7:0] = 8'h0;
1503
      @ (posedge MRxClk);
1504
      MRxD=Data[3:0];
1505
      @ (posedge MRxClk);
1506
      MRxD=Data[3:0];
1507
    end
1508
 
1509
    for(tt=0; tt<4; tt=tt+1)    // crc
1510
    begin
1511
      Data[31:0] = Crc << (tt*8);
1512
      @ (posedge MRxClk);
1513
      MRxD=Data[27:24];
1514
      @ (posedge MRxClk);
1515
      MRxD=Data[31:28];
1516
    end
1517
 
1518
 
1519
 
1520
    @ (posedge MRxClk);
1521
    MRxDV=1'b0;
1522
  end
1523
endtask
1524 66 mohor
 
1525
task InitializeMemory;
1526
  reg [9:0] mem_addr;
1527
 
1528
  begin
1529 108 mohor
    LogEnable = 1'b0;
1530
    $display("\n\n(%0t) Initializing Memory...", $time);
1531 66 mohor
    for(mem_addr=0; mem_addr<=10'h0ff; mem_addr=mem_addr+1'b1)
1532
      WishboneWrite(32'h0, {22'h01, mem_addr<<2}); // Writing status to RxBD
1533 108 mohor
    LogEnable = 1'b1;
1534 66 mohor
  end
1535
endtask
1536
 
1537
 
1538 41 mohor
 
1539
 
1540 15 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.