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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Blame information for rev 169

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1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet.v                                               ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 169 mohor
////      - Tadej Markovic, tadej@opencores.org                   ////
10 116 mohor
////                                                              ////
11 169 mohor
////  All additional information is available in the Readme.txt   ////
12 116 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001, 2002 Authors                             ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 121 mohor
// Revision 1.2  2002/07/19 14:02:47  mohor
45
// Clock mrx_clk set to 2.5 MHz.
46
//
47 117 mohor
// Revision 1.1  2002/07/19 13:57:53  mohor
48
// Testing environment also includes traffic cop, memory interface and host
49
// interface.
50 116 mohor
//
51
//
52
//
53
//
54 117 mohor
//
55 116 mohor
 
56
 
57 169 mohor
`define TIME $display("  Time: %0t", $time)
58 116 mohor
 
59 169 mohor
`include "eth_phy_defines.v"
60
`include "wb_model_defines.v"
61 116 mohor
`include "tb_eth_defines.v"
62
`include "eth_defines.v"
63
`include "timescale.v"
64
 
65
module tb_ethernet();
66
 
67
 
68 169 mohor
reg           wb_clk;
69
reg           wb_rst;
70
wire          wb_int;
71 116 mohor
 
72 169 mohor
wire          mtx_clk;  // This goes to PHY
73
wire          mrx_clk;  // This goes to PHY
74 116 mohor
 
75
wire   [3:0]  MTxD;
76
wire          MTxEn;
77
wire          MTxErr;
78
 
79 169 mohor
wire   [3:0]  MRxD;     // This goes to PHY
80
wire          MRxDV;    // This goes to PHY
81
wire          MRxErr;   // This goes to PHY
82
wire          MColl;    // This goes to PHY
83
wire          MCrs;     // This goes to PHY
84 116 mohor
 
85
wire          Mdi_I;
86
wire          Mdo_O;
87
wire          Mdo_OE;
88 169 mohor
tri           Mdio_IO;
89 116 mohor
wire          Mdc_O;
90
 
91
 
92 169 mohor
parameter Tp = 1;
93 116 mohor
 
94 121 mohor
 
95 116 mohor
// Ethernet Slave Interface signals
96 169 mohor
wire [31:0] eth_sl_wb_adr;
97 116 mohor
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
98
wire  [3:0] eth_sl_wb_sel_i;
99
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
100
 
101
// Ethernet Master Interface signals
102
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
103
wire  [3:0] eth_ma_wb_sel_o;
104
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
105
 
106
 
107
 
108
 
109
// Connecting Ethernet top module
110 169 mohor
eth_top eth_top
111 116 mohor
(
112
  // WISHBONE common
113 169 mohor
  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),
114 116 mohor
 
115
  // WISHBONE slave
116 169 mohor
  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
117
  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
118
  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
119 116 mohor
 
120
  // WISHBONE master
121
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
122
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
123
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
124
 
125
  //TX
126
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
127
 
128
  //RX
129
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
130
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
131
 
132
  // MIIM
133
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
134
 
135 169 mohor
  .int_o(wb_int)
136 116 mohor
);
137
 
138
 
139
 
140 169 mohor
// Connecting Ethernet PHY Module
141
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
142
assign Mdi_I   = Mdio_IO;
143
integer phy_log_file_desc;
144
 
145
eth_phy eth_phy
146 116 mohor
(
147 169 mohor
  // WISHBONE reset
148
  .m_rst_n_i(!wb_rst),
149 116 mohor
 
150 169 mohor
  // MAC TX
151
  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),
152
 
153
  // MAC RX
154
  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),
155
  .mcoll_o(MColl),        .mcrs_o(MCrs),
156
 
157
  // MIIM
158
  .mdc_i(Mdc_O),          .md_io(Mdio_IO),
159
 
160
  // SYSTEM
161
  .phy_log(phy_log_file_desc)
162 116 mohor
);
163
 
164
 
165 169 mohor
 
166
// Connecting WB Master as Host Interface
167
integer host_log_file_desc;
168
 
169
WB_MASTER_BEHAVIORAL wb_master
170 116 mohor
(
171 169 mohor
    .CLK_I(wb_clk),
172
    .RST_I(wb_rst),
173
    .TAG_I({`WB_TAG_WIDTH{1'b0}}),
174
    .TAG_O(),
175
    .ACK_I(eth_sl_wb_ack_o),
176
    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
177
    .CYC_O(eth_sl_wb_cyc_i),
178
    .DAT_I(eth_sl_wb_dat_o),
179
    .DAT_O(eth_sl_wb_dat_i),
180
    .ERR_I(eth_sl_wb_err_o),
181
    .RTY_I(1'b0),  // inactive (1'b0)
182
    .SEL_O(eth_sl_wb_sel_i),
183
    .STB_O(eth_sl_wb_stb_i),
184
    .WE_O (eth_sl_wb_we_i),
185
    .CAB_O()       // NOT USED for now!
186
);
187
 
188
assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
189
 
190
 
191
 
192
// Connecting WB Slave as Memory Interface Module
193
integer memory_log_file_desc;
194
 
195
WB_SLAVE_BEHAVIORAL wb_slave
196
(
197
    .CLK_I(wb_clk),
198
    .RST_I(wb_rst),
199
    .ACK_O(eth_ma_wb_ack_i),
200
    .ADR_I(eth_ma_wb_adr_o),
201
    .CYC_I(eth_ma_wb_cyc_o),
202
    .DAT_O(eth_ma_wb_dat_i),
203
    .DAT_I(eth_ma_wb_dat_o),
204
    .ERR_O(eth_ma_wb_err_i),
205
    .RTY_O(),      // NOT USED for now!
206
    .SEL_I(eth_ma_wb_sel_o),
207
    .STB_I(eth_ma_wb_stb_o),
208
    .WE_I (eth_ma_wb_we_o),
209
    .CAB_I(1'b0)   // inactive (1'b0)
210
);
211
 
212
 
213
 
214
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
215
integer wb_s_mon_log_file_desc ;
216
integer wb_m_mon_log_file_desc ;
217
 
218
WB_BUS_MON wb_eth_slave_bus_mon
219
(
220 116 mohor
  // WISHBONE common
221 169 mohor
  .CLK_I(wb_clk),
222
  .RST_I(wb_rst),
223 116 mohor
 
224 169 mohor
  // WISHBONE slave
225
  .ACK_I(eth_sl_wb_ack_o),
226
  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),
227
  .CYC_O(eth_sl_wb_cyc_i),
228
  .DAT_I(eth_sl_wb_dat_o),
229
  .DAT_O(eth_sl_wb_dat_i),
230
  .ERR_I(eth_sl_wb_err_o),
231
  .RTY_I(1'b0),
232
  .SEL_O(eth_sl_wb_sel_i),
233
  .STB_O(eth_sl_wb_stb_i),
234
  .WE_O (eth_sl_wb_we_i),
235
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
236
  .TAG_O(),
237
  .CAB_O(1'b0),
238
  .log_file_desc (wb_s_mon_log_file_desc)
239
);
240
 
241
WB_BUS_MON wb_eth_master_bus_mon
242
(
243
  // WISHBONE common
244
  .CLK_I(wb_clk),
245
  .RST_I(wb_rst),
246
 
247 116 mohor
  // WISHBONE master
248 169 mohor
  .ACK_I(eth_ma_wb_ack_i),
249
  .ADDR_O(eth_ma_wb_adr_o),
250
  .CYC_O(eth_ma_wb_cyc_o),
251
  .DAT_I(eth_ma_wb_dat_i),
252
  .DAT_O(eth_ma_wb_dat_o),
253
  .ERR_I(eth_ma_wb_err_i),
254
  .RTY_I(1'b0),
255
  .SEL_O(eth_ma_wb_sel_o),
256
  .STB_O(eth_ma_wb_stb_o),
257
  .WE_O (eth_ma_wb_we_o),
258
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
259
  .TAG_O(),
260
  .CAB_O(1'b0),
261
  .log_file_desc(wb_m_mon_log_file_desc)
262 116 mohor
);
263
 
264
 
265
 
266 169 mohor
reg         StartTB;
267
integer     tb_log_file;
268 116 mohor
 
269 169 mohor
initial
270
begin
271
  tb_log_file = $fopen("../log/eth_tb.log");
272
  if (tb_log_file < 2)
273
  begin
274
    $display("*E Could not open/create testbench log file in ../log/ directory!");
275
    $finish;
276
  end
277
  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");
278
  $fdisplay(tb_log_file, " ");
279 116 mohor
 
280 169 mohor
  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");
281
  if (phy_log_file_desc < 2)
282
  begin
283
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");
284
    $finish;
285
  end
286
  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");
287
  $fdisplay(phy_log_file_desc, " ");
288
 
289
  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");
290
  if (memory_log_file_desc < 2)
291
  begin
292
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");
293
    $finish;
294
  end
295
  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");
296
  $fdisplay(memory_log_file_desc, " ");
297
 
298
  host_log_file_desc = $fopen("../log/eth_tb_host.log");
299
  if (host_log_file_desc < 2)
300
  begin
301
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");
302
    $finish;
303
  end
304
  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");
305
  $fdisplay(host_log_file_desc, " ");
306
 
307
  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");
308
  if (wb_s_mon_log_file_desc < 2)
309
  begin
310
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");
311
    $finish;
312
  end
313
  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");
314
  $fdisplay(wb_s_mon_log_file_desc, " ");
315
  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
316
  $fdisplay(wb_s_mon_log_file_desc, " ");
317
 
318
  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");
319
  if (wb_m_mon_log_file_desc < 2)
320
  begin
321
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");
322
    $finish;
323
  end
324
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
325
  $fdisplay(wb_m_mon_log_file_desc, " ");
326
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
327
  $fdisplay(wb_m_mon_log_file_desc, " ");
328
 
329
  // Clear memories
330
  clear_memories;
331
 
332
  // Reset pulse
333
  wb_rst =  1'b1;
334
  #423 wb_rst =  1'b0;
335
  #423 StartTB  =  1'b1;
336
end
337
 
338
 
339
 
340
// Generating wb_clk clock
341 116 mohor
initial
342
begin
343 169 mohor
  wb_clk=0;
344
//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    
345
//  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    
346
//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    
347
//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    
348
//  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    
349
  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    
350
//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz
351
//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    
352
//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz
353
//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    
354 116 mohor
end
355
 
356
 
357
 
358 169 mohor
integer      tests_successfull;
359
integer      tests_failed;
360
reg [799:0]  test_name; // used for tb_log_file
361 121 mohor
 
362 169 mohor
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
363
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
364
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
365
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
366
 
367 116 mohor
initial
368
begin
369 169 mohor
  wait(StartTB);  // Start of testbench
370
 
371
  // Initial global values
372
  tests_successfull = 0;
373
  tests_failed = 0;
374
 
375
  wbm_init_waits = 4'h1;
376
  wbm_subseq_waits = 4'h3;
377
  wbs_waits = 4'h1;
378
  wbs_retries = 8'h2;
379
  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
380
 
381
 
382
  //  Call tests
383
  //  ----------
384
    test_access_to_mac_reg(0, 3);          // 0 - 3
385
    test_mii(0, 17);                        // 0 - 17
386
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
387
  eth_phy.carrier_sense_real_delay(0);
388
    test_mac_full_duplex_transmit(0, 3);   // 0 - (3)
389
 
390
  test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
391
  eth_phy.carrier_sense_real_delay(1);
392
 
393
 
394
  // Finish test's logs
395
  test_summary;
396
  $display("\n\n END of SIMULATION");
397
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
398
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);
399
 
400
  $stop;
401 116 mohor
end
402 169 mohor
 
403 116 mohor
 
404 169 mohor
 
405
//////////////////////////////////////////////////////////////
406
// Test tasks
407
//////////////////////////////////////////////////////////////
408
 
409
task test_access_to_mac_reg;
410
  input  [31:0]  start_task;
411
  input  [31:0]  end_task;
412
  integer        bit_start_1;
413
  integer        bit_end_1;
414
  integer        bit_start_2;
415
  integer        bit_end_2;
416
  integer        num_of_reg;
417
  integer        i_addr;
418
  integer        i_data;
419
  integer        i_length;
420
  integer        tmp_data;
421
  reg    [31:0]  tx_bd_num;
422
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
423
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
424
  integer        i;
425
  integer        i1;
426
  integer        i2;
427
  integer        i3;
428
  integer        fail;
429
  reg    [31:0]  addr;
430
  reg    [31:0]  data;
431
  reg    [31:0]  data_max;
432 116 mohor
begin
433 169 mohor
// ACCESS TO MAC REGISTERS TEST
434
test_heading("ACCESS TO MAC REGISTERS TEST");
435
$display(" ");
436
$display("ACCESS TO MAC REGISTERS TEST");
437
fail = 0;
438
 
439
  /* Register space
440
     --------------
441
  `define ETH_MODER      `ETH_BASE + 32'h00      Mode Register
442
  `define ETH_INT        `ETH_BASE + 32'h04      Interrupt Source Register
443
  `define ETH_INT_MASK   `ETH_BASE + 32'h08      Interrupt Mask Register
444
  `define ETH_IPGT       `ETH_BASE + 32'h0C      Back to Bak Inter Packet Gap Register
445
  `define ETH_IPGR1      `ETH_BASE + 32'h10      Non Back to Back Inter Packet Gap Register 1
446
  `define ETH_IPGR2      `ETH_BASE + 32'h14      Non Back to Back Inter Packet Gap Register 2
447
  `define ETH_PACKETLEN  `ETH_BASE + 32'h18      Packet Length Register (min. and max.)
448
  `define ETH_COLLCONF   `ETH_BASE + 32'h1C      Collision and Retry Configuration Register
449
  `define ETH_TX_BD_NUM  `ETH_BASE + 32'h20      Transmit Buffer Descriptor Number Register
450
  `define ETH_CTRLMODER  `ETH_BASE + 32'h24      Control Module Mode Register
451
  `define ETH_MIIMODER   `ETH_BASE + 32'h28      MII Mode Register
452
  `define ETH_MIICOMMAND `ETH_BASE + 32'h2C      MII Command Register
453
  `define ETH_MIIADDRESS `ETH_BASE + 32'h30      MII Address Register
454
  `define ETH_MIITX_DATA `ETH_BASE + 32'h34      MII Transmit Data Register
455
  `define ETH_MIIRX_DATA `ETH_BASE + 32'h38      MII Receive Data Register
456
  `define ETH_MIISTATUS  `ETH_BASE + 32'h3C      MII Status Register
457
  `define ETH_MAC_ADDR0  `ETH_BASE + 32'h40      MAC Individual Address Register 0
458
  `define ETH_MAC_ADDR1  `ETH_BASE + 32'h44      MAC Individual Address Register 1
459
  `define ETH_HASH_ADDR0 `ETH_BASE + 32'h48      Hash Register 0
460
  `define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C      Hash Register 1
461
  */
462
 
463
 
464
if ((start_task <= 0) && (end_task >= 0))
465
begin
466
  // TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
467
  test_name   = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
468
  `TIME; $display("  TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
469
 
470
  data = 0;
471
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
472
  begin
473
      wbm_init_waits = i;
474
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
475
      for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
476
      begin
477
        addr = `ETH_BASE + i_addr;
478
        // set ranges of R/W bits
479
        case (addr)
480
        `ETH_MODER:
481
          begin
482
            bit_start_1 = 0;
483
            bit_end_1   = 16;
484
            bit_start_2 = 32; // not used
485
            bit_end_2   = 32; // not used
486
          end
487
        `ETH_INT: // READONLY - tested within INT test
488
          begin
489
            bit_start_1 = 32; // not used
490
            bit_end_1   = 32; // not used
491
            bit_start_2 = 32; // not used
492
            bit_end_2   = 32; // not used
493
          end
494
        `ETH_INT_MASK:
495
          begin
496
            bit_start_1 = 0;
497
            bit_end_1   = 6;
498
            bit_start_2 = 32; // not used
499
            bit_end_2   = 32; // not used
500
          end
501
        `ETH_IPGT:
502
          begin
503
            bit_start_1 = 0;
504
            bit_end_1   = 6;
505
            bit_start_2 = 32; // not used
506
            bit_end_2   = 32; // not used
507
          end
508
        `ETH_IPGR1:
509
          begin
510
            bit_start_1 = 0;
511
            bit_end_1   = 6;
512
            bit_start_2 = 32; // not used
513
            bit_end_2   = 32; // not used
514
          end
515
        `ETH_IPGR2:
516
          begin
517
            bit_start_1 = 0;
518
            bit_end_1   = 6;
519
            bit_start_2 = 32; // not used
520
            bit_end_2   = 32; // not used
521
          end
522
        `ETH_PACKETLEN:
523
          begin
524
            bit_start_1 = 0;
525
            bit_end_1   = 31;
526
            bit_start_2 = 32; // not used
527
            bit_end_2   = 32; // not used
528
          end
529
        `ETH_COLLCONF:
530
          begin
531
            bit_start_1 = 0;
532
            bit_end_1   = 5;
533
            bit_start_2 = 16;
534
            bit_end_2   = 19;
535
          end
536
        `ETH_TX_BD_NUM:
537
          begin
538
            bit_start_1 = 0;
539
            bit_end_1   = 7;
540
            bit_start_2 = 32; // not used
541
            bit_end_2   = 32; // not used
542
          end
543
        `ETH_CTRLMODER:
544
          begin
545
            bit_start_1 = 0;
546
            bit_end_1   = 2;
547
            bit_start_2 = 32; // not used
548
            bit_end_2   = 32; // not used
549
          end
550
        `ETH_MIIMODER:
551
          begin
552
            bit_start_1 = 0;
553
            bit_end_1   = 9;
554
            bit_start_2 = 32; // not used
555
            bit_end_2   = 32; // not used
556
          end
557
        `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
558
          begin
559
            bit_start_1 = 32; // not used
560
            bit_end_1   = 32; // not used
561
            bit_start_2 = 32; // not used
562
            bit_end_2   = 32; // not used
563
          end
564
        `ETH_MIIADDRESS:
565
          begin
566
            bit_start_1 = 0;
567
            bit_end_1   = 4;
568
            bit_start_2 = 8;
569
            bit_end_2   = 12;
570
          end
571
        `ETH_MIITX_DATA:
572
          begin
573
            bit_start_1 = 0;
574
            bit_end_1   = 15;
575
            bit_start_2 = 32; // not used
576
            bit_end_2   = 32; // not used
577
          end
578
        `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
579
          begin
580
            bit_start_1 = 32; // not used
581
            bit_end_1   = 32; // not used
582
            bit_start_2 = 32; // not used
583
            bit_end_2   = 32; // not used
584
          end
585
        `ETH_MIISTATUS: // READONLY - tested within MIIM test
586
          begin
587
            bit_start_1 = 32; // not used
588
            bit_end_1   = 32; // not used
589
            bit_start_2 = 32; // not used
590
            bit_end_2   = 32; // not used
591
          end
592
        `ETH_MAC_ADDR0:
593
          begin
594
            bit_start_1 = 0;
595
            bit_end_1   = 31;
596
            bit_start_2 = 32; // not used
597
            bit_end_2   = 32; // not used
598
          end
599
        `ETH_MAC_ADDR1:
600
          begin
601
            bit_start_1 = 0;
602
            bit_end_1   = 15;
603
            bit_start_2 = 32; // not used
604
            bit_end_2   = 32; // not used
605
          end
606
        `ETH_HASH_ADDR0:
607
          begin
608
            bit_start_1 = 0;
609
            bit_end_1   = 31;
610
            bit_start_2 = 32; // not used
611
            bit_end_2   = 32; // not used
612
          end
613
        default: // `ETH_HASH_ADDR1:
614
          begin
615
            bit_start_1 = 0;
616
            bit_end_1   = 31;
617
            bit_start_2 = 32; // not used
618
            bit_end_2   = 32; // not used
619
          end
620
        endcase
621
        for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
622
        begin
623
          data = 1'b1 << i_data;
624
          if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
625
          begin
626
          end
627
          else
628
          begin
629
            wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
630
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
631
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
632
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
633
            begin
634
              if (tmp_data !== data)
635
              begin
636
                fail = fail + 1;
637
                test_fail("RW bit of the MAC register was not written or not read");
638
                `TIME;
639
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
640
                          wbm_init_waits, addr, data, tmp_data);
641
              end
642
            end
643
            else // data should not be equal to tmp_data
644
            begin
645
              if (tmp_data === data)
646
              begin
647
                fail = fail + 1;
648
                test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
649
                `TIME;
650
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
651
                          wbm_init_waits, addr, data, tmp_data);
652
              end
653
            end
654
          end
655
        end
656
      end
657
  end
658
  if(fail == 0)
659
    test_ok;
660
  else
661
    fail = 0;    // Errors were reported previously
662 116 mohor
end
663
 
664 169 mohor
 
665
if ((start_task <= 4) && (end_task >= 4)) // not used, since burst access to reg. is not supported
666 116 mohor
begin
667 169 mohor
/*  // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
668
  test_name   = "TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
669
  `TIME; $display("  TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
670
 
671
  data = 0;
672
  burst_data = 0;
673
  burst_tmp_data = 0;
674
  i_length = 10; // two bursts for length 20
675
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
676
  begin
677
    for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
678
    begin
679
      wbm_init_waits = i;
680
      wbm_subseq_waits = i1;
681
      #1;
682
      for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
683
      begin
684
        data = 1'b1 << i_data;
685
        #1;
686
        for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
687
        begin
688
          burst_data = burst_data << 32;
689
          // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
690
          if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
691
          begin
692
            #1 burst_data[31:0] = 0;
693
          end
694
          else
695
          begin
696
            #1 burst_data[31:0] = data;
697
          end
698
        end
699
        #1;
700
        // 2 burst writes
701
        addr = `ETH_BASE; // address of a first burst
702
        wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
703
        burst_tmp_data = burst_data >> (32 * i_length);
704
        addr = addr + 32'h28; // address of a second burst
705
        wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
706
        #1;
707
        // 2 burst reads
708
        addr = `ETH_BASE; // address of a first burst
709
        wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
710
                 wbm_init_waits, wbm_subseq_waits); // first burst
711
        burst_tmp_data = burst_tmp_data << (32 * i_length);
712
        addr = addr + 32'h28; // address of a second burst
713
        wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
714
                 wbm_init_waits, wbm_subseq_waits); // second burst
715
        #1;
716
        for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
717
        begin
718
          // set ranges of R/W bits
719
          case (`ETH_BASE + i2)
720
          `ETH_MODER:
721
            begin
722
              bit_start_1 = 0;
723
              bit_end_1   = 16;
724
              bit_start_2 = 32; // not used
725
              bit_end_2   = 32; // not used
726
            end
727
          `ETH_INT: // READONLY - tested within INT test
728
            begin
729
              bit_start_1 = 32; // not used
730
              bit_end_1   = 32; // not used
731
              bit_start_2 = 32; // not used
732
              bit_end_2   = 32; // not used
733
            end
734
          `ETH_INT_MASK:
735
            begin
736
              bit_start_1 = 0;
737
              bit_end_1   = 6;
738
              bit_start_2 = 32; // not used
739
              bit_end_2   = 32; // not used
740
            end
741
          `ETH_IPGT:
742
            begin
743
              bit_start_1 = 0;
744
              bit_end_1   = 6;
745
              bit_start_2 = 32; // not used
746
              bit_end_2   = 32; // not used
747
            end
748
          `ETH_IPGR1:
749
            begin
750
              bit_start_1 = 0;
751
              bit_end_1   = 6;
752
              bit_start_2 = 32; // not used
753
              bit_end_2   = 32; // not used
754
            end
755
          `ETH_IPGR2:
756
            begin
757
              bit_start_1 = 0;
758
              bit_end_1   = 6;
759
              bit_start_2 = 32; // not used
760
              bit_end_2   = 32; // not used
761
            end
762
          `ETH_PACKETLEN:
763
            begin
764
              bit_start_1 = 0;
765
              bit_end_1   = 31;
766
              bit_start_2 = 32; // not used
767
              bit_end_2   = 32; // not used
768
            end
769
          `ETH_COLLCONF:
770
            begin
771
              bit_start_1 = 0;
772
              bit_end_1   = 5;
773
              bit_start_2 = 16;
774
              bit_end_2   = 19;
775
            end
776
          `ETH_TX_BD_NUM:
777
            begin
778
              bit_start_1 = 0;
779
              bit_end_1   = 7;
780
              bit_start_2 = 32; // not used
781
              bit_end_2   = 32; // not used
782
            end
783
          `ETH_CTRLMODER:
784
            begin
785
              bit_start_1 = 0;
786
              bit_end_1   = 2;
787
              bit_start_2 = 32; // not used
788
              bit_end_2   = 32; // not used
789
            end
790
          `ETH_MIIMODER:
791
            begin
792
              bit_start_1 = 0;
793
              bit_end_1   = 9;
794
              bit_start_2 = 32; // not used
795
              bit_end_2   = 32; // not used
796
            end
797
          `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
798
            begin
799
              bit_start_1 = 32; // not used
800
              bit_end_1   = 32; // not used
801
              bit_start_2 = 32; // not used
802
              bit_end_2   = 32; // not used
803
            end
804
          `ETH_MIIADDRESS:
805
            begin
806
              bit_start_1 = 0;
807
              bit_end_1   = 4;
808
              bit_start_2 = 8;
809
              bit_end_2   = 12;
810
            end
811
          `ETH_MIITX_DATA:
812
            begin
813
              bit_start_1 = 0;
814
              bit_end_1   = 15;
815
              bit_start_2 = 32; // not used
816
              bit_end_2   = 32; // not used
817
            end
818
          `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
819
            begin
820
              bit_start_1 = 32; // not used
821
              bit_end_1   = 32; // not used
822
              bit_start_2 = 32; // not used
823
              bit_end_2   = 32; // not used
824
            end
825
          `ETH_MIISTATUS: // READONLY - tested within MIIM test
826
            begin
827
              bit_start_1 = 32; // not used
828
              bit_end_1   = 32; // not used
829
              bit_start_2 = 32; // not used
830
              bit_end_2   = 32; // not used
831
            end
832
          `ETH_MAC_ADDR0:
833
            begin
834
              bit_start_1 = 0;
835
              bit_end_1   = 31;
836
              bit_start_2 = 32; // not used
837
              bit_end_2   = 32; // not used
838
            end
839
          `ETH_MAC_ADDR1:
840
            begin
841
              bit_start_1 = 0;
842
              bit_end_1   = 15;
843
              bit_start_2 = 32; // not used
844
              bit_end_2   = 32; // not used
845
            end
846
          `ETH_HASH_ADDR0:
847
            begin
848
              bit_start_1 = 0;
849
              bit_end_1   = 31;
850
              bit_start_2 = 32; // not used
851
              bit_end_2   = 32; // not used
852
            end
853
          default: // `ETH_HASH_ADDR1:
854
            begin
855
              bit_start_1 = 0;
856
              bit_end_1   = 31;
857
              bit_start_2 = 32; // not used
858
              bit_end_2   = 32; // not used
859
            end
860
          endcase
861
          #1;
862
          // 3 LSBits of MIICOMMAND are NOT written !!!
863
          if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
864
          begin
865
            if (burst_tmp_data[31:0] !== burst_data[31:0])
866
            begin
867
              fail = fail + 1;
868
              test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
869
              `TIME;
870
              $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
871
                        wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
872
            end
873
          end
874
          else
875
          begin
876
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
877
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
878
            begin
879
              if (burst_tmp_data[31:0] !== burst_data[31:0])
880
              begin
881
                fail = fail + 1;
882
                test_fail("RW bit of the MAC register was not written or not read");
883
                `TIME;
884
                $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
885
                          wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
886
              end
887
            end
888
            else // data should not be equal to tmp_data
889
            begin
890
              if (burst_tmp_data[31:0] === burst_data[31:0])
891
              begin
892
                fail = fail + 1;
893
                test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
894
                `TIME;
895
                $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
896
                          wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
897
              end
898
            end
899
          end
900
          burst_tmp_data = burst_tmp_data >> 32;
901
          burst_data = burst_data >> 32;
902
        end
903
      end
904
    end
905
  end
906
  if(fail == 0)
907
    test_ok;
908
  else
909
    fail = 0;*/
910 116 mohor
end
911
 
912 169 mohor
 
913
if ((start_task <= 1) && (end_task >= 1))
914 116 mohor
begin
915 169 mohor
  // TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
916
  test_name   = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
917
  `TIME; $display("  TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
918 116 mohor
 
919 169 mohor
  data = 0;
920
  // set TX and RX buffer descriptors
921
  tx_bd_num = 32'h40;
922
  wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
923
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
924
  begin
925
    wbm_init_waits = i;
926
    wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
927
    for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
928
    begin
929
      addr = `ETH_BASE + i_addr;
930
      if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
931
      begin
932
        // set ranges of R/W bits
933
        case (addr[3])
934
        1'b0: // buffer control bits
935
          begin
936
            bit_start_1 = 0;
937
            bit_end_1   = 31; // 8;
938
            bit_start_2 = 11;
939
            bit_end_2   = 31;
940
          end
941
        default: // 1'b1: // buffer pointer
942
          begin
943
            bit_start_1 = 0;
944
            bit_end_1   = 31;
945
            bit_start_2 = 32; // not used
946
            bit_end_2   = 32; // not used
947
          end
948
        endcase
949
      end
950
      else // RX buffer descriptors
951
      begin
952
        // set ranges of R/W bits
953
        case (addr[3])
954
        1'b0: // buffer control bits
955
          begin
956
            bit_start_1 = 0;
957
            bit_end_1   = 31; // 7;
958
            bit_start_2 = 13;
959
            bit_end_2   = 31;
960
          end
961
        default: // 1'b1: // buffer pointer
962
          begin
963
            bit_start_1 = 0;
964
            bit_end_1   = 31;
965
            bit_start_2 = 32; // not used
966
            bit_end_2   = 32; // not used
967
          end
968
        endcase
969
      end
970 116 mohor
 
971 169 mohor
      for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
972
      begin
973
        data = 1'b1 << i_data;
974
        if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
975
        begin
976
        end
977
        else
978
        begin
979
          wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
980
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
981
          if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
982
               ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
983
          begin
984
            if (tmp_data !== data)
985
            begin
986
              fail = fail + 1;
987
              test_fail("RW bit of the MAC buffer descriptors was not written or not read");
988
              `TIME;
989
              $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
990
                        wbm_init_waits, addr, data, tmp_data);
991
            end
992
          end
993
          else // data should not be equal to tmp_data
994
          begin
995
            if (tmp_data === data)
996
            begin
997
              fail = fail + 1;
998
              test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
999
              `TIME;
1000
              $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
1001
                        wbm_init_waits, addr, data, tmp_data);
1002
            end
1003
          end
1004
        end
1005
      end
1006
    end
1007
    case (i)
1008
    0:       $display("    buffer descriptors tested with 0 bus delay");
1009
    1:       $display("    buffer descriptors tested with 1 bus delay cycle");
1010
    2:       $display("    buffer descriptors tested with 2 bus delay cycles");
1011
    3:       $display("    buffer descriptors tested with 3 bus delay cycles");
1012
    default: $display("    buffer descriptors tested with 4 bus delay cycles");
1013
    endcase
1014
  end
1015
  if(fail == 0)
1016
    test_ok;
1017
  else
1018
    fail = 0;
1019
end
1020 116 mohor
 
1021 169 mohor
  /* Register      RESET values    MAX. values
1022
     -----------------------------------------
1023
   ETH_MODER       32'h0000_A800   32'h0000_A800   Mode Register
1024
   ETH_INT         32'h0000_0000   32'h0000_0000   Interrupt Source Register
1025
   ETH_INT_MASK    32'h0000_0000   32'h0000_0000   Interrupt Mask Register
1026
   ETH_IPGT        32'h0000_0012   32'h0000_0012   Back to Bak Inter Packet Gap Register
1027
   ETH_IPGR1       32'h0000_000C   32'h0000_000C   Non Back to Back Inter Packet Gap Register 1
1028
   ETH_IPGR2       32'h0000_0012   32'h0000_0012   Non Back to Back Inter Packet Gap Register 2
1029
   ETH_PACKETLEN   32'h0040_0600   32'h0040_0600   Packet Length Register (min. and max.)
1030
   ETH_COLLCONF    32'h000F_003F   32'h000F_003F   Collision and Retry Configuration Register
1031
   ETH_TX_BD_NUM   32'h0000_0040   32'h0000_0080   Transmit Buffer Descriptor Number Register
1032
   ETH_CTRLMODER   32'h0000_0000   32'h0000_0000   Control Module Mode Register
1033
   ETH_MIIMODER    32'h0000_0064   32'h0000_0064   MII Mode Register
1034
   ETH_MIICOMMAND  32'h0000_0000   32'h0000_0000   MII Command Register
1035
   ETH_MIIADDRESS  32'h0000_0000   32'h0000_0000   MII Address Register
1036
   ETH_MIITX_DATA  32'h0000_0000   32'h0000_0000   MII Transmit Data Register
1037
   ETH_MIIRX_DATA  32'h0000_0000   32'h0000_0000   MII Receive Data Register
1038
   ETH_MIISTATUS   32'h0000_0000   32'h0000_0000   MII Status Register
1039
   ETH_MAC_ADDR0   32'h0000_0000   32'h0000_0000   MAC Individual Address Register 0
1040
   ETH_MAC_ADDR1   32'h0000_0000   32'h0000_0000   MAC Individual Address Register 1
1041
   ETH_HASH_ADDR0  32'h0000_0000   32'h0000_0000   Hash Register 0
1042
   ETH_HASH_ADDR1  32'h0000_0000   32'h0000_0000   Hash Register 1
1043
  */
1044 156 mohor
 
1045 116 mohor
 
1046 169 mohor
if ((start_task <= 2) && (end_task >= 2))
1047
begin
1048
  // TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
1049
  test_name   =
1050
  "TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
1051
  `TIME; $display(
1052
  "  TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
1053 158 mohor
 
1054 169 mohor
  // reset MAC registers
1055
  hard_reset;
1056
  for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
1057
  begin
1058
    for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
1059
    begin
1060
      addr = `ETH_BASE + i_addr;
1061
      // set ranges of R/W bits
1062
      case (addr)
1063
      `ETH_MODER:
1064
      begin
1065
        data = 32'h0000_A800;
1066
        data_max = 32'h0001_FFFF;
1067
      end
1068
      `ETH_INT: // READONLY - tested within INT test
1069
      begin
1070
        data = 32'h0000_0000;
1071
        data_max = 32'h0000_0000;
1072
      end
1073
      `ETH_INT_MASK:
1074
      begin
1075
        data = 32'h0000_0000;
1076
        data_max = 32'h0000_007F;
1077
      end
1078
      `ETH_IPGT:
1079
      begin
1080
        data = 32'h0000_0012;
1081
        data_max = 32'h0000_007F;
1082
      end
1083
      `ETH_IPGR1:
1084
      begin
1085
        data = 32'h0000_000C;
1086
        data_max = 32'h0000_007F;
1087
      end
1088
      `ETH_IPGR2:
1089
      begin
1090
        data = 32'h0000_0012;
1091
        data_max = 32'h0000_007F;
1092
      end
1093
      `ETH_PACKETLEN:
1094
      begin
1095
        data = 32'h0040_0600;
1096
        data_max = 32'hFFFF_FFFF;
1097
      end
1098
      `ETH_COLLCONF:
1099
      begin
1100
        data = 32'h000F_003F;
1101
        data_max = 32'h000F_003F;
1102
      end
1103
      `ETH_TX_BD_NUM:
1104
      begin
1105
        data = 32'h0000_0040;
1106
        data_max = 32'h0000_0080;
1107
      end
1108
      `ETH_CTRLMODER:
1109
      begin
1110
        data = 32'h0000_0000;
1111
        data_max = 32'h0000_0007;
1112
      end
1113
      `ETH_MIIMODER:
1114
      begin
1115
        data = 32'h0000_0064;
1116
        data_max = 32'h0000_03FF;
1117
      end
1118
      `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
1119
      begin
1120
        data = 32'h0000_0000;
1121
        data_max = 32'h0000_0007;
1122
      end
1123
      `ETH_MIIADDRESS:
1124
      begin
1125
        data = 32'h0000_0000;
1126
        data_max = 32'h0000_1F1F;
1127
      end
1128
      `ETH_MIITX_DATA:
1129
      begin
1130
        data = 32'h0000_0000;
1131
        data_max = 32'h0000_FFFF;
1132
      end
1133
      `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
1134
      begin
1135
        data = 32'h0000_0000;
1136
        data_max = 32'h0000_0000;
1137
      end
1138
      `ETH_MIISTATUS: // READONLY - tested within MIIM test
1139
      begin
1140
        data = 32'h0000_0000;
1141
        data_max = 32'h0000_0000;
1142
      end
1143
      `ETH_MAC_ADDR0:
1144
      begin
1145
        data = 32'h0000_0000;
1146
        data_max = 32'hFFFF_FFFF;
1147
      end
1148
      `ETH_MAC_ADDR1:
1149
      begin
1150
        data = 32'h0000_0000;
1151
        data_max = 32'h0000_FFFF;
1152
      end
1153
      `ETH_HASH_ADDR0:
1154
      begin
1155
        data = 32'h0000_0000;
1156
        data_max = 32'hFFFF_FFFF;
1157
      end
1158
      default: // `ETH_HASH_ADDR1:
1159
      begin
1160
        data = 32'h0000_0000;
1161
        data_max = 32'hFFFF_FFFF;
1162
      end
1163
      endcase
1164 116 mohor
 
1165 169 mohor
      wbm_init_waits = {$random} % 3;
1166
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1167
      if (i == 0)
1168
        wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1169
      else if (i == 2)
1170
        wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1171
      else if ((i == 1) || (i == 4))
1172
      begin
1173
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1174
        if (tmp_data !== data)
1175
        begin
1176
          fail = fail + 1;
1177
          test_fail("RESET value of the MAC register is not correct");
1178
          `TIME;
1179
          $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1180
        end
1181
      end
1182
      else // check maximum values
1183
      begin
1184
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1185
        if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
1186
        begin
1187
          if (tmp_data !== data)
1188
          begin
1189
            fail = fail + 1;
1190
            test_fail("Previous value of the TX_BD_NUM register did not remain");
1191
            `TIME;
1192
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1193
          end
1194
          // try maximum (80)
1195
          wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1196
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1197
          if (tmp_data !== data_max)
1198
          begin
1199
            fail = fail + 1;
1200
            test_fail("MAX value of the TX_BD_NUM register is not correct");
1201
            `TIME;
1202
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1203
          end
1204
          // try one less than maximum (80)
1205
          wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1206
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1207
          if (tmp_data !== (data_max - 1))
1208
          begin
1209
            fail = fail + 1;
1210
            test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
1211
            `TIME;
1212
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1213
          end
1214
          // try one more than maximum (80)
1215
          wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1216
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1217
          if (tmp_data !== (data_max - 1)) // previous data should remain in this register
1218
          begin
1219
            fail = fail + 1;
1220
            test_fail("Previous value of the TX_BD_NUM register did not remain");
1221
            `TIME;
1222
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1223
          end
1224
        end
1225
        else
1226
        begin
1227
          if (tmp_data !== data_max)
1228
          begin
1229
            fail = fail + 1;
1230
            test_fail("MAX value of the MAC register is not correct");
1231
            `TIME;
1232
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1233
          end
1234
        end
1235
      end
1236
    end
1237
    // reset MAC registers
1238
    if ((i == 0) || (i == 3))
1239
    begin
1240
      hard_reset;
1241
    end
1242
  end
1243
  if(fail == 0)
1244
    test_ok;
1245
  else
1246
    fail = 0;
1247
end
1248 116 mohor
 
1249
 
1250 169 mohor
if ((start_task <= 3) && (end_task >= 3))
1251
begin
1252
  // TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
1253
  test_name   = "TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
1254
  `TIME;
1255
  $display("  TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
1256 116 mohor
 
1257 169 mohor
  // reset MAC registers
1258
  hard_reset;
1259
  // reset LOGIC with soft reset
1260
  reset_mac;
1261
  reset_mii;
1262
  for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
1263
  begin
1264
    for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1265
    begin
1266
      addr = `ETH_BASE + i_addr;
1267 116 mohor
 
1268 169 mohor
      wbm_init_waits = {$random} % 3;
1269
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1270
      if (i == 0)
1271
      begin
1272
        data = 32'hFFFFFFFF;
1273
        wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1274
      end
1275
      else if (i == 2)
1276
      begin
1277
        data = 32'h00000000;
1278
        wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1279
      end
1280
      else
1281
      begin
1282
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1283
        if (tmp_data !== data)
1284
        begin
1285
          fail = fail + 1;
1286
          test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
1287
          `TIME;
1288
          $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1289
        end
1290
      end
1291
    end
1292
    if ((i == 0) || (i == 2))
1293
    begin
1294
      // reset MAC registers
1295
      hard_reset;
1296
      // reset LOGIC with soft reset
1297
      reset_mac;
1298
      reset_mii;
1299
    end
1300
  end
1301
  if(fail == 0)
1302
    test_ok;
1303
  else
1304
    fail = 0;
1305
end
1306 156 mohor
 
1307
 
1308 169 mohor
end
1309
endtask // test_access_to_mac_reg
1310 156 mohor
 
1311
 
1312 169 mohor
task test_mii;
1313
  input  [31:0]  start_task;
1314
  input  [31:0]  end_task;
1315
  integer        i;
1316
  integer        i1;
1317
  integer        i2;
1318
  integer        i3;
1319
  integer        cnt;
1320
  integer        fail;
1321
  reg     [8:0]  clk_div; // only 8 bits are valid!
1322
  reg     [4:0]  phy_addr;
1323
  reg     [4:0]  reg_addr;
1324
  reg     [15:0] phy_data;
1325
  reg     [15:0] tmp_data;
1326
begin
1327
// MIIM MODULE TEST
1328
test_heading("MIIM MODULE TEST");
1329
$display(" ");
1330
$display("MIIM MODULE TEST");
1331
fail = 0;
1332 156 mohor
 
1333 169 mohor
// reset MIIM LOGIC with soft reset
1334
reset_mii;
1335 116 mohor
 
1336
 
1337 169 mohor
if ((start_task <= 0) && (end_task >= 0))
1338
begin
1339
  // TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
1340
  test_name   = "TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
1341
  `TIME; $display("  TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
1342 116 mohor
 
1343 169 mohor
  wait(Mdc_O); // wait for MII clock to be 1
1344
  for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
1345
  begin
1346
    i1 = 0;
1347
    i2 = 0;
1348
    #Tp mii_set_clk_div(clk_div[7:0]);
1349
    @(posedge Mdc_O);
1350
    #Tp;
1351
    fork
1352
      begin
1353
        @(posedge Mdc_O);
1354
        #Tp;
1355
        disable count_i1;
1356
        disable count_i2;
1357
      end
1358
      begin: count_i1
1359
        forever
1360
        begin
1361
          @(posedge wb_clk);
1362
          i1 = i1 + 1;
1363
          #Tp;
1364
        end
1365
      end
1366
      begin: count_i2
1367
        forever
1368
        begin
1369
          @(negedge wb_clk);
1370
          i2 = i2 + 1;
1371
          #Tp;
1372
        end
1373
      end
1374
    join
1375
    if((clk_div[7:0] == 0) || (clk_div[7:0] == 1) || (clk_div[7:0] == 2) || (clk_div[7:0] == 3))
1376
    begin
1377
      if((i1 == i2) && (i1 == 2))
1378
      begin
1379
      end
1380
      else
1381
      begin
1382
        fail = fail + 1;
1383
        test_fail("Clock divider of MII module did'nt divide frequency corectly (it should divid with 2)");
1384
      end
1385
    end
1386
    else
1387
    begin
1388
      if((i1 == i2) && (i1 == {clk_div[7:1], 1'b0}))
1389
      begin
1390
      end
1391
      else
1392
      begin
1393
        fail = fail + 1;
1394
        test_fail("Clock divider of MII module did'nt divide frequency corectly");
1395
      end
1396
    end
1397
  end
1398
  if(fail == 0)
1399
    test_ok;
1400
  else
1401
    fail = 0;
1402 116 mohor
end
1403
 
1404
 
1405 169 mohor
if ((start_task <= 1) && (end_task >= 1))
1406
begin
1407
  // TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS
1408
  test_name   = "TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
1409
  `TIME; $display("  TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
1410
 
1411
  // set the fastest possible MII
1412
  clk_div = 0;
1413
  mii_set_clk_div(clk_div[7:0]);
1414
  // set address
1415
  reg_addr = 5'h1F;
1416
  phy_addr = 5'h1;
1417
  while(reg_addr >= 5'h4)
1418
  begin
1419
    // read request
1420
    #Tp mii_read_req(phy_addr, reg_addr);
1421
    check_mii_busy; // wait for read to finish
1422
    // read data
1423
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1424
    if (phy_data !== 16'hDEAD)
1425
    begin
1426
      test_fail("Wrong data was read from PHY from 'not used' address space");
1427
      fail = fail + 1;
1428
    end
1429
    if (reg_addr == 5'h4) // go out of for loop
1430
      reg_addr = 5'h3;
1431 116 mohor
    else
1432 169 mohor
      reg_addr = reg_addr - 5'h9;
1433
  end
1434 116 mohor
 
1435 169 mohor
  // set address
1436
  reg_addr = 5'h3;
1437
  // read request
1438
  #Tp mii_read_req(phy_addr, reg_addr);
1439
  check_mii_busy; // wait for read to finish
1440
  // read data
1441
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1442
  if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})
1443
  begin
1444
    test_fail("Wrong data was read from PHY from ID register 2");
1445
    fail = fail + 1;
1446 116 mohor
  end
1447 169 mohor
  if(fail == 0)
1448
    test_ok;
1449
  else
1450
    fail = 0;
1451
end
1452 116 mohor
 
1453
 
1454 169 mohor
if ((start_task <= 2) && (end_task >= 2))
1455
begin
1456
  // TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
1457
  test_name   = "TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
1458
  `TIME; $display("  TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
1459
 
1460
  // negate data and try to write into unwritable register
1461
  tmp_data = ~phy_data;
1462
  // write request
1463
  #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1464
  check_mii_busy; // wait for write to finish
1465
  // read request
1466
  #Tp mii_read_req(phy_addr, reg_addr);
1467
  check_mii_busy; // wait for read to finish
1468
  // read data
1469
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1470
  if (tmp_data !== phy_data)
1471
  begin
1472
    test_fail("Data was written into unwritable PHY register - ID register 2");
1473
    fail = fail + 1;
1474
  end
1475
 
1476
  // set address
1477
  reg_addr = 5'h0; // control register
1478
  // read request
1479
  #Tp mii_read_req(phy_addr, reg_addr);
1480
  check_mii_busy; // wait for read to finish
1481
  // read data
1482
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1483
  // write request
1484
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1485
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1486
  check_mii_busy; // wait for write to finish
1487
  // read request
1488
  #Tp mii_read_req(phy_addr, reg_addr);
1489
  check_mii_busy; // wait for read to finish
1490
  // read data
1491
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1492
  if (phy_data !== 16'h7DFF)
1493
  begin
1494
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1495
    fail = fail + 1;
1496
  end
1497
  // write request
1498
  #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1499
  check_mii_busy; // wait for write to finish
1500
  // read request
1501
  #Tp mii_read_req(phy_addr, reg_addr);
1502
  check_mii_busy; // wait for read to finish
1503
  // read data
1504
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1505
  if (phy_data !== tmp_data)
1506
  begin
1507
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1508
    fail = fail + 1;
1509
  end
1510
  if(fail == 0)
1511
    test_ok;
1512
  else
1513
    fail = 0;
1514
end
1515
 
1516
 
1517
if ((start_task <= 3) && (end_task >= 3))
1518
begin
1519
  // TEST RESET PHY THROUGH MII MANAGEMENT MODULE
1520
  test_name   = "TEST RESET PHY THROUGH MII MANAGEMENT MODULE";
1521
  `TIME; $display("  TEST RESET PHY THROUGH MII MANAGEMENT MODULE");
1522
 
1523
  // set address
1524
  reg_addr = 5'h0; // control register
1525
  // write request
1526
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1527
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1528
  check_mii_busy; // wait for write to finish
1529
  // read request
1530
  #Tp mii_read_req(phy_addr, reg_addr);
1531
  check_mii_busy; // wait for read to finish
1532
  // read data
1533
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1534
  if (phy_data !== tmp_data)
1535
  begin
1536
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1537
    fail = fail + 1;
1538
  end
1539
  // set reset bit - selfclearing bit in PHY
1540
  phy_data = phy_data | 16'h8000;
1541
  // write request
1542
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1543
  check_mii_busy; // wait for write to finish
1544
  // read request
1545
  #Tp mii_read_req(phy_addr, reg_addr);
1546
  check_mii_busy; // wait for read to finish
1547
  // read data
1548
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1549
  // check self clearing of reset bit
1550
  if (tmp_data[15] !== 1'b0)
1551
  begin
1552
    test_fail("Reset bit should be self cleared - control register");
1553
    fail = fail + 1;
1554
  end
1555
  // check reset value of control register
1556
  if (tmp_data !== {2'h0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 3'h0, `LED_CFG3, 8'h0})
1557
  begin
1558
    test_fail("PHY was not reset correctly AND/OR reset bit not self cleared");
1559
    fail = fail + 1;
1560
  end
1561
  if(fail == 0)
1562
    test_ok;
1563
  else
1564
    fail = 0;
1565
end
1566
 
1567
 
1568
if ((start_task <= 4) && (end_task >= 4))
1569
begin
1570
  // TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
1571
  test_name   = "TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1572
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1573
 
1574
  // set PHY to test mode
1575
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1576
  for (i = 0; i <= 1; i = i + 1)
1577
  begin
1578
    #Tp eth_phy.preamble_suppresed(i);
1579
    #Tp eth_phy.clear_test_regs;
1580
    // MII mode register
1581
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1582
              wbm_subseq_waits);
1583
    // walk one across phy address
1584
    for (phy_addr = 5'h1; phy_addr > 5'h0; phy_addr = phy_addr << 1)
1585
    begin
1586
      reg_addr = $random;
1587
      tmp_data = $random;
1588
      // write request
1589
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1590
      check_mii_busy; // wait for write to finish
1591
      // read request
1592
      #Tp mii_read_req(phy_addr, reg_addr);
1593
      check_mii_busy; // wait for read to finish
1594
      // read data
1595
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1596
      #Tp;
1597
      if (phy_data !== tmp_data)
1598
      begin
1599
        if (i)
1600
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1601
        else
1602
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1603
        fail = fail + 1;
1604
      end
1605
      @(posedge wb_clk);
1606
      #Tp;
1607
    end
1608
  end
1609
  // set PHY to normal mode
1610
  #Tp eth_phy.test_regs(0);
1611
  #Tp eth_phy.preamble_suppresed(0);
1612
  // MII mode register
1613
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1614
  if(fail == 0)
1615
    test_ok;
1616
  else
1617
    fail = 0;
1618
end
1619
 
1620
 
1621
if ((start_task <= 5) && (end_task >= 5))
1622
begin
1623
  // TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
1624
  test_name   = "TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1625
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1626
 
1627
  // set PHY to test mode
1628
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1629
  for (i = 0; i <= 1; i = i + 1)
1630
  begin
1631
    #Tp eth_phy.preamble_suppresed(i);
1632
    #Tp eth_phy.clear_test_regs;
1633
    // MII mode register
1634
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1635
              wbm_subseq_waits);
1636
    // walk one across reg address
1637
    for (reg_addr = 5'h1; reg_addr > 5'h0; reg_addr = reg_addr << 1)
1638
    begin
1639
      phy_addr = $random;
1640
      tmp_data = $random;
1641
      // write request
1642
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1643
      check_mii_busy; // wait for write to finish
1644
      // read request
1645
      #Tp mii_read_req(phy_addr, reg_addr);
1646
      check_mii_busy; // wait for read to finish
1647
      // read data
1648
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1649
      #Tp;
1650
      if (phy_data !== tmp_data)
1651
      begin
1652
        if (i)
1653
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1654
        else
1655
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1656
        fail = fail + 1;
1657
      end
1658
      @(posedge wb_clk);
1659
      #Tp;
1660
    end
1661
  end
1662
  // set PHY to normal mode
1663
  #Tp eth_phy.test_regs(0);
1664
  #Tp eth_phy.preamble_suppresed(0);
1665
  // MII mode register
1666
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1667
  if(fail == 0)
1668
    test_ok;
1669
  else
1670
    fail = 0;
1671
end
1672
 
1673
 
1674
if ((start_task <= 6) && (end_task >= 6))
1675
begin
1676
  // TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
1677
  test_name   = "TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
1678
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
1679
 
1680
  // set PHY to test mode
1681
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1682
  for (i = 0; i <= 1; i = i + 1)
1683
  begin
1684
    #Tp eth_phy.preamble_suppresed(i);
1685
    #Tp eth_phy.clear_test_regs;
1686
    // MII mode register
1687
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1688
              wbm_subseq_waits);
1689
    // walk one across data
1690
    for (tmp_data = 16'h1; tmp_data > 16'h0; tmp_data = tmp_data << 1)
1691
    begin
1692
      phy_addr = $random;
1693
      reg_addr = $random;
1694
      // write request
1695
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1696
      check_mii_busy; // wait for write to finish
1697
      // read request
1698
      #Tp mii_read_req(phy_addr, reg_addr);
1699
      check_mii_busy; // wait for read to finish
1700
      // read data
1701
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1702
      #Tp;
1703
      if (phy_data !== tmp_data)
1704
      begin
1705
        if (i)
1706
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1707
        else
1708
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1709
        fail = fail + 1;
1710
      end
1711
      @(posedge wb_clk);
1712
      #Tp;
1713
    end
1714
  end
1715
  // set PHY to normal mode
1716
  #Tp eth_phy.test_regs(0);
1717
  #Tp eth_phy.preamble_suppresed(0);
1718
  // MII mode register
1719
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1720
  if(fail == 0)
1721
    test_ok;
1722
  else
1723
    fail = 0;
1724
end
1725
 
1726
 
1727
if ((start_task <= 7) && (end_task >= 7))
1728
begin
1729
  // TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
1730
  test_name   = "TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
1731
  `TIME; $display("  TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
1732
 
1733
  phy_addr = 5'h2; // wrong PHY address
1734
  // read request
1735
  #Tp mii_read_req(phy_addr, reg_addr);
1736
  check_mii_busy; // wait for read to finish
1737
  // read data
1738
  $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
1739
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1740
  if (tmp_data !== 16'hzzzz)
1741
  begin
1742
    test_fail("Data was read from PHY register with wrong PHY address - control register");
1743
    fail = fail + 1;
1744
  end
1745
  if(fail == 0)
1746
    test_ok;
1747
  else
1748
    fail = 0;
1749
end
1750
 
1751
 
1752
if ((start_task <= 8) && (end_task >= 8))
1753
begin
1754
  // TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
1755
  test_name   = "TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
1756
  `TIME; $display("  TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
1757
 
1758
  // set address
1759
  reg_addr = 5'h0; // control register
1760
  phy_addr = 5'h2; // wrong PHY address
1761
  // write request
1762
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1763
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1764
  check_mii_busy; // wait for write to finish
1765
 
1766
  phy_addr = 5'h1; // correct PHY address
1767
  // read request
1768
  #Tp mii_read_req(phy_addr, reg_addr);
1769
  check_mii_busy; // wait for read to finish
1770
  // read data
1771
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1772
  if (phy_data === tmp_data)
1773
  begin
1774
    test_fail("Data was written into PHY register with wrong PHY address - control register");
1775
    fail = fail + 1;
1776
  end
1777
  if(fail == 0)
1778
    test_ok;
1779
  else
1780
    fail = 0;
1781
end
1782
 
1783
 
1784
if ((start_task <= 9) && (end_task >= 9))
1785
begin
1786
  // TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
1787
  test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
1788
  `TIME;
1789
  $display("  TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
1790
 
1791
  for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1792
  begin
1793
    #Tp eth_phy.preamble_suppresed(i2);
1794
    // MII mode register
1795
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1796
             wbm_subseq_waits);
1797
    i = 0;
1798
    cnt = 0;
1799
    while (i < 80) // delay for sliding of writing a STOP SCAN command
1800
    begin
1801
      for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after read will be finished
1802
      begin
1803
        // set address
1804
        reg_addr = 5'h0; // control register
1805
        phy_addr = 5'h1; // correct PHY address
1806
        cnt = 0;
1807
        // read request
1808
        #Tp mii_read_req(phy_addr, reg_addr);
1809
        fork
1810
          begin
1811
            repeat(i) @(posedge Mdc_O);
1812
            // write command 0x0 into MII command register
1813
            // MII command written while read in progress
1814
            wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1815
            @(posedge wb_clk);
1816
            #Tp check_mii_busy; // wait for read to finish
1817
          end
1818
          begin
1819
            // wait for serial bus to become active
1820
            wait(Mdio_IO !== 1'bz);
1821
            // count transfer length
1822
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
1823
            begin
1824
              @(posedge Mdc_O);
1825
              #Tp cnt = cnt + 1;
1826
            end
1827
          end
1828
        join
1829
        // check transfer length
1830
        if (i2) // without preamble
1831
        begin
1832
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
1833
          begin
1834
            test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
1835
            fail = fail + 1;
1836
          end
1837
        end
1838
        else // with preamble
1839
        begin
1840
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
1841
          begin
1842
            test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
1843
            fail = fail + 1;
1844
          end
1845
        end
1846
        // check the BUSY signal to see if the bus is still IDLE
1847
        for (i1 = 0; i1 < 8; i1 = i1 + 1)
1848
          check_mii_busy; // wait for bus to become idle
1849 116 mohor
 
1850 169 mohor
        // try normal write or read after read was finished
1851
        #Tp phy_data = {8'h7D, (i[7:0] + 1)};
1852
        #Tp cnt = 0;
1853
        if (i3 == 0) // write after read
1854
        begin
1855
          // write request
1856
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1857
          // wait for serial bus to become active
1858
          wait(Mdio_IO !== 1'bz);
1859
          // count transfer length
1860
          while(Mdio_IO !== 1'bz)
1861
          begin
1862
            @(posedge Mdc_O);
1863
            #Tp cnt = cnt + 1;
1864
          end
1865
          @(posedge Mdc_O);
1866
          // read request
1867
          #Tp mii_read_req(phy_addr, reg_addr);
1868
          check_mii_busy; // wait for read to finish
1869
          // read and check data
1870
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1871
          if (phy_data !== tmp_data)
1872
          begin
1873
            test_fail("Data was not correctly written into OR read from PHY register - control register");
1874
            fail = fail + 1;
1875
          end
1876
        end
1877
        else // read after read
1878
        begin
1879
          // read request
1880
          #Tp mii_read_req(phy_addr, reg_addr);
1881
          // wait for serial bus to become active
1882
          wait(Mdio_IO !== 1'bz);
1883
          // count transfer length
1884
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
1885
          begin
1886
            @(posedge Mdc_O);
1887
            #Tp cnt = cnt + 1;
1888
          end
1889
          @(posedge Mdc_O);
1890
          check_mii_busy; // wait for read to finish
1891
          // read and check data
1892
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1893
          if (phy_data !== tmp_data)
1894
          begin
1895
            test_fail("Data was not correctly written into OR read from PHY register - control register");
1896
            fail = fail + 1;
1897
          end
1898
        end
1899
        // check if transfer was a proper length
1900
        if (i2) // without preamble
1901
        begin
1902
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
1903
          begin
1904
            test_fail("New request did not proceed correctly, after read request");
1905
            fail = fail + 1;
1906
          end
1907
        end
1908
        else // with preamble
1909
        begin
1910
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
1911
          begin
1912
            test_fail("New request did not proceed correctly, after read request");
1913
            fail = fail + 1;
1914
          end
1915
        end
1916
      end
1917
      #Tp;
1918
      // set delay of writing the command
1919
      if (i2) // without preamble
1920
      begin
1921
        case(i)
1922
          0, 1:               i = i + 1;
1923
          18, 19, 20, 21, 22,
1924
          23, 24, 25, 26, 27,
1925
          28, 29, 30, 31, 32,
1926
          33, 34, 35:         i = i + 1;
1927
          36:                 i = 80;
1928
          default:            i = 18;
1929
        endcase
1930
      end
1931
      else // with preamble
1932
      begin
1933
        case(i)
1934
          0, 1:               i = i + 1;
1935
          50, 51, 52, 53, 54,
1936
          55, 56, 57, 58, 59,
1937
          60, 61, 62, 63, 64,
1938
          65, 66, 67:         i = i + 1;
1939
          68:                 i = 80;
1940
          default:            i = 50;
1941
        endcase
1942
      end
1943
      @(posedge wb_clk);
1944
    end
1945
  end
1946
  // set PHY to normal mode
1947
  #Tp eth_phy.preamble_suppresed(0);
1948
  // MII mode register
1949
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1950
  if(fail == 0)
1951
    test_ok;
1952
  else
1953
    fail = 0;
1954
end
1955
 
1956
 
1957
if ((start_task <= 10) && (end_task >= 10))
1958
begin
1959
  // TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
1960
  test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
1961
  `TIME;
1962
  $display("  TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
1963
 
1964
  for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1965
  begin
1966
    #Tp eth_phy.preamble_suppresed(i2);
1967
    // MII mode register
1968
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1969
              wbm_subseq_waits);
1970
    i = 0;
1971
    cnt = 0;
1972
    while (i < 80) // delay for sliding of writing a STOP SCAN command
1973
    begin
1974
      for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after write will be finished
1975
      begin
1976
        // set address
1977
        reg_addr = 5'h0; // control register
1978
        phy_addr = 5'h1; // correct PHY address
1979
        cnt = 0;
1980
        // write request
1981
        phy_data = {8'h75, (i[7:0] + 1)};
1982
        #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1983
        fork
1984
          begin
1985
            repeat(i) @(posedge Mdc_O);
1986
            // write command 0x0 into MII command register
1987
            // MII command written while read in progress
1988
            wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1989
            @(posedge wb_clk);
1990
            #Tp check_mii_busy; // wait for write to finish
1991
          end
1992
          begin
1993
            // wait for serial bus to become active
1994
            wait(Mdio_IO !== 1'bz);
1995
            // count transfer length
1996
            while(Mdio_IO !== 1'bz)
1997
            begin
1998
              @(posedge Mdc_O);
1999
              #Tp cnt = cnt + 1;
2000
            end
2001
          end
2002
        join
2003
        // check transfer length
2004
        if (i2) // without preamble
2005
        begin
2006
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2007
          begin
2008
            test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2009
            fail = fail + 1;
2010
          end
2011
        end
2012
        else // with preamble
2013
        begin
2014
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2015
          begin
2016
            test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2017
            fail = fail + 1;
2018
          end
2019
        end
2020
        // check the BUSY signal to see if the bus is still IDLE
2021
        for (i1 = 0; i1 < 8; i1 = i1 + 1)
2022
          check_mii_busy; // wait for bus to become idle
2023 116 mohor
 
2024 169 mohor
        // try normal write or read after write was finished
2025
        #Tp cnt = 0;
2026
        if (i3 == 0) // write after write
2027
        begin
2028
          phy_data = {8'h7A, (i[7:0] + 1)};
2029
          // write request
2030
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2031
          // wait for serial bus to become active
2032
          wait(Mdio_IO !== 1'bz);
2033
          // count transfer length
2034
          while(Mdio_IO !== 1'bz)
2035
          begin
2036
            @(posedge Mdc_O);
2037
            #Tp cnt = cnt + 1;
2038
          end
2039
          @(posedge Mdc_O);
2040
          // read request
2041
          #Tp mii_read_req(phy_addr, reg_addr);
2042
          check_mii_busy; // wait for read to finish
2043
          // read and check data
2044
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2045
          if (phy_data !== tmp_data)
2046
          begin
2047
            test_fail("Data was not correctly written into OR read from PHY register - control register");
2048
            fail = fail + 1;
2049
          end
2050
        end
2051
        else // read after write
2052
        begin
2053
          // read request
2054
          #Tp mii_read_req(phy_addr, reg_addr);
2055
          // wait for serial bus to become active
2056
          wait(Mdio_IO !== 1'bz);
2057
          // count transfer length
2058
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2059
          begin
2060
            @(posedge Mdc_O);
2061
            #Tp cnt = cnt + 1;
2062
          end
2063
          @(posedge Mdc_O);
2064
          check_mii_busy; // wait for read to finish
2065
          // read and check data
2066
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2067
          if (phy_data !== tmp_data)
2068
          begin
2069
            test_fail("Data was not correctly written into OR read from PHY register - control register");
2070
            fail = fail + 1;
2071
          end
2072
        end
2073
        // check if transfer was a proper length
2074
        if (i2) // without preamble
2075
        begin
2076
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2077
          begin
2078
            test_fail("New request did not proceed correctly, after write request");
2079
            fail = fail + 1;
2080
          end
2081
        end
2082
        else // with preamble
2083
        begin
2084
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2085
          begin
2086
            test_fail("New request did not proceed correctly, after write request");
2087
            fail = fail + 1;
2088
          end
2089
        end
2090
      end
2091
      #Tp;
2092
      // set delay of writing the command
2093
      if (i2) // without preamble
2094
      begin
2095
        case(i)
2096
          0, 1:               i = i + 1;
2097
          18, 19, 20, 21, 22,
2098
          23, 24, 25, 26, 27,
2099
          28, 29, 30, 31, 32,
2100
          33, 34, 35:         i = i + 1;
2101
          36:                 i = 80;
2102
          default:            i = 18;
2103
        endcase
2104
      end
2105
      else // with preamble
2106
      begin
2107
        case(i)
2108
          0, 1:               i = i + 1;
2109
          50, 51, 52, 53, 54,
2110
          55, 56, 57, 58, 59,
2111
          60, 61, 62, 63, 64,
2112
          65, 66, 67:         i = i + 1;
2113
          68:                 i = 80;
2114
          default:            i = 50;
2115
        endcase
2116
      end
2117
      @(posedge wb_clk);
2118
    end
2119
  end
2120
  // set PHY to normal mode
2121
  #Tp eth_phy.preamble_suppresed(0);
2122
  // MII mode register
2123
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2124
  if(fail == 0)
2125
    test_ok;
2126
  else
2127
    fail = 0;
2128
end
2129
 
2130
 
2131
if ((start_task <= 11) && (end_task >= 11))
2132
begin
2133
  // TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
2134
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
2135
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
2136
 
2137
  reset_mii; // reset MII
2138
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2139
  #Tp eth_phy.link_up_down(1);
2140
  // set the MII
2141
  clk_div = 64;
2142
  mii_set_clk_div(clk_div[7:0]);
2143
  // set address
2144
  reg_addr = 5'h1; // status register
2145
  phy_addr = 5'h1; // correct PHY address
2146
 
2147
  for (i = 0; i <= 1; i = i + 1)
2148
  begin
2149
    #Tp eth_phy.preamble_suppresed(i);
2150
    // MII mode register
2151
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2152
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2153
    @(posedge Mdc_O);
2154
    // write request
2155
    #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);
2156
    // read data from MII status register - Busy and Nvalid bits
2157
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2158
 
2159
    // check MII IO signal and Busy and Nvalid bits
2160
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2161
    begin
2162
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2163
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2164
      begin
2165
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2166
        fail = fail + 1;
2167
      end
2168
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2169
      begin
2170
        test_fail("Nvalid signal was set during write");
2171
        fail = fail + 1;
2172
      end
2173
    end
2174
    else // Busy bit should already be set to '1', due to reads from MII status register
2175
    begin
2176
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2177
      begin
2178
        test_fail("Busy signal should be set after write, due to reads from MII status register");
2179
        fail = fail + 1;
2180
      end
2181
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2182
      begin
2183
        test_fail("Nvalid signal was set during write");
2184
        fail = fail + 1;
2185
      end
2186
    end
2187
 
2188
    // wait for serial bus to become active
2189
    wait(Mdio_IO !== 1'bz);
2190
    // count transfer bits
2191
    if (i)
2192
    begin
2193
      repeat(32) @(posedge Mdc_O);
2194
    end
2195 116 mohor
    else
2196 169 mohor
    begin
2197
      repeat(64) @(posedge Mdc_O);
2198
    end
2199
    // read data from MII status register - Busy and Nvalid bits
2200
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2201 116 mohor
 
2202 169 mohor
    // check MII IO signal and Busy and Nvalid bits
2203
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2204
    begin
2205
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2206
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2207
      begin
2208
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2209
        fail = fail + 1;
2210
      end
2211
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2212
      begin
2213
        test_fail("Nvalid signal was set during write");
2214
        fail = fail + 1;
2215
      end
2216
    end
2217
    else // Busy bit should still be set to '1'
2218
    begin
2219
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2220
      begin
2221
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2222
        fail = fail + 1;
2223
      end
2224
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2225
      begin
2226
        test_fail("Nvalid signal was set during write");
2227
        fail = fail + 1;
2228
      end
2229
    end
2230
 
2231
    // wait for next negative clock edge
2232
    @(negedge Mdc_O);
2233
    // read data from MII status register - Busy and Nvalid bits
2234
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2235
 
2236
    // check MII IO signal and Busy and Nvalid bits
2237
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2238
    begin
2239
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2240
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2241
      begin
2242
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2243
        fail = fail + 1;
2244
      end
2245
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2246
      begin
2247
        test_fail("Nvalid signal was set during write");
2248
        fail = fail + 1;
2249
      end
2250
    end
2251
    else // Busy bit should still be set to '1'
2252
    begin
2253
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2254
      begin
2255
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2256
        fail = fail + 1;
2257
      end
2258
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2259
      begin
2260
        test_fail("Nvalid signal was set during write");
2261
        fail = fail + 1;
2262
      end
2263
    end
2264
 
2265
    // wait for Busy to become inactive
2266
    i1 = 0;
2267
    while (i1 <= 2)
2268
    begin
2269
      // wait for next positive clock edge
2270
      @(posedge Mdc_O);
2271
      // read data from MII status register - Busy and Nvalid bits
2272
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2273
 
2274
      // check MII IO signal and Busy and Nvalid bits
2275
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2276
      begin
2277
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2278
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2279
        begin
2280
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2281
          fail = fail + 1;
2282
        end
2283
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2284
        begin
2285
          test_fail("Nvalid signal was set during write");
2286
          fail = fail + 1;
2287
        end
2288
      end
2289
      else // wait for Busy bit to be set to '0'
2290
      begin
2291
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2292
        begin
2293
          i1 = 3; // end of Busy checking
2294
        end
2295
        else
2296
        begin
2297
          if (i1 == 2)
2298
          begin
2299
            test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2300
            fail = fail + 1;
2301
          end
2302
          #Tp i1 = i1 + 1;
2303
        end
2304
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2305
        begin
2306
          test_fail("Nvalid signal was set after write");
2307
          fail = fail + 1;
2308
        end
2309
      end
2310
    end
2311 116 mohor
  end
2312 169 mohor
  // set PHY to normal mode
2313
  #Tp eth_phy.preamble_suppresed(0);
2314
  // MII mode register
2315
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2316
  if(fail == 0)
2317
    test_ok;
2318
  else
2319
    fail = 0;
2320
end
2321 116 mohor
 
2322
 
2323 169 mohor
if ((start_task <= 12) && (end_task >= 12))
2324
begin
2325
  // TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
2326
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
2327
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
2328 116 mohor
 
2329 169 mohor
  reset_mii; // reset MII
2330
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2331
  #Tp eth_phy.link_up_down(1);
2332
  // set the MII
2333
  clk_div = 64;
2334
  mii_set_clk_div(clk_div[7:0]);
2335
  // set address
2336
  reg_addr = 5'h1; // status register
2337
  phy_addr = 5'h1; // correct PHY address
2338
 
2339
  for (i = 0; i <= 1; i = i + 1)
2340
  begin
2341
    #Tp eth_phy.preamble_suppresed(i);
2342
    // MII mode register
2343
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2344
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2345
    @(posedge Mdc_O);
2346
    // read request
2347
    #Tp mii_read_req(phy_addr, reg_addr);
2348
    // read data from MII status register - Busy and Nvalid bits
2349
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2350
 
2351
    // check MII IO signal and Busy and Nvalid bits
2352
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2353
    begin
2354
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2355
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2356
      begin
2357
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2358
        fail = fail + 1;
2359
      end
2360
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2361
      begin
2362
        test_fail("Nvalid signal was set during read");
2363
        fail = fail + 1;
2364
      end
2365
    end
2366
    else // Busy bit should already be set to '1', due to reads from MII status register
2367
    begin
2368
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2369
      begin
2370
        test_fail("Busy signal should be set after read, due to reads from MII status register");
2371
        fail = fail + 1;
2372
      end
2373
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2374
      begin
2375
        test_fail("Nvalid signal was set during read");
2376
        fail = fail + 1;
2377
      end
2378
    end
2379
 
2380
    // wait for serial bus to become active
2381
    wait(Mdio_IO !== 1'bz);
2382
    // count transfer bits
2383
    if (i)
2384
    begin
2385
      repeat(31) @(posedge Mdc_O);
2386
    end
2387
    else
2388
    begin
2389
      repeat(63) @(posedge Mdc_O);
2390
    end
2391
    // wait for next negative clock edge
2392
    @(negedge Mdc_O);
2393
    // read data from MII status register - Busy and Nvalid bits
2394
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2395
 
2396
    // check MII IO signal and Busy and Nvalid bits
2397
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2398
    begin
2399
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2400
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2401
      begin
2402
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2403
        fail = fail + 1;
2404
      end
2405
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2406
      begin
2407
        test_fail("Nvalid signal was set during read");
2408
        fail = fail + 1;
2409
      end
2410
    end
2411
    else // Busy bit should still be set to '1'
2412
    begin
2413
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2414
      begin
2415
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2416
        fail = fail + 1;
2417
      end
2418
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2419
      begin
2420
        test_fail("Nvalid signal was set during read");
2421
        fail = fail + 1;
2422
      end
2423
    end
2424
 
2425
    // wait for next positive clock edge
2426
    @(posedge Mdc_O);
2427
    // read data from MII status register - Busy and Nvalid bits
2428
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2429
 
2430
    // check MII IO signal and Busy and Nvalid bits
2431
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2432
    begin
2433
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2434
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2435
      begin
2436
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2437
        fail = fail + 1;
2438
      end
2439
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2440
      begin
2441
        test_fail("Nvalid signal was set during read");
2442
        fail = fail + 1;
2443
      end
2444
    end
2445
    else // Busy bit should still be set to '1'
2446
    begin
2447
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2448
      begin
2449
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2450
        fail = fail + 1;
2451
      end
2452
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2453
      begin
2454
        test_fail("Nvalid signal was set during read");
2455
        fail = fail + 1;
2456
      end
2457
    end
2458
 
2459
    // wait for Busy to become inactive
2460
    i1 = 0;
2461
    while (i1 <= 2)
2462
    begin
2463
      // wait for next positive clock edge
2464
      @(posedge Mdc_O);
2465
      // read data from MII status register - Busy and Nvalid bits
2466
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2467
 
2468
      // check MII IO signal and Busy and Nvalid bits
2469
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2470
      begin
2471
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2472
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2473
        begin
2474
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2475
          fail = fail + 1;
2476
        end
2477
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2478
        begin
2479
          test_fail("Nvalid signal was set during read");
2480
          fail = fail + 1;
2481
        end
2482
      end
2483
      else // wait for Busy bit to be set to '0'
2484
      begin
2485
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2486
        begin
2487
          i1 = 3; // end of Busy checking
2488
        end
2489
        else
2490
        begin
2491
          if (i1 == 2)
2492
          begin
2493
            test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2494
            fail = fail + 1;
2495
          end
2496
          #Tp i1 = i1 + 1;
2497
        end
2498
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2499
        begin
2500
          test_fail("Nvalid signal was set after read");
2501
          fail = fail + 1;
2502
        end
2503
      end
2504
    end
2505
  end
2506
  // set PHY to normal mode
2507
  #Tp eth_phy.preamble_suppresed(0);
2508
  // MII mode register
2509
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2510
  if(fail == 0)
2511
    test_ok;
2512
  else
2513
    fail = 0;
2514
end
2515
 
2516
 
2517
if ((start_task <= 13) && (end_task >= 13))
2518
begin
2519
  // TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
2520
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
2521
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
2522
 
2523
  reset_mii; // reset MII
2524
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2525
  #Tp eth_phy.link_up_down(1);
2526
  // set the MII
2527
  clk_div = 64;
2528
  mii_set_clk_div(clk_div[7:0]);
2529
  // set address
2530
  reg_addr = 5'h1; // status register
2531
  phy_addr = 5'h1; // correct PHY address
2532
 
2533
  for (i = 0; i <= 1; i = i + 1)
2534
  begin
2535
    #Tp eth_phy.preamble_suppresed(i);
2536
    // MII mode register
2537
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2538
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2539
    @(posedge Mdc_O);
2540
    // scan request
2541
    #Tp mii_scan_req(phy_addr, reg_addr);
2542
    // read data from MII status register - Busy and Nvalid bits
2543
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2544
 
2545
    // check MII IO signal and Busy and Nvalid bits
2546
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2547
    begin
2548
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2549
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2550
      begin
2551
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2552
        fail = fail + 1;
2553
      end
2554
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2555
      begin
2556
        test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2557
        fail = fail + 1;
2558
      end
2559
    end
2560
    else // Busy bit should already be set to '1', due to reads from MII status register
2561
    begin
2562
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2563
      begin
2564
        test_fail("Busy signal should be set after scan, due to reads from MII status register");
2565
        fail = fail + 1;
2566
      end
2567
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2568
      begin
2569
        test_fail("Nvalid signal should be set after scan, due to reads from MII status register");
2570
        fail = fail + 1;
2571
      end
2572
    end
2573
 
2574
    // wait for serial bus to become active
2575
    wait(Mdio_IO !== 1'bz);
2576
    // count transfer bits
2577
    if (i)
2578
    begin
2579
      repeat(21) @(posedge Mdc_O);
2580
    end
2581
    else
2582
    begin
2583
      repeat(53) @(posedge Mdc_O);
2584
    end
2585
    // stop scan
2586
    #Tp mii_scan_finish; // finish scan operation
2587
 
2588
    // wait for next positive clock edge
2589
    repeat(10) @(posedge Mdc_O);
2590
    // read data from MII status register - Busy and Nvalid bits
2591
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2592
 
2593
    // check MII IO signal and Busy and Nvalid bits
2594
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2595
    begin
2596
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2597
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2598
      begin
2599
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2600
        fail = fail + 1;
2601
      end
2602
      // Nvalid signal can be cleared here - it is still Testbench error
2603
    end
2604
    else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2605
    begin
2606
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2607
      begin
2608
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2609
        fail = fail + 1;
2610
      end
2611
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2612
      begin
2613
        test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2614
        fail = fail + 1;
2615
      end
2616
    end
2617
 
2618
    // wait for next negative clock edge
2619
    @(negedge Mdc_O);
2620
    // read data from MII status register - Busy and Nvalid bits
2621
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2622
 
2623
    // check MII IO signal and Busy and Nvalid bits
2624
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2625
    begin
2626
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2627
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2628
      begin
2629
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2630
        fail = fail + 1;
2631
      end
2632
      // Nvalid signal can be cleared here - it is still Testbench error
2633
    end
2634
    else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2635
    begin
2636
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2637
      begin
2638
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2639
        fail = fail + 1;
2640
      end
2641
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2642
      begin
2643
        test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2644
        fail = fail + 1;
2645
      end
2646
    end
2647
 
2648
    // wait for next negative clock edge
2649
    @(posedge Mdc_O);
2650
    // read data from MII status register - Busy and Nvalid bits
2651
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2652
 
2653
    // check MII IO signal and Busy and Nvalid bits
2654
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2655
    begin
2656
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2657
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2658
      begin
2659
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2660
        fail = fail + 1;
2661
      end
2662
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2663
      begin
2664
        test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2665
        fail = fail + 1;
2666
      end
2667
    end
2668
    else // Busy bit should still be set to '1', Nvalid bit can be set to '0'
2669
    begin
2670
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2671
      begin
2672
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2673
        fail = fail + 1;
2674
      end
2675
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2676
      begin
2677
        i2 = 1; // check finished
2678
      end
2679
      else
2680
      begin
2681
        i2 = 0; // check must continue
2682
      end
2683
    end
2684
 
2685
    // wait for Busy to become inactive
2686
    i1 = 0;
2687
    while ((i1 <= 2) || (i2 == 0))
2688
    begin
2689
      // wait for next positive clock edge
2690
      @(posedge Mdc_O);
2691
      // read data from MII status register - Busy and Nvalid bits
2692
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2693
 
2694
      // check MII IO signal and Busy and Nvalid bits
2695
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2696
      begin
2697
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2698
        if (i1 <= 2)
2699
        begin
2700
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2701
          begin
2702
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2703
            fail = fail + 1;
2704
          end
2705
        end
2706
        if (i2 == 0)
2707
        begin
2708
          if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2709
          begin
2710
            test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2711
            fail = fail + 1;
2712
          end
2713
        end
2714
      end
2715
      else // wait for Busy bit to be set to '0'
2716
      begin
2717
        if (i1 <= 2)
2718
        begin
2719
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2720
          begin
2721
            i1 = 3; // end of Busy checking
2722
          end
2723
          else
2724
          begin
2725
            if (i1 == 2)
2726
            begin
2727
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2728
              fail = fail + 1;
2729
            end
2730
            #Tp i1 = i1 + 1;
2731
          end
2732
        end
2733
        if (i2 == 0)
2734
        begin
2735
          if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2736
          begin
2737
            i2 = 1;
2738
          end
2739
          else
2740
          begin
2741
            test_fail("Nvalid signal should be cleared after MII IO signal become HIGH Z");
2742
            fail = fail + 1;
2743
          end
2744
        end
2745
      end
2746
    end
2747
  end
2748
  // set PHY to normal mode
2749
  #Tp eth_phy.preamble_suppresed(0);
2750
  // MII mode register
2751
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2752
  if(fail == 0)
2753
    test_ok;
2754
  else
2755
    fail = 0;
2756
end
2757
 
2758
 
2759
if ((start_task <= 14) && (end_task >= 14))
2760
begin
2761
  // TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
2762
  test_name   = "TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
2763
  `TIME; $display("  TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
2764
 
2765
  reset_mii; // reset MII
2766
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2767
  #Tp eth_phy.link_up_down(1);
2768
  // set MII speed
2769
  clk_div = 6;
2770
  mii_set_clk_div(clk_div[7:0]);
2771
  // set address
2772
  reg_addr = 5'h1; // status register
2773
  phy_addr = 5'h1; // correct PHY address
2774
 
2775
  // read request
2776
  #Tp mii_read_req(phy_addr, reg_addr);
2777
  check_mii_busy; // wait for read to finish
2778
  // read data from PHY status register - remember LINK-UP status
2779
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2780
 
2781
  for (i = 0; i <= 1; i = i + 1)
2782
  begin
2783
    #Tp eth_phy.preamble_suppresed(i);
2784
    // MII mode register
2785
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2786
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2787
    if (i)
2788
    begin
2789
      // change saved data when preamble is suppressed
2790
      #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
2791
    end
2792
 
2793
    // scan request
2794
    #Tp mii_scan_req(phy_addr, reg_addr);
2795
    check_mii_scan_valid; // wait for scan to make first data valid
2796
 
2797
    fork
2798
    begin
2799
      repeat(2) @(posedge Mdc_O);
2800
      // read data from PHY status register
2801
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2802
      if (phy_data !== tmp_data)
2803
      begin
2804
        test_fail("Data was not correctly scaned from status register");
2805
        fail = fail + 1;
2806
      end
2807
      // read data from MII status register
2808
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2809
      if (phy_data[0] !== 1'b0)
2810
      begin
2811
        test_fail("Link FAIL bit was set in the MII status register");
2812
        fail = fail + 1;
2813
      end
2814
    end
2815
    begin
2816
    // Completely check second scan
2817
      #Tp cnt = 0;
2818
      // wait for serial bus to become active - second scan
2819
      wait(Mdio_IO !== 1'bz);
2820
      // count transfer length
2821
      while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
2822
      begin
2823
        @(posedge Mdc_O);
2824
        #Tp cnt = cnt + 1;
2825
      end
2826
      // check transfer length
2827
      if (i) // without preamble
2828
      begin
2829
        if (cnt != 33) // at this value Mdio_IO is HIGH Z
2830
        begin
2831
          test_fail("Second scan request did not proceed correctly");
2832
          fail = fail + 1;
2833
        end
2834
      end
2835
      else // with preamble
2836
      begin
2837
        if (cnt != 65) // at this value Mdio_IO is HIGH Z
2838
        begin
2839
          test_fail("Second scan request did not proceed correctly");
2840
          fail = fail + 1;
2841
        end
2842
      end
2843
    end
2844
    join
2845
    // check third to fifth scans
2846
    for (i3 = 0; i3 <= 2; i3 = i3 + 1)
2847
    begin
2848
      fork
2849
      begin
2850
        repeat(2) @(posedge Mdc_O);
2851
        // read data from PHY status register
2852
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2853
        if (phy_data !== tmp_data)
2854
        begin
2855
          test_fail("Data was not correctly scaned from status register");
2856
          fail = fail + 1;
2857
        end
2858
        // read data from MII status register
2859
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2860
        if (phy_data[0] !== 1'b0)
2861
        begin
2862
          test_fail("Link FAIL bit was set in the MII status register");
2863
          fail = fail + 1;
2864
        end
2865
        if (i3 == 2) // after fourth scan read
2866
        begin
2867
          @(posedge Mdc_O);
2868
          // change saved data
2869
          #Tp tmp_data = tmp_data & 16'hFFFB; // put bit 3 to ZERO
2870
          // set link down
2871
          #Tp eth_phy.link_up_down(0);
2872
        end
2873
      end
2874
      begin
2875
      // Completely check scans
2876
        #Tp cnt = 0;
2877
        // wait for serial bus to become active - second scan
2878
        wait(Mdio_IO !== 1'bz);
2879
        // count transfer length
2880
        while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
2881
        begin
2882
          @(posedge Mdc_O);
2883
          #Tp cnt = cnt + 1;
2884
        end
2885
        // check transfer length
2886
        if (i) // without preamble
2887
        begin
2888
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2889
          begin
2890
            test_fail("Fifth scan request did not proceed correctly");
2891
            fail = fail + 1;
2892
          end
2893
        end
2894
        else // with preamble
2895
        begin
2896
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2897
          begin
2898
            test_fail("Fifth scan request did not proceed correctly");
2899
            fail = fail + 1;
2900
          end
2901
        end
2902
      end
2903
      join
2904
    end
2905
 
2906
    fork
2907
    begin
2908
      repeat(2) @(posedge Mdc_O);
2909
      // read data from PHY status register
2910
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2911
      if (phy_data !== tmp_data)
2912
      begin
2913
        test_fail("Data was not correctly scaned from status register");
2914
        fail = fail + 1;
2915
      end
2916
      // read data from MII status register
2917
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2918
      if (phy_data[0] === 1'b0)
2919
      begin
2920
        test_fail("Link FAIL bit was not set in the MII status register");
2921
        fail = fail + 1;
2922
      end
2923
      // wait to see if data stayed latched
2924
      repeat(4) @(posedge Mdc_O);
2925
      // read data from PHY status register
2926
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2927
      if (phy_data !== tmp_data)
2928
      begin
2929
        test_fail("Data was not latched correctly in status register");
2930
        fail = fail + 1;
2931
      end
2932
      // read data from MII status register
2933
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2934
      if (phy_data[0] === 1'b0)
2935
      begin
2936
        test_fail("Link FAIL bit was not set in the MII status register");
2937
        fail = fail + 1;
2938
      end
2939
      // change saved data
2940
      #Tp tmp_data = tmp_data | 16'h0004; // put bit 2 to ONE
2941
      // set link up
2942
      #Tp eth_phy.link_up_down(1);
2943
    end
2944
    begin
2945
    // Wait for sixth scan
2946
      // wait for serial bus to become active - sixth scan
2947
      wait(Mdio_IO !== 1'bz);
2948
      // wait for serial bus to become inactive - turn-around cycle in sixth scan
2949
      wait(Mdio_IO === 1'bz);
2950
      // wait for serial bus to become active - end of turn-around cycle in sixth scan
2951
      wait(Mdio_IO !== 1'bz);
2952
      // wait for serial bus to become inactive - end of sixth scan
2953
      wait(Mdio_IO === 1'bz);
2954
    end
2955
    join
2956
 
2957
    @(posedge Mdc_O);
2958
    // read data from PHY status register
2959
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2960
    if (phy_data !== tmp_data)
2961
    begin
2962
      test_fail("Data was not correctly scaned from status register");
2963
      fail = fail + 1;
2964
    end
2965
    // read data from MII status register
2966
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2967
    if (phy_data[0] !== 1'b0)
2968
    begin
2969
      test_fail("Link FAIL bit was set in the MII status register");
2970
      fail = fail + 1;
2971
    end
2972
    // wait to see if data stayed latched
2973
    repeat(4) @(posedge Mdc_O);
2974
    // read data from PHY status register
2975
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2976
    if (phy_data !== tmp_data