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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Blame information for rev 170

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1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet.v                                               ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 169 mohor
////      - Tadej Markovic, tadej@opencores.org                   ////
10 170 mohor
////      - Igor Mohor,     igormM@opencores.org                  ////
11 116 mohor
////                                                              ////
12 169 mohor
////  All additional information is available in the Readme.txt   ////
13 116 mohor
////  file.                                                       ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2001, 2002 Authors                             ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 170 mohor
// Revision 1.6  2002/09/13 11:57:20  mohor
46
// New testbench. Thanks to Tadej M - "The Spammer".
47
//
48 121 mohor
// Revision 1.2  2002/07/19 14:02:47  mohor
49
// Clock mrx_clk set to 2.5 MHz.
50
//
51 117 mohor
// Revision 1.1  2002/07/19 13:57:53  mohor
52
// Testing environment also includes traffic cop, memory interface and host
53
// interface.
54 116 mohor
//
55
//
56
//
57
//
58 117 mohor
//
59 116 mohor
 
60
 
61 169 mohor
`define TIME $display("  Time: %0t", $time)
62 116 mohor
 
63 169 mohor
`include "eth_phy_defines.v"
64
`include "wb_model_defines.v"
65 116 mohor
`include "tb_eth_defines.v"
66
`include "eth_defines.v"
67
`include "timescale.v"
68
 
69
module tb_ethernet();
70
 
71
 
72 169 mohor
reg           wb_clk;
73
reg           wb_rst;
74
wire          wb_int;
75 116 mohor
 
76 169 mohor
wire          mtx_clk;  // This goes to PHY
77
wire          mrx_clk;  // This goes to PHY
78 116 mohor
 
79
wire   [3:0]  MTxD;
80
wire          MTxEn;
81
wire          MTxErr;
82
 
83 169 mohor
wire   [3:0]  MRxD;     // This goes to PHY
84
wire          MRxDV;    // This goes to PHY
85
wire          MRxErr;   // This goes to PHY
86
wire          MColl;    // This goes to PHY
87
wire          MCrs;     // This goes to PHY
88 116 mohor
 
89
wire          Mdi_I;
90
wire          Mdo_O;
91
wire          Mdo_OE;
92 169 mohor
tri           Mdio_IO;
93 116 mohor
wire          Mdc_O;
94
 
95
 
96 169 mohor
parameter Tp = 1;
97 116 mohor
 
98 121 mohor
 
99 116 mohor
// Ethernet Slave Interface signals
100 169 mohor
wire [31:0] eth_sl_wb_adr;
101 116 mohor
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
102
wire  [3:0] eth_sl_wb_sel_i;
103
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
104
 
105
// Ethernet Master Interface signals
106
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
107
wire  [3:0] eth_ma_wb_sel_o;
108
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
109
 
110
 
111
 
112
 
113
// Connecting Ethernet top module
114 169 mohor
eth_top eth_top
115 116 mohor
(
116
  // WISHBONE common
117 169 mohor
  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),
118 116 mohor
 
119
  // WISHBONE slave
120 169 mohor
  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
121
  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
122
  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
123 116 mohor
 
124
  // WISHBONE master
125
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
126
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
127
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
128
 
129
  //TX
130
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
131
 
132
  //RX
133
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
134
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
135
 
136
  // MIIM
137
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
138
 
139 169 mohor
  .int_o(wb_int)
140 116 mohor
);
141
 
142
 
143
 
144 169 mohor
// Connecting Ethernet PHY Module
145
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
146
assign Mdi_I   = Mdio_IO;
147
integer phy_log_file_desc;
148
 
149
eth_phy eth_phy
150 116 mohor
(
151 169 mohor
  // WISHBONE reset
152
  .m_rst_n_i(!wb_rst),
153 116 mohor
 
154 169 mohor
  // MAC TX
155
  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),
156
 
157
  // MAC RX
158
  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),
159
  .mcoll_o(MColl),        .mcrs_o(MCrs),
160
 
161
  // MIIM
162
  .mdc_i(Mdc_O),          .md_io(Mdio_IO),
163
 
164
  // SYSTEM
165
  .phy_log(phy_log_file_desc)
166 116 mohor
);
167
 
168
 
169 169 mohor
 
170
// Connecting WB Master as Host Interface
171
integer host_log_file_desc;
172
 
173
WB_MASTER_BEHAVIORAL wb_master
174 116 mohor
(
175 169 mohor
    .CLK_I(wb_clk),
176
    .RST_I(wb_rst),
177
    .TAG_I({`WB_TAG_WIDTH{1'b0}}),
178
    .TAG_O(),
179
    .ACK_I(eth_sl_wb_ack_o),
180
    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
181
    .CYC_O(eth_sl_wb_cyc_i),
182
    .DAT_I(eth_sl_wb_dat_o),
183
    .DAT_O(eth_sl_wb_dat_i),
184
    .ERR_I(eth_sl_wb_err_o),
185
    .RTY_I(1'b0),  // inactive (1'b0)
186
    .SEL_O(eth_sl_wb_sel_i),
187
    .STB_O(eth_sl_wb_stb_i),
188
    .WE_O (eth_sl_wb_we_i),
189
    .CAB_O()       // NOT USED for now!
190
);
191
 
192
assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
193
 
194
 
195
 
196
// Connecting WB Slave as Memory Interface Module
197
integer memory_log_file_desc;
198
 
199
WB_SLAVE_BEHAVIORAL wb_slave
200
(
201
    .CLK_I(wb_clk),
202
    .RST_I(wb_rst),
203
    .ACK_O(eth_ma_wb_ack_i),
204
    .ADR_I(eth_ma_wb_adr_o),
205
    .CYC_I(eth_ma_wb_cyc_o),
206
    .DAT_O(eth_ma_wb_dat_i),
207
    .DAT_I(eth_ma_wb_dat_o),
208
    .ERR_O(eth_ma_wb_err_i),
209
    .RTY_O(),      // NOT USED for now!
210
    .SEL_I(eth_ma_wb_sel_o),
211
    .STB_I(eth_ma_wb_stb_o),
212
    .WE_I (eth_ma_wb_we_o),
213
    .CAB_I(1'b0)   // inactive (1'b0)
214
);
215
 
216
 
217
 
218
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
219
integer wb_s_mon_log_file_desc ;
220
integer wb_m_mon_log_file_desc ;
221
 
222
WB_BUS_MON wb_eth_slave_bus_mon
223
(
224 116 mohor
  // WISHBONE common
225 169 mohor
  .CLK_I(wb_clk),
226
  .RST_I(wb_rst),
227 116 mohor
 
228 169 mohor
  // WISHBONE slave
229
  .ACK_I(eth_sl_wb_ack_o),
230
  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),
231
  .CYC_O(eth_sl_wb_cyc_i),
232
  .DAT_I(eth_sl_wb_dat_o),
233
  .DAT_O(eth_sl_wb_dat_i),
234
  .ERR_I(eth_sl_wb_err_o),
235
  .RTY_I(1'b0),
236
  .SEL_O(eth_sl_wb_sel_i),
237
  .STB_O(eth_sl_wb_stb_i),
238
  .WE_O (eth_sl_wb_we_i),
239
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
240
  .TAG_O(),
241
  .CAB_O(1'b0),
242
  .log_file_desc (wb_s_mon_log_file_desc)
243
);
244
 
245
WB_BUS_MON wb_eth_master_bus_mon
246
(
247
  // WISHBONE common
248
  .CLK_I(wb_clk),
249
  .RST_I(wb_rst),
250
 
251 116 mohor
  // WISHBONE master
252 169 mohor
  .ACK_I(eth_ma_wb_ack_i),
253
  .ADDR_O(eth_ma_wb_adr_o),
254
  .CYC_O(eth_ma_wb_cyc_o),
255
  .DAT_I(eth_ma_wb_dat_i),
256
  .DAT_O(eth_ma_wb_dat_o),
257
  .ERR_I(eth_ma_wb_err_i),
258
  .RTY_I(1'b0),
259
  .SEL_O(eth_ma_wb_sel_o),
260
  .STB_O(eth_ma_wb_stb_o),
261
  .WE_O (eth_ma_wb_we_o),
262
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
263
  .TAG_O(),
264
  .CAB_O(1'b0),
265
  .log_file_desc(wb_m_mon_log_file_desc)
266 116 mohor
);
267
 
268
 
269
 
270 169 mohor
reg         StartTB;
271
integer     tb_log_file;
272 116 mohor
 
273 169 mohor
initial
274
begin
275
  tb_log_file = $fopen("../log/eth_tb.log");
276
  if (tb_log_file < 2)
277
  begin
278
    $display("*E Could not open/create testbench log file in ../log/ directory!");
279
    $finish;
280
  end
281
  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");
282
  $fdisplay(tb_log_file, " ");
283 116 mohor
 
284 169 mohor
  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");
285
  if (phy_log_file_desc < 2)
286
  begin
287
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");
288
    $finish;
289
  end
290
  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");
291
  $fdisplay(phy_log_file_desc, " ");
292
 
293
  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");
294
  if (memory_log_file_desc < 2)
295
  begin
296
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");
297
    $finish;
298
  end
299
  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");
300
  $fdisplay(memory_log_file_desc, " ");
301
 
302
  host_log_file_desc = $fopen("../log/eth_tb_host.log");
303
  if (host_log_file_desc < 2)
304
  begin
305
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");
306
    $finish;
307
  end
308
  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");
309
  $fdisplay(host_log_file_desc, " ");
310
 
311
  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");
312
  if (wb_s_mon_log_file_desc < 2)
313
  begin
314
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");
315
    $finish;
316
  end
317
  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");
318
  $fdisplay(wb_s_mon_log_file_desc, " ");
319
  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
320
  $fdisplay(wb_s_mon_log_file_desc, " ");
321
 
322
  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");
323
  if (wb_m_mon_log_file_desc < 2)
324
  begin
325
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");
326
    $finish;
327
  end
328
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
329
  $fdisplay(wb_m_mon_log_file_desc, " ");
330
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
331
  $fdisplay(wb_m_mon_log_file_desc, " ");
332
 
333
  // Clear memories
334
  clear_memories;
335
 
336
  // Reset pulse
337
  wb_rst =  1'b1;
338
  #423 wb_rst =  1'b0;
339
  #423 StartTB  =  1'b1;
340
end
341
 
342
 
343
 
344
// Generating wb_clk clock
345 116 mohor
initial
346
begin
347 169 mohor
  wb_clk=0;
348
//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    
349
//  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    
350
//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    
351
//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    
352
//  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    
353
  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    
354
//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz
355
//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    
356
//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz
357
//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    
358 116 mohor
end
359
 
360
 
361
 
362 169 mohor
integer      tests_successfull;
363
integer      tests_failed;
364
reg [799:0]  test_name; // used for tb_log_file
365 121 mohor
 
366 169 mohor
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
367
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
368
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
369
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
370
 
371 116 mohor
initial
372
begin
373 169 mohor
  wait(StartTB);  // Start of testbench
374
 
375
  // Initial global values
376
  tests_successfull = 0;
377
  tests_failed = 0;
378
 
379
  wbm_init_waits = 4'h1;
380
  wbm_subseq_waits = 4'h3;
381
  wbs_waits = 4'h1;
382
  wbs_retries = 8'h2;
383
  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
384
 
385
 
386
  //  Call tests
387
  //  ----------
388
    test_access_to_mac_reg(0, 3);          // 0 - 3
389
    test_mii(0, 17);                        // 0 - 17
390
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
391
  eth_phy.carrier_sense_real_delay(0);
392
    test_mac_full_duplex_transmit(0, 3);   // 0 - (3)
393
 
394
  test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
395
  eth_phy.carrier_sense_real_delay(1);
396
 
397
 
398
  // Finish test's logs
399
  test_summary;
400
  $display("\n\n END of SIMULATION");
401
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
402
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);
403
 
404
  $stop;
405 116 mohor
end
406 169 mohor
 
407 116 mohor
 
408 169 mohor
 
409
//////////////////////////////////////////////////////////////
410
// Test tasks
411
//////////////////////////////////////////////////////////////
412
 
413
task test_access_to_mac_reg;
414
  input  [31:0]  start_task;
415
  input  [31:0]  end_task;
416
  integer        bit_start_1;
417
  integer        bit_end_1;
418
  integer        bit_start_2;
419
  integer        bit_end_2;
420
  integer        num_of_reg;
421
  integer        i_addr;
422
  integer        i_data;
423
  integer        i_length;
424
  integer        tmp_data;
425
  reg    [31:0]  tx_bd_num;
426
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
427
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
428
  integer        i;
429
  integer        i1;
430
  integer        i2;
431
  integer        i3;
432
  integer        fail;
433
  reg    [31:0]  addr;
434
  reg    [31:0]  data;
435
  reg    [31:0]  data_max;
436 116 mohor
begin
437 169 mohor
// ACCESS TO MAC REGISTERS TEST
438
test_heading("ACCESS TO MAC REGISTERS TEST");
439
$display(" ");
440
$display("ACCESS TO MAC REGISTERS TEST");
441
fail = 0;
442
 
443
  /* Register space
444
     --------------
445
  `define ETH_MODER      `ETH_BASE + 32'h00      Mode Register
446
  `define ETH_INT        `ETH_BASE + 32'h04      Interrupt Source Register
447
  `define ETH_INT_MASK   `ETH_BASE + 32'h08      Interrupt Mask Register
448
  `define ETH_IPGT       `ETH_BASE + 32'h0C      Back to Bak Inter Packet Gap Register
449
  `define ETH_IPGR1      `ETH_BASE + 32'h10      Non Back to Back Inter Packet Gap Register 1
450
  `define ETH_IPGR2      `ETH_BASE + 32'h14      Non Back to Back Inter Packet Gap Register 2
451
  `define ETH_PACKETLEN  `ETH_BASE + 32'h18      Packet Length Register (min. and max.)
452
  `define ETH_COLLCONF   `ETH_BASE + 32'h1C      Collision and Retry Configuration Register
453
  `define ETH_TX_BD_NUM  `ETH_BASE + 32'h20      Transmit Buffer Descriptor Number Register
454
  `define ETH_CTRLMODER  `ETH_BASE + 32'h24      Control Module Mode Register
455
  `define ETH_MIIMODER   `ETH_BASE + 32'h28      MII Mode Register
456
  `define ETH_MIICOMMAND `ETH_BASE + 32'h2C      MII Command Register
457
  `define ETH_MIIADDRESS `ETH_BASE + 32'h30      MII Address Register
458
  `define ETH_MIITX_DATA `ETH_BASE + 32'h34      MII Transmit Data Register
459
  `define ETH_MIIRX_DATA `ETH_BASE + 32'h38      MII Receive Data Register
460
  `define ETH_MIISTATUS  `ETH_BASE + 32'h3C      MII Status Register
461
  `define ETH_MAC_ADDR0  `ETH_BASE + 32'h40      MAC Individual Address Register 0
462
  `define ETH_MAC_ADDR1  `ETH_BASE + 32'h44      MAC Individual Address Register 1
463
  `define ETH_HASH_ADDR0 `ETH_BASE + 32'h48      Hash Register 0
464
  `define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C      Hash Register 1
465
  */
466
 
467
 
468
if ((start_task <= 0) && (end_task >= 0))
469
begin
470
  // TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
471
  test_name   = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
472
  `TIME; $display("  TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
473
 
474
  data = 0;
475
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
476
  begin
477
      wbm_init_waits = i;
478
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
479
      for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
480
      begin
481
        addr = `ETH_BASE + i_addr;
482
        // set ranges of R/W bits
483
        case (addr)
484
        `ETH_MODER:
485
          begin
486
            bit_start_1 = 0;
487
            bit_end_1   = 16;
488
            bit_start_2 = 32; // not used
489
            bit_end_2   = 32; // not used
490
          end
491
        `ETH_INT: // READONLY - tested within INT test
492
          begin
493
            bit_start_1 = 32; // not used
494
            bit_end_1   = 32; // not used
495
            bit_start_2 = 32; // not used
496
            bit_end_2   = 32; // not used
497
          end
498
        `ETH_INT_MASK:
499
          begin
500
            bit_start_1 = 0;
501
            bit_end_1   = 6;
502
            bit_start_2 = 32; // not used
503
            bit_end_2   = 32; // not used
504
          end
505
        `ETH_IPGT:
506
          begin
507
            bit_start_1 = 0;
508
            bit_end_1   = 6;
509
            bit_start_2 = 32; // not used
510
            bit_end_2   = 32; // not used
511
          end
512
        `ETH_IPGR1:
513
          begin
514
            bit_start_1 = 0;
515
            bit_end_1   = 6;
516
            bit_start_2 = 32; // not used
517
            bit_end_2   = 32; // not used
518
          end
519
        `ETH_IPGR2:
520
          begin
521
            bit_start_1 = 0;
522
            bit_end_1   = 6;
523
            bit_start_2 = 32; // not used
524
            bit_end_2   = 32; // not used
525
          end
526
        `ETH_PACKETLEN:
527
          begin
528
            bit_start_1 = 0;
529
            bit_end_1   = 31;
530
            bit_start_2 = 32; // not used
531
            bit_end_2   = 32; // not used
532
          end
533
        `ETH_COLLCONF:
534
          begin
535
            bit_start_1 = 0;
536
            bit_end_1   = 5;
537
            bit_start_2 = 16;
538
            bit_end_2   = 19;
539
          end
540
        `ETH_TX_BD_NUM:
541
          begin
542
            bit_start_1 = 0;
543
            bit_end_1   = 7;
544
            bit_start_2 = 32; // not used
545
            bit_end_2   = 32; // not used
546
          end
547
        `ETH_CTRLMODER:
548
          begin
549
            bit_start_1 = 0;
550
            bit_end_1   = 2;
551
            bit_start_2 = 32; // not used
552
            bit_end_2   = 32; // not used
553
          end
554
        `ETH_MIIMODER:
555
          begin
556
            bit_start_1 = 0;
557
            bit_end_1   = 9;
558
            bit_start_2 = 32; // not used
559
            bit_end_2   = 32; // not used
560
          end
561
        `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
562
          begin
563
            bit_start_1 = 32; // not used
564
            bit_end_1   = 32; // not used
565
            bit_start_2 = 32; // not used
566
            bit_end_2   = 32; // not used
567
          end
568
        `ETH_MIIADDRESS:
569
          begin
570
            bit_start_1 = 0;
571
            bit_end_1   = 4;
572
            bit_start_2 = 8;
573
            bit_end_2   = 12;
574
          end
575
        `ETH_MIITX_DATA:
576
          begin
577
            bit_start_1 = 0;
578
            bit_end_1   = 15;
579
            bit_start_2 = 32; // not used
580
            bit_end_2   = 32; // not used
581
          end
582
        `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
583
          begin
584
            bit_start_1 = 32; // not used
585
            bit_end_1   = 32; // not used
586
            bit_start_2 = 32; // not used
587
            bit_end_2   = 32; // not used
588
          end
589
        `ETH_MIISTATUS: // READONLY - tested within MIIM test
590
          begin
591
            bit_start_1 = 32; // not used
592
            bit_end_1   = 32; // not used
593
            bit_start_2 = 32; // not used
594
            bit_end_2   = 32; // not used
595
          end
596
        `ETH_MAC_ADDR0:
597
          begin
598
            bit_start_1 = 0;
599
            bit_end_1   = 31;
600
            bit_start_2 = 32; // not used
601
            bit_end_2   = 32; // not used
602
          end
603
        `ETH_MAC_ADDR1:
604
          begin
605
            bit_start_1 = 0;
606
            bit_end_1   = 15;
607
            bit_start_2 = 32; // not used
608
            bit_end_2   = 32; // not used
609
          end
610
        `ETH_HASH_ADDR0:
611
          begin
612
            bit_start_1 = 0;
613
            bit_end_1   = 31;
614
            bit_start_2 = 32; // not used
615
            bit_end_2   = 32; // not used
616
          end
617
        default: // `ETH_HASH_ADDR1:
618
          begin
619
            bit_start_1 = 0;
620
            bit_end_1   = 31;
621
            bit_start_2 = 32; // not used
622
            bit_end_2   = 32; // not used
623
          end
624
        endcase
625
        for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
626
        begin
627
          data = 1'b1 << i_data;
628
          if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
629
          begin
630
          end
631
          else
632
          begin
633
            wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
634
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
635
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
636
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
637
            begin
638
              if (tmp_data !== data)
639
              begin
640
                fail = fail + 1;
641
                test_fail("RW bit of the MAC register was not written or not read");
642
                `TIME;
643
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
644
                          wbm_init_waits, addr, data, tmp_data);
645
              end
646
            end
647
            else // data should not be equal to tmp_data
648
            begin
649
              if (tmp_data === data)
650
              begin
651
                fail = fail + 1;
652
                test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
653
                `TIME;
654
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
655
                          wbm_init_waits, addr, data, tmp_data);
656
              end
657
            end
658
          end
659
        end
660
      end
661
  end
662
  if(fail == 0)
663
    test_ok;
664
  else
665
    fail = 0;    // Errors were reported previously
666 116 mohor
end
667
 
668 169 mohor
 
669
if ((start_task <= 4) && (end_task >= 4)) // not used, since burst access to reg. is not supported
670 116 mohor
begin
671 169 mohor
/*  // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
672
  test_name   = "TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
673
  `TIME; $display("  TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
674
 
675
  data = 0;
676
  burst_data = 0;
677
  burst_tmp_data = 0;
678
  i_length = 10; // two bursts for length 20
679
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
680
  begin
681
    for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
682
    begin
683
      wbm_init_waits = i;
684
      wbm_subseq_waits = i1;
685
      #1;
686
      for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
687
      begin
688
        data = 1'b1 << i_data;
689
        #1;
690
        for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
691
        begin
692
          burst_data = burst_data << 32;
693
          // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
694
          if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
695
          begin
696
            #1 burst_data[31:0] = 0;
697
          end
698
          else
699
          begin
700
            #1 burst_data[31:0] = data;
701
          end
702
        end
703
        #1;
704
        // 2 burst writes
705
        addr = `ETH_BASE; // address of a first burst
706
        wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
707
        burst_tmp_data = burst_data >> (32 * i_length);
708
        addr = addr + 32'h28; // address of a second burst
709
        wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
710
        #1;
711
        // 2 burst reads
712
        addr = `ETH_BASE; // address of a first burst
713
        wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
714
                 wbm_init_waits, wbm_subseq_waits); // first burst
715
        burst_tmp_data = burst_tmp_data << (32 * i_length);
716
        addr = addr + 32'h28; // address of a second burst
717
        wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
718
                 wbm_init_waits, wbm_subseq_waits); // second burst
719
        #1;
720
        for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
721
        begin
722
          // set ranges of R/W bits
723
          case (`ETH_BASE + i2)
724
          `ETH_MODER:
725
            begin
726
              bit_start_1 = 0;
727
              bit_end_1   = 16;
728
              bit_start_2 = 32; // not used
729
              bit_end_2   = 32; // not used
730
            end
731
          `ETH_INT: // READONLY - tested within INT test
732
            begin
733
              bit_start_1 = 32; // not used
734
              bit_end_1   = 32; // not used
735
              bit_start_2 = 32; // not used
736
              bit_end_2   = 32; // not used
737
            end
738
          `ETH_INT_MASK:
739
            begin
740
              bit_start_1 = 0;
741
              bit_end_1   = 6;
742
              bit_start_2 = 32; // not used
743
              bit_end_2   = 32; // not used
744
            end
745
          `ETH_IPGT:
746
            begin
747
              bit_start_1 = 0;
748
              bit_end_1   = 6;
749
              bit_start_2 = 32; // not used
750
              bit_end_2   = 32; // not used
751
            end
752
          `ETH_IPGR1:
753
            begin
754
              bit_start_1 = 0;
755
              bit_end_1   = 6;
756
              bit_start_2 = 32; // not used
757
              bit_end_2   = 32; // not used
758
            end
759
          `ETH_IPGR2:
760
            begin
761
              bit_start_1 = 0;
762
              bit_end_1   = 6;
763
              bit_start_2 = 32; // not used
764
              bit_end_2   = 32; // not used
765
            end
766
          `ETH_PACKETLEN:
767
            begin
768
              bit_start_1 = 0;
769
              bit_end_1   = 31;
770
              bit_start_2 = 32; // not used
771
              bit_end_2   = 32; // not used
772
            end
773
          `ETH_COLLCONF:
774
            begin
775
              bit_start_1 = 0;
776
              bit_end_1   = 5;
777
              bit_start_2 = 16;
778
              bit_end_2   = 19;
779
            end
780
          `ETH_TX_BD_NUM:
781
            begin
782
              bit_start_1 = 0;
783
              bit_end_1   = 7;
784
              bit_start_2 = 32; // not used
785
              bit_end_2   = 32; // not used
786
            end
787
          `ETH_CTRLMODER:
788
            begin
789
              bit_start_1 = 0;
790
              bit_end_1   = 2;
791
              bit_start_2 = 32; // not used
792
              bit_end_2   = 32; // not used
793
            end
794
          `ETH_MIIMODER:
795
            begin
796
              bit_start_1 = 0;
797
              bit_end_1   = 9;
798
              bit_start_2 = 32; // not used
799
              bit_end_2   = 32; // not used
800
            end
801
          `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
802
            begin
803
              bit_start_1 = 32; // not used
804
              bit_end_1   = 32; // not used
805
              bit_start_2 = 32; // not used
806
              bit_end_2   = 32; // not used
807
            end
808
          `ETH_MIIADDRESS:
809
            begin
810
              bit_start_1 = 0;
811
              bit_end_1   = 4;
812
              bit_start_2 = 8;
813
              bit_end_2   = 12;
814
            end
815
          `ETH_MIITX_DATA:
816
            begin
817
              bit_start_1 = 0;
818
              bit_end_1   = 15;
819
              bit_start_2 = 32; // not used
820
              bit_end_2   = 32; // not used
821
            end
822
          `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
823
            begin
824
              bit_start_1 = 32; // not used
825
              bit_end_1   = 32; // not used
826
              bit_start_2 = 32; // not used
827
              bit_end_2   = 32; // not used
828
            end
829
          `ETH_MIISTATUS: // READONLY - tested within MIIM test
830
            begin
831
              bit_start_1 = 32; // not used
832
              bit_end_1   = 32; // not used
833
              bit_start_2 = 32; // not used
834
              bit_end_2   = 32; // not used
835
            end
836
          `ETH_MAC_ADDR0:
837
            begin
838
              bit_start_1 = 0;
839
              bit_end_1   = 31;
840
              bit_start_2 = 32; // not used
841
              bit_end_2   = 32; // not used
842
            end
843
          `ETH_MAC_ADDR1:
844
            begin
845
              bit_start_1 = 0;
846
              bit_end_1   = 15;
847
              bit_start_2 = 32; // not used
848
              bit_end_2   = 32; // not used
849
            end
850
          `ETH_HASH_ADDR0:
851
            begin
852
              bit_start_1 = 0;
853
              bit_end_1   = 31;
854
              bit_start_2 = 32; // not used
855
              bit_end_2   = 32; // not used
856
            end
857
          default: // `ETH_HASH_ADDR1:
858
            begin
859
              bit_start_1 = 0;
860
              bit_end_1   = 31;
861
              bit_start_2 = 32; // not used
862
              bit_end_2   = 32; // not used
863
            end
864
          endcase
865
          #1;
866
          // 3 LSBits of MIICOMMAND are NOT written !!!
867
          if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
868
          begin
869
            if (burst_tmp_data[31:0] !== burst_data[31:0])
870
            begin
871
              fail = fail + 1;
872
              test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
873
              `TIME;
874
              $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
875
                        wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
876
            end
877
          end
878
          else
879
          begin
880
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
881
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
882
            begin
883
              if (burst_tmp_data[31:0] !== burst_data[31:0])
884
              begin
885
                fail = fail + 1;
886
                test_fail("RW bit of the MAC register was not written or not read");
887
                `TIME;
888
                $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
889
                          wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
890
              end
891
            end
892
            else // data should not be equal to tmp_data
893
            begin
894
              if (burst_tmp_data[31:0] === burst_data[31:0])
895
              begin
896
                fail = fail + 1;
897
                test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
898
                `TIME;
899
                $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
900
                          wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
901
              end
902
            end
903
          end
904
          burst_tmp_data = burst_tmp_data >> 32;
905
          burst_data = burst_data >> 32;
906
        end
907
      end
908
    end
909
  end
910
  if(fail == 0)
911
    test_ok;
912
  else
913
    fail = 0;*/
914 116 mohor
end
915
 
916 169 mohor
 
917
if ((start_task <= 1) && (end_task >= 1))
918 116 mohor
begin
919 169 mohor
  // TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
920
  test_name   = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
921
  `TIME; $display("  TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
922 116 mohor
 
923 169 mohor
  data = 0;
924
  // set TX and RX buffer descriptors
925
  tx_bd_num = 32'h40;
926
  wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
927
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
928
  begin
929
    wbm_init_waits = i;
930
    wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
931
    for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
932
    begin
933
      addr = `ETH_BASE + i_addr;
934
      if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
935
      begin
936
        // set ranges of R/W bits
937
        case (addr[3])
938
        1'b0: // buffer control bits
939
          begin
940
            bit_start_1 = 0;
941
            bit_end_1   = 31; // 8;
942
            bit_start_2 = 11;
943
            bit_end_2   = 31;
944
          end
945
        default: // 1'b1: // buffer pointer
946
          begin
947
            bit_start_1 = 0;
948
            bit_end_1   = 31;
949
            bit_start_2 = 32; // not used
950
            bit_end_2   = 32; // not used
951
          end
952
        endcase
953
      end
954
      else // RX buffer descriptors
955
      begin
956
        // set ranges of R/W bits
957
        case (addr[3])
958
        1'b0: // buffer control bits
959
          begin
960
            bit_start_1 = 0;
961
            bit_end_1   = 31; // 7;
962
            bit_start_2 = 13;
963
            bit_end_2   = 31;
964
          end
965
        default: // 1'b1: // buffer pointer
966
          begin
967
            bit_start_1 = 0;
968
            bit_end_1   = 31;
969
            bit_start_2 = 32; // not used
970
            bit_end_2   = 32; // not used
971
          end
972
        endcase
973
      end
974 116 mohor
 
975 169 mohor
      for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
976
      begin
977
        data = 1'b1 << i_data;
978
        if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
979
        begin
980
        end
981
        else
982
        begin
983
          wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
984
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
985
          if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
986
               ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
987
          begin
988
            if (tmp_data !== data)
989
            begin
990
              fail = fail + 1;
991
              test_fail("RW bit of the MAC buffer descriptors was not written or not read");
992
              `TIME;
993
              $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
994
                        wbm_init_waits, addr, data, tmp_data);
995
            end
996
          end
997
          else // data should not be equal to tmp_data
998
          begin
999
            if (tmp_data === data)
1000
            begin
1001
              fail = fail + 1;
1002
              test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
1003
              `TIME;
1004
              $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
1005
                        wbm_init_waits, addr, data, tmp_data);
1006
            end
1007
          end
1008
        end
1009
      end
1010
    end
1011
    case (i)
1012
    0:       $display("    buffer descriptors tested with 0 bus delay");
1013
    1:       $display("    buffer descriptors tested with 1 bus delay cycle");
1014
    2:       $display("    buffer descriptors tested with 2 bus delay cycles");
1015
    3:       $display("    buffer descriptors tested with 3 bus delay cycles");
1016
    default: $display("    buffer descriptors tested with 4 bus delay cycles");
1017
    endcase
1018
  end
1019
  if(fail == 0)
1020
    test_ok;
1021
  else
1022
    fail = 0;
1023
end
1024 116 mohor
 
1025 169 mohor
  /* Register      RESET values    MAX. values
1026
     -----------------------------------------
1027
   ETH_MODER       32'h0000_A800   32'h0000_A800   Mode Register
1028
   ETH_INT         32'h0000_0000   32'h0000_0000   Interrupt Source Register
1029
   ETH_INT_MASK    32'h0000_0000   32'h0000_0000   Interrupt Mask Register
1030
   ETH_IPGT        32'h0000_0012   32'h0000_0012   Back to Bak Inter Packet Gap Register
1031
   ETH_IPGR1       32'h0000_000C   32'h0000_000C   Non Back to Back Inter Packet Gap Register 1
1032
   ETH_IPGR2       32'h0000_0012   32'h0000_0012   Non Back to Back Inter Packet Gap Register 2
1033
   ETH_PACKETLEN   32'h0040_0600   32'h0040_0600   Packet Length Register (min. and max.)
1034
   ETH_COLLCONF    32'h000F_003F   32'h000F_003F   Collision and Retry Configuration Register
1035
   ETH_TX_BD_NUM   32'h0000_0040   32'h0000_0080   Transmit Buffer Descriptor Number Register
1036
   ETH_CTRLMODER   32'h0000_0000   32'h0000_0000   Control Module Mode Register
1037
   ETH_MIIMODER    32'h0000_0064   32'h0000_0064   MII Mode Register
1038
   ETH_MIICOMMAND  32'h0000_0000   32'h0000_0000   MII Command Register
1039
   ETH_MIIADDRESS  32'h0000_0000   32'h0000_0000   MII Address Register
1040
   ETH_MIITX_DATA  32'h0000_0000   32'h0000_0000   MII Transmit Data Register
1041
   ETH_MIIRX_DATA  32'h0000_0000   32'h0000_0000   MII Receive Data Register
1042
   ETH_MIISTATUS   32'h0000_0000   32'h0000_0000   MII Status Register
1043
   ETH_MAC_ADDR0   32'h0000_0000   32'h0000_0000   MAC Individual Address Register 0
1044
   ETH_MAC_ADDR1   32'h0000_0000   32'h0000_0000   MAC Individual Address Register 1
1045
   ETH_HASH_ADDR0  32'h0000_0000   32'h0000_0000   Hash Register 0
1046
   ETH_HASH_ADDR1  32'h0000_0000   32'h0000_0000   Hash Register 1
1047
  */
1048 156 mohor
 
1049 116 mohor
 
1050 169 mohor
if ((start_task <= 2) && (end_task >= 2))
1051
begin
1052
  // TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
1053
  test_name   =
1054
  "TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
1055
  `TIME; $display(
1056
  "  TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
1057 158 mohor
 
1058 169 mohor
  // reset MAC registers
1059
  hard_reset;
1060
  for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
1061
  begin
1062
    for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
1063
    begin
1064
      addr = `ETH_BASE + i_addr;
1065
      // set ranges of R/W bits
1066
      case (addr)
1067
      `ETH_MODER:
1068
      begin
1069
        data = 32'h0000_A800;
1070
        data_max = 32'h0001_FFFF;
1071
      end
1072
      `ETH_INT: // READONLY - tested within INT test
1073
      begin
1074
        data = 32'h0000_0000;
1075
        data_max = 32'h0000_0000;
1076
      end
1077
      `ETH_INT_MASK:
1078
      begin
1079
        data = 32'h0000_0000;
1080
        data_max = 32'h0000_007F;
1081
      end
1082
      `ETH_IPGT:
1083
      begin
1084
        data = 32'h0000_0012;
1085
        data_max = 32'h0000_007F;
1086
      end
1087
      `ETH_IPGR1:
1088
      begin
1089
        data = 32'h0000_000C;
1090
        data_max = 32'h0000_007F;
1091
      end
1092
      `ETH_IPGR2:
1093
      begin
1094
        data = 32'h0000_0012;
1095
        data_max = 32'h0000_007F;
1096
      end
1097
      `ETH_PACKETLEN:
1098
      begin
1099
        data = 32'h0040_0600;
1100
        data_max = 32'hFFFF_FFFF;
1101
      end
1102
      `ETH_COLLCONF:
1103
      begin
1104
        data = 32'h000F_003F;
1105
        data_max = 32'h000F_003F;
1106
      end
1107
      `ETH_TX_BD_NUM:
1108
      begin
1109
        data = 32'h0000_0040;
1110
        data_max = 32'h0000_0080;
1111
      end
1112
      `ETH_CTRLMODER:
1113
      begin
1114
        data = 32'h0000_0000;
1115
        data_max = 32'h0000_0007;
1116
      end
1117
      `ETH_MIIMODER:
1118
      begin
1119
        data = 32'h0000_0064;
1120
        data_max = 32'h0000_03FF;
1121
      end
1122
      `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
1123
      begin
1124
        data = 32'h0000_0000;
1125
        data_max = 32'h0000_0007;
1126
      end
1127
      `ETH_MIIADDRESS:
1128
      begin
1129
        data = 32'h0000_0000;
1130
        data_max = 32'h0000_1F1F;
1131
      end
1132
      `ETH_MIITX_DATA:
1133
      begin
1134
        data = 32'h0000_0000;
1135
        data_max = 32'h0000_FFFF;
1136
      end
1137
      `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
1138
      begin
1139
        data = 32'h0000_0000;
1140
        data_max = 32'h0000_0000;
1141
      end
1142
      `ETH_MIISTATUS: // READONLY - tested within MIIM test
1143
      begin
1144
        data = 32'h0000_0000;
1145
        data_max = 32'h0000_0000;
1146
      end
1147
      `ETH_MAC_ADDR0:
1148
      begin
1149
        data = 32'h0000_0000;
1150
        data_max = 32'hFFFF_FFFF;
1151
      end
1152
      `ETH_MAC_ADDR1:
1153
      begin
1154
        data = 32'h0000_0000;
1155
        data_max = 32'h0000_FFFF;
1156
      end
1157
      `ETH_HASH_ADDR0:
1158
      begin
1159
        data = 32'h0000_0000;
1160
        data_max = 32'hFFFF_FFFF;
1161
      end
1162
      default: // `ETH_HASH_ADDR1:
1163
      begin
1164
        data = 32'h0000_0000;
1165
        data_max = 32'hFFFF_FFFF;
1166
      end
1167
      endcase
1168 116 mohor
 
1169 169 mohor
      wbm_init_waits = {$random} % 3;
1170
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1171
      if (i == 0)
1172
        wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1173
      else if (i == 2)
1174
        wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1175
      else if ((i == 1) || (i == 4))
1176
      begin
1177
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1178
        if (tmp_data !== data)
1179
        begin
1180
          fail = fail + 1;
1181
          test_fail("RESET value of the MAC register is not correct");
1182
          `TIME;
1183
          $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1184
        end
1185
      end
1186
      else // check maximum values
1187
      begin
1188
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1189
        if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
1190
        begin
1191
          if (tmp_data !== data)
1192
          begin
1193
            fail = fail + 1;
1194
            test_fail("Previous value of the TX_BD_NUM register did not remain");
1195
            `TIME;
1196
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1197
          end
1198
          // try maximum (80)
1199
          wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1200
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1201
          if (tmp_data !== data_max)
1202
          begin
1203
            fail = fail + 1;
1204
            test_fail("MAX value of the TX_BD_NUM register is not correct");
1205
            `TIME;
1206
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1207
          end
1208
          // try one less than maximum (80)
1209
          wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1210
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1211
          if (tmp_data !== (data_max - 1))
1212
          begin
1213
            fail = fail + 1;
1214
            test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
1215
            `TIME;
1216
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1217
          end
1218
          // try one more than maximum (80)
1219
          wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1220
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1221
          if (tmp_data !== (data_max - 1)) // previous data should remain in this register
1222
          begin
1223
            fail = fail + 1;
1224
            test_fail("Previous value of the TX_BD_NUM register did not remain");
1225
            `TIME;
1226
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1227
          end
1228
        end
1229
        else
1230
        begin
1231
          if (tmp_data !== data_max)
1232
          begin
1233
            fail = fail + 1;
1234
            test_fail("MAX value of the MAC register is not correct");
1235
            `TIME;
1236
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1237
          end
1238
        end
1239
      end
1240
    end
1241
    // reset MAC registers
1242
    if ((i == 0) || (i == 3))
1243
    begin
1244
      hard_reset;
1245
    end
1246
  end
1247
  if(fail == 0)
1248
    test_ok;
1249
  else
1250
    fail = 0;
1251
end
1252 116 mohor
 
1253
 
1254 169 mohor
if ((start_task <= 3) && (end_task >= 3))
1255
begin
1256
  // TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
1257
  test_name   = "TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
1258
  `TIME;
1259
  $display("  TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
1260 116 mohor
 
1261 169 mohor
  // reset MAC registers
1262
  hard_reset;
1263
  // reset LOGIC with soft reset
1264
  reset_mac;
1265
  reset_mii;
1266
  for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
1267
  begin
1268
    for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1269
    begin
1270
      addr = `ETH_BASE + i_addr;
1271 116 mohor
 
1272 169 mohor
      wbm_init_waits = {$random} % 3;
1273
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1274
      if (i == 0)
1275
      begin
1276
        data = 32'hFFFFFFFF;
1277
        wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1278
      end
1279
      else if (i == 2)
1280
      begin
1281
        data = 32'h00000000;
1282
        wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1283
      end
1284
      else
1285
      begin
1286
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1287
        if (tmp_data !== data)
1288
        begin
1289
          fail = fail + 1;
1290
          test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
1291
          `TIME;
1292
          $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1293
        end
1294
      end
1295
    end
1296
    if ((i == 0) || (i == 2))
1297
    begin
1298
      // reset MAC registers
1299
      hard_reset;
1300
      // reset LOGIC with soft reset
1301
      reset_mac;
1302
      reset_mii;
1303
    end
1304
  end
1305
  if(fail == 0)
1306
    test_ok;
1307
  else
1308
    fail = 0;
1309
end
1310 156 mohor
 
1311
 
1312 169 mohor
end
1313
endtask // test_access_to_mac_reg
1314 156 mohor
 
1315
 
1316 169 mohor
task test_mii;
1317
  input  [31:0]  start_task;
1318
  input  [31:0]  end_task;
1319
  integer        i;
1320
  integer        i1;
1321
  integer        i2;
1322
  integer        i3;
1323
  integer        cnt;
1324
  integer        fail;
1325
  reg     [8:0]  clk_div; // only 8 bits are valid!
1326
  reg     [4:0]  phy_addr;
1327
  reg     [4:0]  reg_addr;
1328
  reg     [15:0] phy_data;
1329
  reg     [15:0] tmp_data;
1330
begin
1331
// MIIM MODULE TEST
1332
test_heading("MIIM MODULE TEST");
1333
$display(" ");
1334
$display("MIIM MODULE TEST");
1335
fail = 0;
1336 156 mohor
 
1337 169 mohor
// reset MIIM LOGIC with soft reset
1338
reset_mii;
1339 116 mohor
 
1340
 
1341 169 mohor
if ((start_task <= 0) && (end_task >= 0))
1342
begin
1343
  // TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
1344
  test_name   = "TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
1345
  `TIME; $display("  TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
1346 116 mohor
 
1347 169 mohor
  wait(Mdc_O); // wait for MII clock to be 1
1348
  for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
1349
  begin
1350
    i1 = 0;
1351
    i2 = 0;
1352
    #Tp mii_set_clk_div(clk_div[7:0]);
1353
    @(posedge Mdc_O);
1354
    #Tp;
1355
    fork
1356
      begin
1357
        @(posedge Mdc_O);
1358
        #Tp;
1359
        disable count_i1;
1360
        disable count_i2;
1361
      end
1362
      begin: count_i1
1363
        forever
1364
        begin
1365
          @(posedge wb_clk);
1366
          i1 = i1 + 1;
1367
          #Tp;
1368
        end
1369
      end
1370
      begin: count_i2
1371
        forever
1372
        begin
1373
          @(negedge wb_clk);
1374
          i2 = i2 + 1;
1375
          #Tp;
1376
        end
1377
      end
1378
    join
1379
    if((clk_div[7:0] == 0) || (clk_div[7:0] == 1) || (clk_div[7:0] == 2) || (clk_div[7:0] == 3))
1380
    begin
1381
      if((i1 == i2) && (i1 == 2))
1382
      begin
1383
      end
1384
      else
1385
      begin
1386
        fail = fail + 1;
1387
        test_fail("Clock divider of MII module did'nt divide frequency corectly (it should divid with 2)");
1388
      end
1389
    end
1390
    else
1391
    begin
1392
      if((i1 == i2) && (i1 == {clk_div[7:1], 1'b0}))
1393
      begin
1394
      end
1395
      else
1396
      begin
1397
        fail = fail + 1;
1398
        test_fail("Clock divider of MII module did'nt divide frequency corectly");
1399
      end
1400
    end
1401
  end
1402
  if(fail == 0)
1403
    test_ok;
1404
  else
1405
    fail = 0;
1406 116 mohor
end
1407
 
1408
 
1409 169 mohor
if ((start_task <= 1) && (end_task >= 1))
1410
begin
1411
  // TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS
1412
  test_name   = "TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
1413
  `TIME; $display("  TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
1414
 
1415
  // set the fastest possible MII
1416
  clk_div = 0;
1417
  mii_set_clk_div(clk_div[7:0]);
1418
  // set address
1419
  reg_addr = 5'h1F;
1420
  phy_addr = 5'h1;
1421
  while(reg_addr >= 5'h4)
1422
  begin
1423
    // read request
1424
    #Tp mii_read_req(phy_addr, reg_addr);
1425
    check_mii_busy; // wait for read to finish
1426
    // read data
1427
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1428
    if (phy_data !== 16'hDEAD)
1429
    begin
1430
      test_fail("Wrong data was read from PHY from 'not used' address space");
1431
      fail = fail + 1;
1432
    end
1433
    if (reg_addr == 5'h4) // go out of for loop
1434
      reg_addr = 5'h3;
1435 116 mohor
    else
1436 169 mohor
      reg_addr = reg_addr - 5'h9;
1437
  end
1438 116 mohor
 
1439 169 mohor
  // set address
1440
  reg_addr = 5'h3;
1441
  // read request
1442
  #Tp mii_read_req(phy_addr, reg_addr);
1443
  check_mii_busy; // wait for read to finish
1444
  // read data
1445
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1446
  if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})
1447
  begin
1448
    test_fail("Wrong data was read from PHY from ID register 2");
1449
    fail = fail + 1;
1450 116 mohor
  end
1451 169 mohor
  if(fail == 0)
1452
    test_ok;
1453
  else
1454
    fail = 0;
1455
end
1456 116 mohor
 
1457
 
1458 169 mohor
if ((start_task <= 2) && (end_task >= 2))
1459
begin
1460
  // TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
1461
  test_name   = "TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
1462
  `TIME; $display("  TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
1463
 
1464
  // negate data and try to write into unwritable register
1465
  tmp_data = ~phy_data;
1466
  // write request
1467
  #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1468
  check_mii_busy; // wait for write to finish
1469
  // read request
1470
  #Tp mii_read_req(phy_addr, reg_addr);
1471
  check_mii_busy; // wait for read to finish
1472
  // read data
1473
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1474
  if (tmp_data !== phy_data)
1475
  begin
1476
    test_fail("Data was written into unwritable PHY register - ID register 2");
1477
    fail = fail + 1;
1478
  end
1479
 
1480
  // set address
1481
  reg_addr = 5'h0; // control register
1482
  // read request
1483
  #Tp mii_read_req(phy_addr, reg_addr);
1484
  check_mii_busy; // wait for read to finish
1485
  // read data
1486
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1487
  // write request
1488
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1489
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1490
  check_mii_busy; // wait for write to finish
1491
  // read request
1492
  #Tp mii_read_req(phy_addr, reg_addr);
1493
  check_mii_busy; // wait for read to finish
1494
  // read data
1495
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1496
  if (phy_data !== 16'h7DFF)
1497
  begin
1498
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1499
    fail = fail + 1;
1500
  end
1501
  // write request
1502
  #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1503
  check_mii_busy; // wait for write to finish
1504
  // read request
1505
  #Tp mii_read_req(phy_addr, reg_addr);
1506
  check_mii_busy; // wait for read to finish
1507
  // read data
1508
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1509
  if (phy_data !== tmp_data)
1510
  begin
1511
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1512
    fail = fail + 1;
1513
  end
1514
  if(fail == 0)
1515
    test_ok;
1516
  else
1517
    fail = 0;
1518
end
1519
 
1520
 
1521
if ((start_task <= 3) && (end_task >= 3))
1522
begin
1523
  // TEST RESET PHY THROUGH MII MANAGEMENT MODULE
1524
  test_name   = "TEST RESET PHY THROUGH MII MANAGEMENT MODULE";
1525
  `TIME; $display("  TEST RESET PHY THROUGH MII MANAGEMENT MODULE");
1526
 
1527
  // set address
1528
  reg_addr = 5'h0; // control register
1529
  // write request
1530
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1531
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1532
  check_mii_busy; // wait for write to finish
1533
  // read request
1534
  #Tp mii_read_req(phy_addr, reg_addr);
1535
  check_mii_busy; // wait for read to finish
1536
  // read data
1537
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1538
  if (phy_data !== tmp_data)
1539
  begin
1540
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1541
    fail = fail + 1;
1542
  end
1543
  // set reset bit - selfclearing bit in PHY
1544
  phy_data = phy_data | 16'h8000;
1545
  // write request
1546
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1547
  check_mii_busy; // wait for write to finish
1548
  // read request
1549
  #Tp mii_read_req(phy_addr, reg_addr);
1550
  check_mii_busy; // wait for read to finish
1551
  // read data
1552
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1553
  // check self clearing of reset bit
1554
  if (tmp_data[15] !== 1'b0)
1555
  begin
1556
    test_fail("Reset bit should be self cleared - control register");
1557
    fail = fail + 1;
1558
  end
1559
  // check reset value of control register
1560
  if (tmp_data !== {2'h0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 3'h0, `LED_CFG3, 8'h0})
1561
  begin
1562
    test_fail("PHY was not reset correctly AND/OR reset bit not self cleared");
1563
    fail = fail + 1;
1564
  end
1565
  if(fail == 0)
1566
    test_ok;
1567
  else
1568
    fail = 0;
1569
end
1570
 
1571
 
1572
if ((start_task <= 4) && (end_task >= 4))
1573
begin
1574
  // TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
1575
  test_name   = "TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1576
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1577
 
1578
  // set PHY to test mode
1579
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1580
  for (i = 0; i <= 1; i = i + 1)
1581
  begin
1582
    #Tp eth_phy.preamble_suppresed(i);
1583
    #Tp eth_phy.clear_test_regs;
1584
    // MII mode register
1585
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1586
              wbm_subseq_waits);
1587
    // walk one across phy address
1588
    for (phy_addr = 5'h1; phy_addr > 5'h0; phy_addr = phy_addr << 1)
1589
    begin
1590
      reg_addr = $random;
1591
      tmp_data = $random;
1592
      // write request
1593
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1594
      check_mii_busy; // wait for write to finish
1595
      // read request
1596
      #Tp mii_read_req(phy_addr, reg_addr);
1597
      check_mii_busy; // wait for read to finish
1598
      // read data
1599
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1600
      #Tp;
1601
      if (phy_data !== tmp_data)
1602
      begin
1603
        if (i)
1604
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1605
        else
1606
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1607
        fail = fail + 1;
1608
      end
1609
      @(posedge wb_clk);
1610
      #Tp;
1611
    end
1612
  end
1613
  // set PHY to normal mode
1614
  #Tp eth_phy.test_regs(0);
1615
  #Tp eth_phy.preamble_suppresed(0);
1616
  // MII mode register
1617
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1618
  if(fail == 0)
1619
    test_ok;
1620
  else
1621
    fail = 0;
1622
end
1623
 
1624
 
1625
if ((start_task <= 5) && (end_task >= 5))
1626
begin
1627
  // TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
1628
  test_name   = "TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1629
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1630
 
1631
  // set PHY to test mode
1632
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1633
  for (i = 0; i <= 1; i = i + 1)
1634
  begin
1635
    #Tp eth_phy.preamble_suppresed(i);
1636
    #Tp eth_phy.clear_test_regs;
1637
    // MII mode register
1638
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1639
              wbm_subseq_waits);
1640
    // walk one across reg address
1641
    for (reg_addr = 5'h1; reg_addr > 5'h0; reg_addr = reg_addr << 1)
1642
    begin
1643
      phy_addr = $random;
1644
      tmp_data = $random;
1645
      // write request
1646
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1647
      check_mii_busy; // wait for write to finish
1648
      // read request
1649
      #Tp mii_read_req(phy_addr, reg_addr);
1650
      check_mii_busy; // wait for read to finish
1651
      // read data
1652
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1653
      #Tp;
1654
      if (phy_data !== tmp_data)
1655
      begin
1656
        if (i)
1657
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1658
        else
1659
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1660
        fail = fail + 1;
1661
      end
1662
      @(posedge wb_clk);
1663
      #Tp;
1664
    end
1665
  end
1666
  // set PHY to normal mode
1667
  #Tp eth_phy.test_regs(0);
1668
  #Tp eth_phy.preamble_suppresed(0);
1669
  // MII mode register
1670
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1671
  if(fail == 0)
1672
    test_ok;
1673
  else
1674
    fail = 0;
1675
end
1676
 
1677
 
1678
if ((start_task <= 6) && (end_task >= 6))
1679
begin
1680
  // TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
1681
  test_name   = "TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
1682
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
1683
 
1684
  // set PHY to test mode
1685
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1686
  for (i = 0; i <= 1; i = i + 1)
1687
  begin
1688
    #Tp eth_phy.preamble_suppresed(i);
1689
    #Tp eth_phy.clear_test_regs;
1690
    // MII mode register
1691
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1692
              wbm_subseq_waits);
1693
    // walk one across data
1694
    for (tmp_data = 16'h1; tmp_data > 16'h0; tmp_data = tmp_data << 1)
1695
    begin
1696
      phy_addr = $random;
1697
      reg_addr = $random;
1698
      // write request
1699
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1700
      check_mii_busy; // wait for write to finish
1701
      // read request
1702
      #Tp mii_read_req(phy_addr, reg_addr);
1703
      check_mii_busy; // wait for read to finish
1704
      // read data
1705
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1706
      #Tp;
1707
      if (phy_data !== tmp_data)
1708
      begin
1709
        if (i)
1710
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1711
        else
1712
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1713
        fail = fail + 1;
1714
      end
1715
      @(posedge wb_clk);
1716
      #Tp;
1717
    end
1718
  end
1719
  // set PHY to normal mode
1720
  #Tp eth_phy.test_regs(0);
1721
  #Tp eth_phy.preamble_suppresed(0);
1722
  // MII mode register
1723
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1724
  if(fail == 0)
1725
    test_ok;
1726
  else
1727
    fail = 0;
1728
end
1729
 
1730
 
1731
if ((start_task <= 7) && (end_task >= 7))
1732
begin
1733
  // TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
1734
  test_name   = "TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
1735
  `TIME; $display("  TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
1736
 
1737
  phy_addr = 5'h2; // wrong PHY address
1738
  // read request
1739
  #Tp mii_read_req(phy_addr, reg_addr);
1740
  check_mii_busy; // wait for read to finish
1741
  // read data
1742
  $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
1743
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1744
  if (tmp_data !== 16'hzzzz)
1745
  begin
1746
    test_fail("Data was read from PHY register with wrong PHY address - control register");
1747
    fail = fail + 1;
1748
  end
1749
  if(fail == 0)
1750
    test_ok;
1751
  else
1752
    fail = 0;
1753
end
1754
 
1755
 
1756
if ((start_task <= 8) && (end_task >= 8))
1757
begin
1758
  // TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
1759
  test_name   = "TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
1760
  `TIME; $display("  TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
1761
 
1762
  // set address
1763
  reg_addr = 5'h0; // control register
1764
  phy_addr = 5'h2; // wrong PHY address
1765
  // write request
1766
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1767
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1768
  check_mii_busy; // wait for write to finish
1769
 
1770
  phy_addr = 5'h1; // correct PHY address
1771
  // read request
1772
  #Tp mii_read_req(phy_addr, reg_addr);
1773
  check_mii_busy; // wait for read to finish
1774
  // read data
1775
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1776
  if (phy_data === tmp_data)
1777
  begin
1778
    test_fail("Data was written into PHY register with wrong PHY address - control register");
1779
    fail = fail + 1;
1780
  end
1781
  if(fail == 0)
1782
    test_ok;
1783
  else
1784
    fail = 0;
1785
end
1786
 
1787
 
1788
if ((start_task <= 9) && (end_task >= 9))
1789
begin
1790
  // TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
1791
  test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
1792
  `TIME;
1793
  $display("  TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
1794
 
1795
  for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1796
  begin
1797
    #Tp eth_phy.preamble_suppresed(i2);
1798
    // MII mode register
1799
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1800
             wbm_subseq_waits);
1801
    i = 0;
1802
    cnt = 0;
1803
    while (i < 80) // delay for sliding of writing a STOP SCAN command
1804
    begin
1805
      for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after read will be finished
1806
      begin
1807
        // set address
1808
        reg_addr = 5'h0; // control register
1809
        phy_addr = 5'h1; // correct PHY address
1810
        cnt = 0;
1811
        // read request
1812
        #Tp mii_read_req(phy_addr, reg_addr);
1813
        fork
1814
          begin
1815
            repeat(i) @(posedge Mdc_O);
1816
            // write command 0x0 into MII command register
1817
            // MII command written while read in progress
1818
            wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1819
            @(posedge wb_clk);
1820
            #Tp check_mii_busy; // wait for read to finish
1821
          end
1822
          begin
1823
            // wait for serial bus to become active
1824
            wait(Mdio_IO !== 1'bz);
1825
            // count transfer length
1826
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
1827
            begin
1828
              @(posedge Mdc_O);
1829
              #Tp cnt = cnt + 1;
1830
            end
1831
          end
1832
        join
1833
        // check transfer length
1834
        if (i2) // without preamble
1835
        begin
1836
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
1837
          begin
1838
            test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
1839
            fail = fail + 1;
1840
          end
1841
        end
1842
        else // with preamble
1843
        begin
1844
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
1845
          begin
1846
            test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
1847
            fail = fail + 1;
1848
          end
1849
        end
1850
        // check the BUSY signal to see if the bus is still IDLE
1851
        for (i1 = 0; i1 < 8; i1 = i1 + 1)
1852
          check_mii_busy; // wait for bus to become idle
1853 116 mohor
 
1854 169 mohor
        // try normal write or read after read was finished
1855
        #Tp phy_data = {8'h7D, (i[7:0] + 1)};
1856
        #Tp cnt = 0;
1857
        if (i3 == 0) // write after read
1858
        begin
1859
          // write request
1860
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1861
          // wait for serial bus to become active
1862
          wait(Mdio_IO !== 1'bz);
1863
          // count transfer length
1864
          while(Mdio_IO !== 1'bz)
1865
          begin
1866
            @(posedge Mdc_O);
1867
            #Tp cnt = cnt + 1;
1868
          end
1869
          @(posedge Mdc_O);
1870
          // read request
1871
          #Tp mii_read_req(phy_addr, reg_addr);
1872
          check_mii_busy; // wait for read to finish
1873
          // read and check data
1874
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1875
          if (phy_data !== tmp_data)
1876
          begin
1877
            test_fail("Data was not correctly written into OR read from PHY register - control register");
1878
            fail = fail + 1;
1879
          end
1880
        end
1881
        else // read after read
1882
        begin
1883
          // read request
1884
          #Tp mii_read_req(phy_addr, reg_addr);
1885
          // wait for serial bus to become active
1886
          wait(Mdio_IO !== 1'bz);
1887
          // count transfer length
1888
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
1889
          begin
1890
            @(posedge Mdc_O);
1891
            #Tp cnt = cnt + 1;
1892
          end
1893
          @(posedge Mdc_O);
1894
          check_mii_busy; // wait for read to finish
1895
          // read and check data
1896
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1897
          if (phy_data !== tmp_data)
1898
          begin
1899
            test_fail("Data was not correctly written into OR read from PHY register - control register");
1900
            fail = fail + 1;
1901
          end
1902
        end
1903
        // check if transfer was a proper length
1904
        if (i2) // without preamble
1905
        begin
1906
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
1907
          begin
1908
            test_fail("New request did not proceed correctly, after read request");
1909
            fail = fail + 1;
1910
          end
1911
        end
1912
        else // with preamble
1913
        begin
1914
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
1915
          begin
1916
            test_fail("New request did not proceed correctly, after read request");
1917
            fail = fail + 1;
1918
          end
1919
        end
1920
      end
1921
      #Tp;
1922
      // set delay of writing the command
1923
      if (i2) // without preamble
1924
      begin
1925
        case(i)
1926
          0, 1:               i = i + 1;
1927
          18, 19, 20, 21, 22,
1928
          23, 24, 25, 26, 27,
1929
          28, 29, 30, 31, 32,
1930
          33, 34, 35:         i = i + 1;
1931
          36:                 i = 80;
1932
          default:            i = 18;
1933
        endcase
1934
      end
1935
      else // with preamble
1936
      begin
1937
        case(i)
1938
          0, 1:               i = i + 1;
1939
          50, 51, 52, 53, 54,
1940
          55, 56, 57, 58, 59,
1941
          60, 61, 62, 63, 64,
1942
          65, 66, 67:         i = i + 1;
1943
          68:                 i = 80;
1944
          default:            i = 50;
1945
        endcase
1946
      end
1947
      @(posedge wb_clk);
1948
    end
1949
  end
1950
  // set PHY to normal mode
1951
  #Tp eth_phy.preamble_suppresed(0);
1952
  // MII mode register
1953
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1954
  if(fail == 0)
1955
    test_ok;
1956
  else
1957
    fail = 0;
1958
end
1959
 
1960
 
1961
if ((start_task <= 10) && (end_task >= 10))
1962
begin
1963
  // TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
1964
  test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
1965
  `TIME;
1966
  $display("  TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
1967
 
1968
  for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1969
  begin
1970
    #Tp eth_phy.preamble_suppresed(i2);
1971
    // MII mode register
1972
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1973
              wbm_subseq_waits);
1974
    i = 0;
1975
    cnt = 0;
1976
    while (i < 80) // delay for sliding of writing a STOP SCAN command
1977
    begin
1978
      for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after write will be finished
1979
      begin
1980
        // set address
1981
        reg_addr = 5'h0; // control register
1982
        phy_addr = 5'h1; // correct PHY address
1983
        cnt = 0;
1984
        // write request
1985
        phy_data = {8'h75, (i[7:0] + 1)};
1986
        #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1987
        fork
1988
          begin
1989
            repeat(i) @(posedge Mdc_O);
1990
            // write command 0x0 into MII command register
1991
            // MII command written while read in progress
1992
            wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1993
            @(posedge wb_clk);
1994
            #Tp check_mii_busy; // wait for write to finish
1995
          end
1996
          begin
1997
            // wait for serial bus to become active
1998
            wait(Mdio_IO !== 1'bz);
1999
            // count transfer length
2000
            while(Mdio_IO !== 1'bz)
2001
            begin
2002
              @(posedge Mdc_O);
2003
              #Tp cnt = cnt + 1;
2004
            end
2005
          end
2006
        join
2007
        // check transfer length
2008
        if (i2) // without preamble
2009
        begin
2010
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2011
          begin
2012
            test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2013
            fail = fail + 1;
2014
          end
2015
        end
2016
        else // with preamble
2017
        begin
2018
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2019
          begin
2020
            test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2021
            fail = fail + 1;
2022
          end
2023
        end
2024
        // check the BUSY signal to see if the bus is still IDLE
2025
        for (i1 = 0; i1 < 8; i1 = i1 + 1)
2026
          check_mii_busy; // wait for bus to become idle
2027 116 mohor
 
2028 169 mohor
        // try normal write or read after write was finished
2029
        #Tp cnt = 0;
2030
        if (i3 == 0) // write after write
2031
        begin
2032
          phy_data = {8'h7A, (i[7:0] + 1)};
2033
          // write request
2034
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2035
          // wait for serial bus to become active
2036
          wait(Mdio_IO !== 1'bz);
2037
          // count transfer length
2038
          while(Mdio_IO !== 1'bz)
2039
          begin
2040
            @(posedge Mdc_O);
2041
            #Tp cnt = cnt + 1;
2042
          end
2043
          @(posedge Mdc_O);
2044
          // read request
2045
          #Tp mii_read_req(phy_addr, reg_addr);
2046
          check_mii_busy; // wait for read to finish
2047
          // read and check data
2048
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2049
          if (phy_data !== tmp_data)
2050
          begin
2051
            test_fail("Data was not correctly written into OR read from PHY register - control register");
2052
            fail = fail + 1;
2053
          end
2054
        end
2055
        else // read after write
2056
        begin
2057
          // read request
2058
          #Tp mii_read_req(phy_addr, reg_addr);
2059
          // wait for serial bus to become active
2060
          wait(Mdio_IO !== 1'bz);
2061
          // count transfer length
2062
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2063
          begin
2064
            @(posedge Mdc_O);
2065
            #Tp cnt = cnt + 1;
2066
          end
2067
          @(posedge Mdc_O);
2068
          check_mii_busy; // wait for read to finish
2069
          // read and check data
2070
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2071
          if (phy_data !== tmp_data)
2072
          begin
2073
            test_fail("Data was not correctly written into OR read from PHY register - control register");
2074
            fail = fail + 1;
2075
          end
2076
        end
2077
        // check if transfer was a proper length
2078
        if (i2) // without preamble
2079
        begin
2080
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2081
          begin
2082
            test_fail("New request did not proceed correctly, after write request");
2083
            fail = fail + 1;
2084
          end
2085
        end
2086
        else // with preamble
2087
        begin
2088
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2089
          begin
2090
            test_fail("New request did not proceed correctly, after write request");
2091
            fail = fail + 1;
2092
          end
2093
        end
2094
      end
2095
      #Tp;
2096
      // set delay of writing the command
2097
      if (i2) // without preamble
2098
      begin
2099
        case(i)
2100
          0, 1:               i = i + 1;
2101
          18, 19, 20, 21, 22,
2102
          23, 24, 25, 26, 27,
2103
          28, 29, 30, 31, 32,
2104
          33, 34, 35:         i = i + 1;
2105
          36:                 i = 80;
2106
          default:            i = 18;
2107
        endcase
2108
      end
2109
      else // with preamble
2110
      begin
2111
        case(i)
2112
          0, 1:               i = i + 1;
2113
          50, 51, 52, 53, 54,
2114
          55, 56, 57, 58, 59,
2115
          60, 61, 62, 63, 64,
2116
          65, 66, 67:         i = i + 1;
2117
          68:                 i = 80;
2118
          default:            i = 50;
2119
        endcase
2120
      end
2121
      @(posedge wb_clk);
2122
    end
2123
  end
2124
  // set PHY to normal mode
2125
  #Tp eth_phy.preamble_suppresed(0);
2126
  // MII mode register
2127
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2128
  if(fail == 0)
2129
    test_ok;
2130
  else
2131
    fail = 0;
2132
end
2133
 
2134
 
2135
if ((start_task <= 11) && (end_task >= 11))
2136
begin
2137
  // TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
2138
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
2139
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
2140
 
2141
  reset_mii; // reset MII
2142
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2143
  #Tp eth_phy.link_up_down(1);
2144
  // set the MII
2145
  clk_div = 64;
2146
  mii_set_clk_div(clk_div[7:0]);
2147
  // set address
2148
  reg_addr = 5'h1; // status register
2149
  phy_addr = 5'h1; // correct PHY address
2150
 
2151
  for (i = 0; i <= 1; i = i + 1)
2152
  begin
2153
    #Tp eth_phy.preamble_suppresed(i);
2154
    // MII mode register
2155
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2156
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2157
    @(posedge Mdc_O);
2158
    // write request
2159
    #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);
2160
    // read data from MII status register - Busy and Nvalid bits
2161
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2162
 
2163
    // check MII IO signal and Busy and Nvalid bits
2164
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2165
    begin
2166
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2167
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2168
      begin
2169
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2170
        fail = fail + 1;
2171
      end
2172
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2173
      begin
2174
        test_fail("Nvalid signal was set during write");
2175
        fail = fail + 1;
2176
      end
2177
    end
2178
    else // Busy bit should already be set to '1', due to reads from MII status register
2179
    begin
2180
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2181
      begin
2182
        test_fail("Busy signal should be set after write, due to reads from MII status register");
2183
        fail = fail + 1;
2184
      end
2185
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2186
      begin
2187
        test_fail("Nvalid signal was set during write");
2188
        fail = fail + 1;
2189
      end
2190
    end
2191
 
2192
    // wait for serial bus to become active
2193
    wait(Mdio_IO !== 1'bz);
2194
    // count transfer bits
2195
    if (i)
2196
    begin
2197
      repeat(32) @(posedge Mdc_O);
2198
    end
2199 116 mohor
    else
2200 169 mohor
    begin
2201
      repeat(64) @(posedge Mdc_O);
2202
    end
2203
    // read data from MII status register - Busy and Nvalid bits
2204
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2205 116 mohor
 
2206 169 mohor
    // check MII IO signal and Busy and Nvalid bits
2207
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2208
    begin
2209
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2210
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2211
      begin
2212
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2213
        fail = fail + 1;
2214
      end
2215
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2216
      begin
2217
        test_fail("Nvalid signal was set during write");
2218
        fail = fail + 1;
2219
      end
2220
    end
2221
    else // Busy bit should still be set to '1'
2222
    begin
2223
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2224
      begin
2225
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2226
        fail = fail + 1;
2227
      end
2228
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2229
      begin
2230
        test_fail("Nvalid signal was set during write");
2231
        fail = fail + 1;
2232
      end
2233
    end
2234
 
2235
    // wait for next negative clock edge
2236
    @(negedge Mdc_O);
2237
    // read data from MII status register - Busy and Nvalid bits
2238
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2239
 
2240
    // check MII IO signal and Busy and Nvalid bits
2241
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2242
    begin
2243
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2244
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2245
      begin
2246
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2247
        fail = fail + 1;
2248
      end
2249
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2250
      begin
2251
        test_fail("Nvalid signal was set during write");
2252
        fail = fail + 1;
2253
      end
2254
    end
2255
    else // Busy bit should still be set to '1'
2256
    begin
2257
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2258
      begin
2259
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2260
        fail = fail + 1;
2261
      end
2262
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2263
      begin
2264
        test_fail("Nvalid signal was set during write");
2265
        fail = fail + 1;
2266
      end
2267
    end
2268
 
2269
    // wait for Busy to become inactive
2270
    i1 = 0;
2271
    while (i1 <= 2)
2272
    begin
2273
      // wait for next positive clock edge
2274
      @(posedge Mdc_O);
2275
      // read data from MII status register - Busy and Nvalid bits
2276
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2277
 
2278
      // check MII IO signal and Busy and Nvalid bits
2279
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2280
      begin
2281
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2282
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2283
        begin
2284
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2285
          fail = fail + 1;
2286
        end
2287
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2288
        begin
2289
          test_fail("Nvalid signal was set during write");
2290
          fail = fail + 1;
2291
        end
2292
      end
2293
      else // wait for Busy bit to be set to '0'
2294
      begin
2295
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2296
        begin
2297
          i1 = 3; // end of Busy checking
2298
        end
2299
        else
2300
        begin
2301
          if (i1 == 2)
2302
          begin
2303
            test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2304
            fail = fail + 1;
2305
          end
2306
          #Tp i1 = i1 + 1;
2307
        end
2308
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2309
        begin
2310
          test_fail("Nvalid signal was set after write");
2311
          fail = fail + 1;
2312
        end
2313
      end
2314
    end
2315 116 mohor
  end
2316 169 mohor
  // set PHY to normal mode
2317
  #Tp eth_phy.preamble_suppresed(0);
2318
  // MII mode register
2319
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2320
  if(fail == 0)
2321
    test_ok;
2322
  else
2323
    fail = 0;
2324
end
2325 116 mohor
 
2326
 
2327 169 mohor
if ((start_task <= 12) && (end_task >= 12))
2328
begin
2329
  // TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
2330
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
2331
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
2332 116 mohor
 
2333 169 mohor
  reset_mii; // reset MII
2334
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2335
  #Tp eth_phy.link_up_down(1);
2336
  // set the MII
2337
  clk_div = 64;
2338
  mii_set_clk_div(clk_div[7:0]);
2339
  // set address
2340
  reg_addr = 5'h1; // status register
2341
  phy_addr = 5'h1; // correct PHY address
2342
 
2343
  for (i = 0; i <= 1; i = i + 1)
2344
  begin
2345
    #Tp eth_phy.preamble_suppresed(i);
2346
    // MII mode register
2347
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2348
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2349
    @(posedge Mdc_O);
2350
    // read request
2351
    #Tp mii_read_req(phy_addr, reg_addr);
2352
    // read data from MII status register - Busy and Nvalid bits
2353
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2354
 
2355
    // check MII IO signal and Busy and Nvalid bits
2356
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2357
    begin
2358
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2359
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2360
      begin
2361
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2362
        fail = fail + 1;
2363
      end
2364
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2365
      begin
2366
        test_fail("Nvalid signal was set during read");
2367
        fail = fail + 1;
2368
      end
2369
    end
2370
    else // Busy bit should already be set to '1', due to reads from MII status register
2371
    begin
2372
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2373
      begin
2374
        test_fail("Busy signal should be set after read, due to reads from MII status register");
2375
        fail = fail + 1;
2376
      end
2377
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2378
      begin
2379
        test_fail("Nvalid signal was set during read");
2380
        fail = fail + 1;
2381
      end
2382
    end
2383
 
2384
    // wait for serial bus to become active
2385
    wait(Mdio_IO !== 1'bz);
2386
    // count transfer bits
2387
    if (i)
2388
    begin
2389
      repeat(31) @(posedge Mdc_O);
2390
    end
2391
    else
2392
    begin
2393
      repeat(63) @(posedge Mdc_O);
2394
    end
2395
    // wait for next negative clock edge
2396
    @(negedge Mdc_O);
2397
    // read data from MII status register - Busy and Nvalid bits
2398
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2399
 
2400
    // check MII IO signal and Busy and Nvalid bits
2401
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2402
    begin
2403
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2404
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2405
      begin
2406
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2407
        fail = fail + 1;
2408
      end
2409
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2410
      begin
2411
        test_fail("Nvalid signal was set during read");
2412
        fail = fail + 1;
2413
      end
2414
    end
2415
    else // Busy bit should still be set to '1'
2416
    begin
2417
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2418
      begin
2419
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2420
        fail = fail + 1;
2421
      end
2422
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2423
      begin
2424
        test_fail("Nvalid signal was set during read");
2425
        fail = fail + 1;
2426
      end
2427
    end
2428
 
2429
    // wait for next positive clock edge
2430
    @(posedge Mdc_O);
2431
    // read data from MII status register - Busy and Nvalid bits
2432
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2433
 
2434
    // check MII IO signal and Busy and Nvalid bits
2435
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2436
    begin
2437
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2438
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2439
      begin
2440
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2441
        fail = fail + 1;
2442
      end
2443
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2444
      begin
2445
        test_fail("Nvalid signal was set during read");
2446
        fail = fail + 1;
2447
      end
2448
    end
2449
    else // Busy bit should still be set to '1'
2450
    begin
2451
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2452
      begin
2453
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2454
        fail = fail + 1;
2455
      end
2456
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2457
      begin
2458
        test_fail("Nvalid signal was set during read");
2459
        fail = fail + 1;
2460
      end
2461
    end
2462
 
2463
    // wait for Busy to become inactive
2464
    i1 = 0;
2465
    while (i1 <= 2)
2466
    begin
2467
      // wait for next positive clock edge
2468
      @(posedge Mdc_O);
2469
      // read data from MII status register - Busy and Nvalid bits
2470
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2471
 
2472
      // check MII IO signal and Busy and Nvalid bits
2473
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2474
      begin
2475
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2476
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2477
        begin
2478
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2479
          fail = fail + 1;
2480
        end
2481
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2482
        begin
2483
          test_fail("Nvalid signal was set during read");
2484
          fail = fail + 1;
2485
        end
2486
      end
2487
      else // wait for Busy bit to be set to '0'
2488
      begin
2489
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2490
        begin
2491
          i1 = 3; // end of Busy checking
2492
        end
2493
        else
2494
        begin
2495
          if (i1 == 2)
2496
          begin
2497
            test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2498
            fail = fail + 1;
2499
          end
2500
          #Tp i1 = i1 + 1;
2501
        end
2502
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2503
        begin
2504
          test_fail("Nvalid signal was set after read");
2505
          fail = fail + 1;
2506
        end
2507
      end
2508
    end
2509
  end
2510
  // set PHY to normal mode
2511
  #Tp eth_phy.preamble_suppresed(0);
2512
  // MII mode register
2513
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2514
  if(fail == 0)
2515
    test_ok;
2516
  else
2517
    fail = 0;
2518
end
2519
 
2520
 
2521
if ((start_task <= 13) && (end_task >= 13))
2522
begin
2523
  // TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
2524
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
2525
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
2526
 
2527
  reset_mii; // reset MII
2528
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2529
  #Tp eth_phy.link_up_down(1);
2530
  // set the MII
2531
  clk_div = 64;
2532
  mii_set_clk_div(clk_div[7:0]);
2533
  // set address
2534
  reg_addr = 5'h1; // status register
2535
  phy_addr = 5'h1; // correct PHY address
2536
 
2537
  for (i = 0; i <= 1; i = i + 1)
2538
  begin
2539
    #Tp eth_phy.preamble_suppresed(i);
2540
    // MII mode register
2541
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2542
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2543
    @(posedge Mdc_O);
2544
    // scan request
2545
    #Tp mii_scan_req(phy_addr, reg_addr);
2546
    // read data from MII status register - Busy and Nvalid bits
2547
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2548
 
2549
    // check MII IO signal and Busy and Nvalid bits
2550
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2551
    begin
2552
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2553
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2554
      begin
2555
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2556
        fail = fail + 1;
2557
      end
2558
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2559
      begin
2560
        test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2561
        fail = fail + 1;
2562
      end
2563
    end
2564
    else // Busy bit should already be set to '1', due to reads from MII status register
2565
    begin
2566
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2567
      begin
2568
        test_fail("Busy signal should be set after scan, due to reads from MII status register");
2569
        fail = fail + 1;
2570
      end
2571
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2572
      begin
2573
        test_fail("Nvalid signal should be set after scan, due to reads from MII status register");
2574
        fail = fail + 1;
2575
      end
2576
    end
2577
 
2578
    // wait for serial bus to become active
2579
    wait(Mdio_IO !== 1'bz);
2580
    // count transfer bits
2581
    if (i)
2582
    begin
2583
      repeat(21) @(posedge Mdc_O);
2584
    end
2585
    else
2586
    begin
2587
      repeat(53) @(posedge Mdc_O);
2588
    end
2589
    // stop scan
2590
    #Tp mii_scan_finish; // finish scan operation
2591
 
2592
    // wait for next positive clock edge
2593
    repeat(10) @(posedge Mdc_O);
2594
    // read data from MII status register - Busy and Nvalid bits
2595
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2596
 
2597
    // check MII IO signal and Busy and Nvalid bits
2598
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2599
    begin
2600
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2601
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2602
      begin
2603
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2604
        fail = fail + 1;
2605
      end
2606
      // Nvalid signal can be cleared here - it is still Testbench error
2607
    end
2608
    else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2609
    begin
2610
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2611
      begin
2612
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2613
        fail = fail + 1;
2614
      end
2615
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2616
      begin
2617
        test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2618
        fail = fail + 1;
2619
      end
2620
    end
2621
 
2622
    // wait for next negative clock edge
2623
    @(negedge Mdc_O);
2624
    // read data from MII status register - Busy and Nvalid bits
2625
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2626
 
2627
    // check MII IO signal and Busy and Nvalid bits
2628
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2629
    begin
2630
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2631
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2632
      begin
2633
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2634
        fail = fail + 1;
2635
      end
2636
      // Nvalid signal can be cleared here - it is still Testbench error
2637
    end
2638
    else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2639
    begin
2640
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2641
      begin
2642
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2643
        fail = fail + 1;
2644
      end
2645
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2646
      begin
2647
        test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2648
        fail = fail + 1;
2649
      end
2650
    end
2651
 
2652
    // wait for next negative clock edge
2653
    @(posedge Mdc_O);
2654
    // read data from MII status register - Busy and Nvalid bits
2655
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2656
 
2657
    // check MII IO signal and Busy and Nvalid bits
2658
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2659
    begin
2660
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2661
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2662
      begin
2663
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2664
        fail = fail + 1;
2665
      end
2666
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2667
      begin
2668
        test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2669
        fail = fail + 1;
2670
      end
2671
    end
2672
    else // Busy bit should still be set to '1', Nvalid bit can be set to '0'
2673
    begin
2674
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2675
      begin
2676
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2677
        fail = fail + 1;
2678
      end
2679
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2680
      begin
2681
        i2 = 1; // check finished
2682
      end
2683
      else
2684
      begin
2685
        i2 = 0; // check must continue
2686
      end
2687
    end
2688
 
2689
    // wait for Busy to become inactive
2690
    i1 = 0;
2691
    while ((i1 <= 2) || (i2 == 0))
2692
    begin
2693
      // wait for next positive clock edge
2694
      @(posedge Mdc_O);
2695
      // read data from MII status register - Busy and Nvalid bits
2696
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2697
 
2698
      // check MII IO signal and Busy and Nvalid bits
2699
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2700
      begin
2701
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2702
        if (i1 <= 2)
2703
        begin
2704
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2705
          begin
2706
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2707
            fail = fail + 1;
2708
          end
2709
        end
2710
        if (i2 == 0)
2711
        begin
2712
          if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2713
          begin
2714
            test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2715
            fail = fail + 1;
2716
          end
2717
        end
2718
      end
2719
      else // wait for Busy bit to be set to '0'
2720
      begin
2721
        if (i1 <= 2)
2722
        begin
2723
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2724
          begin
2725
            i1 = 3; // end of Busy checking
2726
          end
2727
          else
2728
          begin
2729
            if (i1 == 2)
2730
            begin
2731
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2732
              fail = fail + 1;
2733
            end
2734
            #Tp i1 = i1 + 1;
2735
          end
2736
        end
2737
        if (i2 == 0)
2738
        begin
2739
          if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2740
          begin
2741
            i2 = 1;
2742
          end
2743
          else
2744
          begin
2745
            test_fail("Nvalid signal should be cleared after MII IO signal become HIGH Z");
2746
            fail = fail + 1;
2747
          end
2748
        end
2749
      end
2750
    end
2751
  end
2752
  // set PHY to normal mode
2753
  #Tp eth_phy.preamble_suppresed(0);
2754
  // MII mode register
2755
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2756
  if(fail == 0)
2757
    test_ok;
2758
  else
2759
    fail = 0;
2760
end
2761
 
2762
 
2763
if ((start_task <= 14) && (end_task >= 14))
2764
begin
2765
  // TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
2766
  test_name   = "TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
2767
  `TIME; $display("  TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
2768
 
2769
  reset_mii; // reset MII
2770
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2771
  #Tp eth_phy.link_up_down(1);
2772
  // set MII speed
2773
  clk_div = 6;
2774
  mii_set_clk_div(clk_div[7:0]);
2775
  // set address
2776
  reg_addr = 5'h1; // status register
2777
  phy_addr = 5'h1; // correct PHY address
2778
 
2779
  // read request
2780
  #Tp mii_read_req(phy_addr, reg_addr);
2781
  check_mii_busy; // wait for read to finish
2782
  // read data from PHY status register - remember LINK-UP status
2783
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2784
 
2785
  for (i = 0; i <= 1; i = i + 1)
2786
  begin
2787
    #Tp eth_phy.preamble_suppresed(i);
2788
    // MII mode register
2789
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2790
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2791
    if (i)
2792
    begin
2793
      // change saved data when preamble is suppressed
2794
      #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
2795
    end
2796
 
2797
    // scan request
2798
    #Tp mii_scan_req(phy_addr, reg_addr);
2799
    check_mii_scan_valid; // wait for scan to make first data valid
2800
 
2801
    fork
2802
    begin
2803
      repeat(2) @(posedge Mdc_O);
2804
      // read data from PHY status register
2805
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2806
      if (phy_data !== tmp_data)
2807
      begin
2808
        test_fail("Data was not correctly scaned from status register");
2809
        fail = fail + 1;
2810
      end
2811
      // read data from MII status register
2812
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2813
      if (phy_data[0] !== 1'b0)
2814
      begin
2815
        test_fail("Link FAIL bit was set in the MII status register");
2816
        fail = fail + 1;
2817
      end
2818
    end
2819
    begin
2820
    // Completely check second scan
2821
      #Tp cnt = 0;
2822
      // wait for serial bus to become active - second scan
2823
      wait(Mdio_IO !== 1'bz);
2824
      // count transfer length
2825
      while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
2826
      begin
2827
        @(posedge Mdc_O);
2828
        #Tp cnt = cnt + 1;
2829
      end
2830
      // check transfer length
2831
      if (i) // without preamble
2832
      begin
2833
        if (cnt != 33) // at this value Mdio_IO is HIGH Z
2834
        begin
2835
          test_fail("Second scan request did not proceed correctly");
2836
          fail = fail + 1;
2837
        end
2838
      end
2839
      else // with preamble
2840
      begin
2841
        if (cnt != 65) // at this value Mdio_IO is HIGH Z
2842
        begin
2843
          test_fail("Second scan request did not proceed correctly");
2844
          fail = fail + 1;
2845
        end
2846
      end
2847
    end
2848
    join
2849
    // check third to fifth scans
2850
    for (i3 = 0; i3 <= 2; i3 = i3 + 1)
2851
    begin
2852
      fork
2853
      begin
2854
        repeat(2) @(posedge Mdc_O);
2855
        // read data from PHY status register
2856
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2857
        if (phy_data !== tmp_data)
2858
        begin
2859
          test_fail("Data was not correctly scaned from status register");
2860
          fail = fail + 1;
2861
        end
2862
        // read data from MII status register
2863
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2864
        if (phy_data[0] !== 1'b0)
2865
        begin
2866
          test_fail("Link FAIL bit was set in the MII status register");
2867
          fail = fail + 1;
2868
        end
2869
        if (i3 == 2) // after fourth scan read
2870
        begin
2871
          @(posedge Mdc_O);
2872
          // change saved data
2873
          #Tp tmp_data = tmp_data & 16'hFFFB; // put bit 3 to ZERO
2874
          // set link down
2875
          #Tp eth_phy.link_up_down(0);
2876
        end
2877
      end
2878
      begin
2879
      // Completely check scans
2880
        #Tp cnt = 0;
2881
        // wait for serial bus to become active - second scan
2882
        wait(Mdio_IO !== 1'bz);
2883
        // count transfer length
2884
        while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
2885
        begin
2886
          @(posedge Mdc_O);
2887
          #Tp cnt = cnt + 1;
2888
        end
2889
        // check transfer length
2890
        if (i) // without preamble
2891
        begin
2892
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2893
          begin
2894
            test_fail("Fifth scan request did not proceed correctly");
2895
            fail = fail + 1;
2896
          end
2897
        end
2898
        else // with preamble
2899
        begin
2900
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2901
          begin
2902
            test_fail("Fifth scan request did not proceed correctly");
2903
            fail = fail + 1;
2904
          end
2905
        end
2906
      end
2907
      join
2908
    end
2909
 
2910
    fork
2911
    begin
2912
      repeat(2) @(posedge Mdc_O);
2913
      // read data from PHY status register
2914
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2915
      if (phy_data !== tmp_data)
2916
      begin
2917
        test_fail("Data was not correctly scaned from status register");
2918
        fail = fail + 1;
2919
      end
2920
      // read data from MII status register
2921
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2922
      if (phy_data[0] === 1'b0)
2923
      begin
2924
        test_fail("Link FAIL bit was not set in the MII status register");
2925
        fail = fail + 1;
2926
      end
2927
      // wait to see if data stayed latched
2928
      repeat(4) @(posedge Mdc_O);
2929
      // read data from PHY status register
2930
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2931
      if (phy_data !== tmp_data)
2932
      begin
2933
        test_fail("Data was not latched correctly in status register");
2934
        fail = fail + 1;
2935
      end
2936
      // read data from MII status register
2937
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2938
      if (phy_data[0] === 1'b0)
2939
      begin
2940
        test_fail("Link FAIL bit was not set in the MII status register");
2941
        fail = fail + 1;
2942
      end
2943
      // change saved data
2944
      #Tp tmp_data = tmp_data | 16'h0004; // put bit 2 to ONE
2945
      // set link up
2946
      #Tp eth_phy.link_up_down(1);
2947
    end
2948
    begin
2949
    // Wait for sixth scan
2950
      // wait for serial bus to become active - sixth scan
2951
      wait(Mdio_IO !== 1'bz);
2952
      // wait for serial bus to become inactive - turn-around cycle in sixth scan
2953
      wait(Mdio_IO === 1'bz);
2954
      // wait for serial bus to become active - end of turn-around cycle in sixth scan
2955
      wait(Mdio_IO !== 1'bz);
2956
      // wait for serial bus to become inactive - end of sixth scan
2957
      wait(Mdio_IO === 1'bz);
2958
    end
2959
    join
2960
 
2961
    @(posedge Mdc_O);
2962
    // read data from PHY status register
2963
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2964
    if (phy_data !== tmp_data)
2965
    begin
2966
      test_fail("Data was not correctly scaned from status register");
2967
      fail = fail + 1;
2968
    end
2969
    // read data from MII status register
2970
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2971
    if (phy_data[0] !== 1'b0)
2972
    begin
2973
      test_fail("Link FAIL bit was set in the MII status register");
2974
      fail = fail + 1;
2975
    end
2976
    // wait to see if data stayed latched
2977
    repeat(4) @(posedge Mdc_O