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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Blame information for rev 177

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1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet.v                                               ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 169 mohor
////      - Tadej Markovic, tadej@opencores.org                   ////
10 170 mohor
////      - Igor Mohor,     igormM@opencores.org                  ////
11 116 mohor
////                                                              ////
12 169 mohor
////  All additional information is available in the Readme.txt   ////
13 116 mohor
////  file.                                                       ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2001, 2002 Authors                             ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 177 mohor
// Revision 1.7  2002/09/13 12:29:14  mohor
46
// Headers changed.
47
//
48 170 mohor
// Revision 1.6  2002/09/13 11:57:20  mohor
49
// New testbench. Thanks to Tadej M - "The Spammer".
50
//
51 121 mohor
// Revision 1.2  2002/07/19 14:02:47  mohor
52
// Clock mrx_clk set to 2.5 MHz.
53
//
54 117 mohor
// Revision 1.1  2002/07/19 13:57:53  mohor
55
// Testing environment also includes traffic cop, memory interface and host
56
// interface.
57 116 mohor
//
58
//
59
//
60
//
61 117 mohor
//
62 116 mohor
 
63
 
64 169 mohor
`define TIME $display("  Time: %0t", $time)
65 116 mohor
 
66 169 mohor
`include "eth_phy_defines.v"
67
`include "wb_model_defines.v"
68 116 mohor
`include "tb_eth_defines.v"
69
`include "eth_defines.v"
70
`include "timescale.v"
71
 
72
module tb_ethernet();
73
 
74
 
75 169 mohor
reg           wb_clk;
76
reg           wb_rst;
77
wire          wb_int;
78 116 mohor
 
79 169 mohor
wire          mtx_clk;  // This goes to PHY
80
wire          mrx_clk;  // This goes to PHY
81 116 mohor
 
82
wire   [3:0]  MTxD;
83
wire          MTxEn;
84
wire          MTxErr;
85
 
86 169 mohor
wire   [3:0]  MRxD;     // This goes to PHY
87
wire          MRxDV;    // This goes to PHY
88
wire          MRxErr;   // This goes to PHY
89
wire          MColl;    // This goes to PHY
90
wire          MCrs;     // This goes to PHY
91 116 mohor
 
92
wire          Mdi_I;
93
wire          Mdo_O;
94
wire          Mdo_OE;
95 169 mohor
tri           Mdio_IO;
96 116 mohor
wire          Mdc_O;
97
 
98
 
99 169 mohor
parameter Tp = 1;
100 116 mohor
 
101 121 mohor
 
102 116 mohor
// Ethernet Slave Interface signals
103 169 mohor
wire [31:0] eth_sl_wb_adr;
104 116 mohor
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
105
wire  [3:0] eth_sl_wb_sel_i;
106
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
107
 
108
// Ethernet Master Interface signals
109
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
110
wire  [3:0] eth_ma_wb_sel_o;
111
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
112
 
113
 
114
 
115
 
116
// Connecting Ethernet top module
117 169 mohor
eth_top eth_top
118 116 mohor
(
119
  // WISHBONE common
120 169 mohor
  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),
121 116 mohor
 
122
  // WISHBONE slave
123 169 mohor
  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
124
  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
125
  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
126 116 mohor
 
127
  // WISHBONE master
128
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
129
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
130
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
131
 
132
  //TX
133
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
134
 
135
  //RX
136
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
137
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
138
 
139
  // MIIM
140
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
141
 
142 169 mohor
  .int_o(wb_int)
143 116 mohor
);
144
 
145
 
146
 
147 169 mohor
// Connecting Ethernet PHY Module
148
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
149
assign Mdi_I   = Mdio_IO;
150
integer phy_log_file_desc;
151
 
152
eth_phy eth_phy
153 116 mohor
(
154 169 mohor
  // WISHBONE reset
155
  .m_rst_n_i(!wb_rst),
156 116 mohor
 
157 169 mohor
  // MAC TX
158
  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),
159
 
160
  // MAC RX
161
  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),
162
  .mcoll_o(MColl),        .mcrs_o(MCrs),
163
 
164
  // MIIM
165
  .mdc_i(Mdc_O),          .md_io(Mdio_IO),
166
 
167
  // SYSTEM
168
  .phy_log(phy_log_file_desc)
169 116 mohor
);
170
 
171
 
172 169 mohor
 
173
// Connecting WB Master as Host Interface
174
integer host_log_file_desc;
175
 
176
WB_MASTER_BEHAVIORAL wb_master
177 116 mohor
(
178 169 mohor
    .CLK_I(wb_clk),
179
    .RST_I(wb_rst),
180
    .TAG_I({`WB_TAG_WIDTH{1'b0}}),
181
    .TAG_O(),
182
    .ACK_I(eth_sl_wb_ack_o),
183
    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
184
    .CYC_O(eth_sl_wb_cyc_i),
185
    .DAT_I(eth_sl_wb_dat_o),
186
    .DAT_O(eth_sl_wb_dat_i),
187
    .ERR_I(eth_sl_wb_err_o),
188
    .RTY_I(1'b0),  // inactive (1'b0)
189
    .SEL_O(eth_sl_wb_sel_i),
190
    .STB_O(eth_sl_wb_stb_i),
191
    .WE_O (eth_sl_wb_we_i),
192
    .CAB_O()       // NOT USED for now!
193
);
194
 
195
assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
196
 
197
 
198
 
199
// Connecting WB Slave as Memory Interface Module
200
integer memory_log_file_desc;
201
 
202
WB_SLAVE_BEHAVIORAL wb_slave
203
(
204
    .CLK_I(wb_clk),
205
    .RST_I(wb_rst),
206
    .ACK_O(eth_ma_wb_ack_i),
207
    .ADR_I(eth_ma_wb_adr_o),
208
    .CYC_I(eth_ma_wb_cyc_o),
209
    .DAT_O(eth_ma_wb_dat_i),
210
    .DAT_I(eth_ma_wb_dat_o),
211
    .ERR_O(eth_ma_wb_err_i),
212
    .RTY_O(),      // NOT USED for now!
213
    .SEL_I(eth_ma_wb_sel_o),
214
    .STB_I(eth_ma_wb_stb_o),
215
    .WE_I (eth_ma_wb_we_o),
216
    .CAB_I(1'b0)   // inactive (1'b0)
217
);
218
 
219
 
220
 
221
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
222
integer wb_s_mon_log_file_desc ;
223
integer wb_m_mon_log_file_desc ;
224
 
225
WB_BUS_MON wb_eth_slave_bus_mon
226
(
227 116 mohor
  // WISHBONE common
228 169 mohor
  .CLK_I(wb_clk),
229
  .RST_I(wb_rst),
230 116 mohor
 
231 169 mohor
  // WISHBONE slave
232
  .ACK_I(eth_sl_wb_ack_o),
233
  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),
234
  .CYC_O(eth_sl_wb_cyc_i),
235
  .DAT_I(eth_sl_wb_dat_o),
236
  .DAT_O(eth_sl_wb_dat_i),
237
  .ERR_I(eth_sl_wb_err_o),
238
  .RTY_I(1'b0),
239
  .SEL_O(eth_sl_wb_sel_i),
240
  .STB_O(eth_sl_wb_stb_i),
241
  .WE_O (eth_sl_wb_we_i),
242
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
243
  .TAG_O(),
244
  .CAB_O(1'b0),
245
  .log_file_desc (wb_s_mon_log_file_desc)
246
);
247
 
248
WB_BUS_MON wb_eth_master_bus_mon
249
(
250
  // WISHBONE common
251
  .CLK_I(wb_clk),
252
  .RST_I(wb_rst),
253
 
254 116 mohor
  // WISHBONE master
255 169 mohor
  .ACK_I(eth_ma_wb_ack_i),
256
  .ADDR_O(eth_ma_wb_adr_o),
257
  .CYC_O(eth_ma_wb_cyc_o),
258
  .DAT_I(eth_ma_wb_dat_i),
259
  .DAT_O(eth_ma_wb_dat_o),
260
  .ERR_I(eth_ma_wb_err_i),
261
  .RTY_I(1'b0),
262
  .SEL_O(eth_ma_wb_sel_o),
263
  .STB_O(eth_ma_wb_stb_o),
264
  .WE_O (eth_ma_wb_we_o),
265
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
266
  .TAG_O(),
267
  .CAB_O(1'b0),
268
  .log_file_desc(wb_m_mon_log_file_desc)
269 116 mohor
);
270
 
271
 
272
 
273 169 mohor
reg         StartTB;
274
integer     tb_log_file;
275 116 mohor
 
276 169 mohor
initial
277
begin
278
  tb_log_file = $fopen("../log/eth_tb.log");
279
  if (tb_log_file < 2)
280
  begin
281
    $display("*E Could not open/create testbench log file in ../log/ directory!");
282
    $finish;
283
  end
284
  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");
285
  $fdisplay(tb_log_file, " ");
286 116 mohor
 
287 169 mohor
  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");
288
  if (phy_log_file_desc < 2)
289
  begin
290
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");
291
    $finish;
292
  end
293
  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");
294
  $fdisplay(phy_log_file_desc, " ");
295
 
296
  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");
297
  if (memory_log_file_desc < 2)
298
  begin
299
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");
300
    $finish;
301
  end
302
  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");
303
  $fdisplay(memory_log_file_desc, " ");
304
 
305
  host_log_file_desc = $fopen("../log/eth_tb_host.log");
306
  if (host_log_file_desc < 2)
307
  begin
308
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");
309
    $finish;
310
  end
311
  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");
312
  $fdisplay(host_log_file_desc, " ");
313
 
314
  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");
315
  if (wb_s_mon_log_file_desc < 2)
316
  begin
317
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");
318
    $finish;
319
  end
320
  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");
321
  $fdisplay(wb_s_mon_log_file_desc, " ");
322
  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
323
  $fdisplay(wb_s_mon_log_file_desc, " ");
324
 
325
  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");
326
  if (wb_m_mon_log_file_desc < 2)
327
  begin
328
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");
329
    $finish;
330
  end
331
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
332
  $fdisplay(wb_m_mon_log_file_desc, " ");
333
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
334
  $fdisplay(wb_m_mon_log_file_desc, " ");
335
 
336
  // Clear memories
337
  clear_memories;
338
 
339
  // Reset pulse
340
  wb_rst =  1'b1;
341
  #423 wb_rst =  1'b0;
342
  #423 StartTB  =  1'b1;
343
end
344
 
345
 
346
 
347
// Generating wb_clk clock
348 116 mohor
initial
349
begin
350 169 mohor
  wb_clk=0;
351
//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    
352
//  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    
353
//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    
354
//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    
355
//  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    
356
  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    
357
//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz
358
//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    
359
//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz
360
//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    
361 116 mohor
end
362
 
363
 
364
 
365 169 mohor
integer      tests_successfull;
366
integer      tests_failed;
367
reg [799:0]  test_name; // used for tb_log_file
368 121 mohor
 
369 169 mohor
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
370
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
371
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
372
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
373
 
374 116 mohor
initial
375
begin
376 169 mohor
  wait(StartTB);  // Start of testbench
377
 
378
  // Initial global values
379
  tests_successfull = 0;
380
  tests_failed = 0;
381
 
382
  wbm_init_waits = 4'h1;
383
  wbm_subseq_waits = 4'h3;
384
  wbs_waits = 4'h1;
385
  wbs_retries = 8'h2;
386
  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
387
 
388
 
389
  //  Call tests
390
  //  ----------
391 177 mohor
//    test_access_to_mac_reg(0, 3);          // 0 - 3
392
//    test_mii(0, 17);                        // 0 - 17
393
    test_mii(0, 1);                        // 0 - 17
394 169 mohor
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
395
  eth_phy.carrier_sense_real_delay(0);
396
    test_mac_full_duplex_transmit(0, 3);   // 0 - (3)
397
 
398
  test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
399
  eth_phy.carrier_sense_real_delay(1);
400
 
401
 
402
  // Finish test's logs
403
  test_summary;
404
  $display("\n\n END of SIMULATION");
405
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
406
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);
407
 
408
  $stop;
409 116 mohor
end
410 169 mohor
 
411 116 mohor
 
412 169 mohor
 
413
//////////////////////////////////////////////////////////////
414
// Test tasks
415
//////////////////////////////////////////////////////////////
416
 
417
task test_access_to_mac_reg;
418
  input  [31:0]  start_task;
419
  input  [31:0]  end_task;
420
  integer        bit_start_1;
421
  integer        bit_end_1;
422
  integer        bit_start_2;
423
  integer        bit_end_2;
424
  integer        num_of_reg;
425
  integer        i_addr;
426
  integer        i_data;
427
  integer        i_length;
428
  integer        tmp_data;
429
  reg    [31:0]  tx_bd_num;
430
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
431
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
432
  integer        i;
433
  integer        i1;
434
  integer        i2;
435
  integer        i3;
436
  integer        fail;
437
  reg    [31:0]  addr;
438
  reg    [31:0]  data;
439
  reg    [31:0]  data_max;
440 116 mohor
begin
441 169 mohor
// ACCESS TO MAC REGISTERS TEST
442
test_heading("ACCESS TO MAC REGISTERS TEST");
443
$display(" ");
444
$display("ACCESS TO MAC REGISTERS TEST");
445
fail = 0;
446
 
447
  /* Register space
448
     --------------
449
  `define ETH_MODER      `ETH_BASE + 32'h00      Mode Register
450
  `define ETH_INT        `ETH_BASE + 32'h04      Interrupt Source Register
451
  `define ETH_INT_MASK   `ETH_BASE + 32'h08      Interrupt Mask Register
452
  `define ETH_IPGT       `ETH_BASE + 32'h0C      Back to Bak Inter Packet Gap Register
453
  `define ETH_IPGR1      `ETH_BASE + 32'h10      Non Back to Back Inter Packet Gap Register 1
454
  `define ETH_IPGR2      `ETH_BASE + 32'h14      Non Back to Back Inter Packet Gap Register 2
455
  `define ETH_PACKETLEN  `ETH_BASE + 32'h18      Packet Length Register (min. and max.)
456
  `define ETH_COLLCONF   `ETH_BASE + 32'h1C      Collision and Retry Configuration Register
457
  `define ETH_TX_BD_NUM  `ETH_BASE + 32'h20      Transmit Buffer Descriptor Number Register
458
  `define ETH_CTRLMODER  `ETH_BASE + 32'h24      Control Module Mode Register
459
  `define ETH_MIIMODER   `ETH_BASE + 32'h28      MII Mode Register
460
  `define ETH_MIICOMMAND `ETH_BASE + 32'h2C      MII Command Register
461
  `define ETH_MIIADDRESS `ETH_BASE + 32'h30      MII Address Register
462
  `define ETH_MIITX_DATA `ETH_BASE + 32'h34      MII Transmit Data Register
463
  `define ETH_MIIRX_DATA `ETH_BASE + 32'h38      MII Receive Data Register
464
  `define ETH_MIISTATUS  `ETH_BASE + 32'h3C      MII Status Register
465
  `define ETH_MAC_ADDR0  `ETH_BASE + 32'h40      MAC Individual Address Register 0
466
  `define ETH_MAC_ADDR1  `ETH_BASE + 32'h44      MAC Individual Address Register 1
467
  `define ETH_HASH_ADDR0 `ETH_BASE + 32'h48      Hash Register 0
468
  `define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C      Hash Register 1
469
  */
470
 
471
 
472
if ((start_task <= 0) && (end_task >= 0))
473
begin
474
  // TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
475
  test_name   = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
476
  `TIME; $display("  TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
477
 
478
  data = 0;
479
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
480
  begin
481
      wbm_init_waits = i;
482
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
483
      for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
484
      begin
485
        addr = `ETH_BASE + i_addr;
486
        // set ranges of R/W bits
487
        case (addr)
488
        `ETH_MODER:
489
          begin
490
            bit_start_1 = 0;
491
            bit_end_1   = 16;
492
            bit_start_2 = 32; // not used
493
            bit_end_2   = 32; // not used
494
          end
495
        `ETH_INT: // READONLY - tested within INT test
496
          begin
497
            bit_start_1 = 32; // not used
498
            bit_end_1   = 32; // not used
499
            bit_start_2 = 32; // not used
500
            bit_end_2   = 32; // not used
501
          end
502
        `ETH_INT_MASK:
503
          begin
504
            bit_start_1 = 0;
505
            bit_end_1   = 6;
506
            bit_start_2 = 32; // not used
507
            bit_end_2   = 32; // not used
508
          end
509
        `ETH_IPGT:
510
          begin
511
            bit_start_1 = 0;
512
            bit_end_1   = 6;
513
            bit_start_2 = 32; // not used
514
            bit_end_2   = 32; // not used
515
          end
516
        `ETH_IPGR1:
517
          begin
518
            bit_start_1 = 0;
519
            bit_end_1   = 6;
520
            bit_start_2 = 32; // not used
521
            bit_end_2   = 32; // not used
522
          end
523
        `ETH_IPGR2:
524
          begin
525
            bit_start_1 = 0;
526
            bit_end_1   = 6;
527
            bit_start_2 = 32; // not used
528
            bit_end_2   = 32; // not used
529
          end
530
        `ETH_PACKETLEN:
531
          begin
532
            bit_start_1 = 0;
533
            bit_end_1   = 31;
534
            bit_start_2 = 32; // not used
535
            bit_end_2   = 32; // not used
536
          end
537
        `ETH_COLLCONF:
538
          begin
539
            bit_start_1 = 0;
540
            bit_end_1   = 5;
541
            bit_start_2 = 16;
542
            bit_end_2   = 19;
543
          end
544
        `ETH_TX_BD_NUM:
545
          begin
546
            bit_start_1 = 0;
547
            bit_end_1   = 7;
548
            bit_start_2 = 32; // not used
549
            bit_end_2   = 32; // not used
550
          end
551
        `ETH_CTRLMODER:
552
          begin
553
            bit_start_1 = 0;
554
            bit_end_1   = 2;
555
            bit_start_2 = 32; // not used
556
            bit_end_2   = 32; // not used
557
          end
558
        `ETH_MIIMODER:
559
          begin
560
            bit_start_1 = 0;
561
            bit_end_1   = 9;
562
            bit_start_2 = 32; // not used
563
            bit_end_2   = 32; // not used
564
          end
565
        `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
566
          begin
567
            bit_start_1 = 32; // not used
568
            bit_end_1   = 32; // not used
569
            bit_start_2 = 32; // not used
570
            bit_end_2   = 32; // not used
571
          end
572
        `ETH_MIIADDRESS:
573
          begin
574
            bit_start_1 = 0;
575
            bit_end_1   = 4;
576
            bit_start_2 = 8;
577
            bit_end_2   = 12;
578
          end
579
        `ETH_MIITX_DATA:
580
          begin
581
            bit_start_1 = 0;
582
            bit_end_1   = 15;
583
            bit_start_2 = 32; // not used
584
            bit_end_2   = 32; // not used
585
          end
586
        `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
587
          begin
588
            bit_start_1 = 32; // not used
589
            bit_end_1   = 32; // not used
590
            bit_start_2 = 32; // not used
591
            bit_end_2   = 32; // not used
592
          end
593
        `ETH_MIISTATUS: // READONLY - tested within MIIM test
594
          begin
595
            bit_start_1 = 32; // not used
596
            bit_end_1   = 32; // not used
597
            bit_start_2 = 32; // not used
598
            bit_end_2   = 32; // not used
599
          end
600
        `ETH_MAC_ADDR0:
601
          begin
602
            bit_start_1 = 0;
603
            bit_end_1   = 31;
604
            bit_start_2 = 32; // not used
605
            bit_end_2   = 32; // not used
606
          end
607
        `ETH_MAC_ADDR1:
608
          begin
609
            bit_start_1 = 0;
610
            bit_end_1   = 15;
611
            bit_start_2 = 32; // not used
612
            bit_end_2   = 32; // not used
613
          end
614
        `ETH_HASH_ADDR0:
615
          begin
616
            bit_start_1 = 0;
617
            bit_end_1   = 31;
618
            bit_start_2 = 32; // not used
619
            bit_end_2   = 32; // not used
620
          end
621
        default: // `ETH_HASH_ADDR1:
622
          begin
623
            bit_start_1 = 0;
624
            bit_end_1   = 31;
625
            bit_start_2 = 32; // not used
626
            bit_end_2   = 32; // not used
627
          end
628
        endcase
629
        for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
630
        begin
631
          data = 1'b1 << i_data;
632
          if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
633
          begin
634
          end
635
          else
636
          begin
637
            wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
638
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
639
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
640
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
641
            begin
642
              if (tmp_data !== data)
643
              begin
644
                fail = fail + 1;
645
                test_fail("RW bit of the MAC register was not written or not read");
646
                `TIME;
647
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
648
                          wbm_init_waits, addr, data, tmp_data);
649
              end
650
            end
651
            else // data should not be equal to tmp_data
652
            begin
653
              if (tmp_data === data)
654
              begin
655
                fail = fail + 1;
656
                test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
657
                `TIME;
658
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
659
                          wbm_init_waits, addr, data, tmp_data);
660
              end
661
            end
662
          end
663
        end
664
      end
665
  end
666
  if(fail == 0)
667
    test_ok;
668
  else
669
    fail = 0;    // Errors were reported previously
670 116 mohor
end
671
 
672 169 mohor
 
673
if ((start_task <= 4) && (end_task >= 4)) // not used, since burst access to reg. is not supported
674 116 mohor
begin
675 169 mohor
/*  // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
676
  test_name   = "TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
677
  `TIME; $display("  TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
678
 
679
  data = 0;
680
  burst_data = 0;
681
  burst_tmp_data = 0;
682
  i_length = 10; // two bursts for length 20
683
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
684
  begin
685
    for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
686
    begin
687
      wbm_init_waits = i;
688
      wbm_subseq_waits = i1;
689
      #1;
690
      for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
691
      begin
692
        data = 1'b1 << i_data;
693
        #1;
694
        for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
695
        begin
696
          burst_data = burst_data << 32;
697
          // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
698
          if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
699
          begin
700
            #1 burst_data[31:0] = 0;
701
          end
702
          else
703
          begin
704
            #1 burst_data[31:0] = data;
705
          end
706
        end
707
        #1;
708
        // 2 burst writes
709
        addr = `ETH_BASE; // address of a first burst
710
        wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
711
        burst_tmp_data = burst_data >> (32 * i_length);
712
        addr = addr + 32'h28; // address of a second burst
713
        wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
714
        #1;
715
        // 2 burst reads
716
        addr = `ETH_BASE; // address of a first burst
717
        wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
718
                 wbm_init_waits, wbm_subseq_waits); // first burst
719
        burst_tmp_data = burst_tmp_data << (32 * i_length);
720
        addr = addr + 32'h28; // address of a second burst
721
        wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
722
                 wbm_init_waits, wbm_subseq_waits); // second burst
723
        #1;
724
        for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
725
        begin
726
          // set ranges of R/W bits
727
          case (`ETH_BASE + i2)
728
          `ETH_MODER:
729
            begin
730
              bit_start_1 = 0;
731
              bit_end_1   = 16;
732
              bit_start_2 = 32; // not used
733
              bit_end_2   = 32; // not used
734
            end
735
          `ETH_INT: // READONLY - tested within INT test
736
            begin
737
              bit_start_1 = 32; // not used
738
              bit_end_1   = 32; // not used
739
              bit_start_2 = 32; // not used
740
              bit_end_2   = 32; // not used
741
            end
742
          `ETH_INT_MASK:
743
            begin
744
              bit_start_1 = 0;
745
              bit_end_1   = 6;
746
              bit_start_2 = 32; // not used
747
              bit_end_2   = 32; // not used
748
            end
749
          `ETH_IPGT:
750
            begin
751
              bit_start_1 = 0;
752
              bit_end_1   = 6;
753
              bit_start_2 = 32; // not used
754
              bit_end_2   = 32; // not used
755
            end
756
          `ETH_IPGR1:
757
            begin
758
              bit_start_1 = 0;
759
              bit_end_1   = 6;
760
              bit_start_2 = 32; // not used
761
              bit_end_2   = 32; // not used
762
            end
763
          `ETH_IPGR2:
764
            begin
765
              bit_start_1 = 0;
766
              bit_end_1   = 6;
767
              bit_start_2 = 32; // not used
768
              bit_end_2   = 32; // not used
769
            end
770
          `ETH_PACKETLEN:
771
            begin
772
              bit_start_1 = 0;
773
              bit_end_1   = 31;
774
              bit_start_2 = 32; // not used
775
              bit_end_2   = 32; // not used
776
            end
777
          `ETH_COLLCONF:
778
            begin
779
              bit_start_1 = 0;
780
              bit_end_1   = 5;
781
              bit_start_2 = 16;
782
              bit_end_2   = 19;
783
            end
784
          `ETH_TX_BD_NUM:
785
            begin
786
              bit_start_1 = 0;
787
              bit_end_1   = 7;
788
              bit_start_2 = 32; // not used
789
              bit_end_2   = 32; // not used
790
            end
791
          `ETH_CTRLMODER:
792
            begin
793
              bit_start_1 = 0;
794
              bit_end_1   = 2;
795
              bit_start_2 = 32; // not used
796
              bit_end_2   = 32; // not used
797
            end
798
          `ETH_MIIMODER:
799
            begin
800
              bit_start_1 = 0;
801
              bit_end_1   = 9;
802
              bit_start_2 = 32; // not used
803
              bit_end_2   = 32; // not used
804
            end
805
          `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
806
            begin
807
              bit_start_1 = 32; // not used
808
              bit_end_1   = 32; // not used
809
              bit_start_2 = 32; // not used
810
              bit_end_2   = 32; // not used
811
            end
812
          `ETH_MIIADDRESS:
813
            begin
814
              bit_start_1 = 0;
815
              bit_end_1   = 4;
816
              bit_start_2 = 8;
817
              bit_end_2   = 12;
818
            end
819
          `ETH_MIITX_DATA:
820
            begin
821
              bit_start_1 = 0;
822
              bit_end_1   = 15;
823
              bit_start_2 = 32; // not used
824
              bit_end_2   = 32; // not used
825
            end
826
          `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
827
            begin
828
              bit_start_1 = 32; // not used
829
              bit_end_1   = 32; // not used
830
              bit_start_2 = 32; // not used
831
              bit_end_2   = 32; // not used
832
            end
833
          `ETH_MIISTATUS: // READONLY - tested within MIIM test
834
            begin
835
              bit_start_1 = 32; // not used
836
              bit_end_1   = 32; // not used
837
              bit_start_2 = 32; // not used
838
              bit_end_2   = 32; // not used
839
            end
840
          `ETH_MAC_ADDR0:
841
            begin
842
              bit_start_1 = 0;
843
              bit_end_1   = 31;
844
              bit_start_2 = 32; // not used
845
              bit_end_2   = 32; // not used
846
            end
847
          `ETH_MAC_ADDR1:
848
            begin
849
              bit_start_1 = 0;
850
              bit_end_1   = 15;
851
              bit_start_2 = 32; // not used
852
              bit_end_2   = 32; // not used
853
            end
854
          `ETH_HASH_ADDR0:
855
            begin
856
              bit_start_1 = 0;
857
              bit_end_1   = 31;
858
              bit_start_2 = 32; // not used
859
              bit_end_2   = 32; // not used
860
            end
861
          default: // `ETH_HASH_ADDR1:
862
            begin
863
              bit_start_1 = 0;
864
              bit_end_1   = 31;
865
              bit_start_2 = 32; // not used
866
              bit_end_2   = 32; // not used
867
            end
868
          endcase
869
          #1;
870
          // 3 LSBits of MIICOMMAND are NOT written !!!
871
          if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
872
          begin
873
            if (burst_tmp_data[31:0] !== burst_data[31:0])
874
            begin
875
              fail = fail + 1;
876
              test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
877
              `TIME;
878
              $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
879
                        wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
880
            end
881
          end
882
          else
883
          begin
884
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
885
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
886
            begin
887
              if (burst_tmp_data[31:0] !== burst_data[31:0])
888
              begin
889
                fail = fail + 1;
890
                test_fail("RW bit of the MAC register was not written or not read");
891
                `TIME;
892
                $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
893
                          wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
894
              end
895
            end
896
            else // data should not be equal to tmp_data
897
            begin
898
              if (burst_tmp_data[31:0] === burst_data[31:0])
899
              begin
900
                fail = fail + 1;
901
                test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
902
                `TIME;
903
                $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
904
                          wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
905
              end
906
            end
907
          end
908
          burst_tmp_data = burst_tmp_data >> 32;
909
          burst_data = burst_data >> 32;
910
        end
911
      end
912
    end
913
  end
914
  if(fail == 0)
915
    test_ok;
916
  else
917
    fail = 0;*/
918 116 mohor
end
919
 
920 169 mohor
 
921
if ((start_task <= 1) && (end_task >= 1))
922 116 mohor
begin
923 169 mohor
  // TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
924
  test_name   = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
925
  `TIME; $display("  TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
926 116 mohor
 
927 169 mohor
  data = 0;
928
  // set TX and RX buffer descriptors
929
  tx_bd_num = 32'h40;
930
  wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
931
  for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
932
  begin
933
    wbm_init_waits = i;
934
    wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
935
    for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
936
    begin
937
      addr = `ETH_BASE + i_addr;
938
      if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
939
      begin
940
        // set ranges of R/W bits
941
        case (addr[3])
942
        1'b0: // buffer control bits
943
          begin
944
            bit_start_1 = 0;
945
            bit_end_1   = 31; // 8;
946
            bit_start_2 = 11;
947
            bit_end_2   = 31;
948
          end
949
        default: // 1'b1: // buffer pointer
950
          begin
951
            bit_start_1 = 0;
952
            bit_end_1   = 31;
953
            bit_start_2 = 32; // not used
954
            bit_end_2   = 32; // not used
955
          end
956
        endcase
957
      end
958
      else // RX buffer descriptors
959
      begin
960
        // set ranges of R/W bits
961
        case (addr[3])
962
        1'b0: // buffer control bits
963
          begin
964
            bit_start_1 = 0;
965
            bit_end_1   = 31; // 7;
966
            bit_start_2 = 13;
967
            bit_end_2   = 31;
968
          end
969
        default: // 1'b1: // buffer pointer
970
          begin
971
            bit_start_1 = 0;
972
            bit_end_1   = 31;
973
            bit_start_2 = 32; // not used
974
            bit_end_2   = 32; // not used
975
          end
976
        endcase
977
      end
978 116 mohor
 
979 169 mohor
      for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
980
      begin
981
        data = 1'b1 << i_data;
982
        if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
983
        begin
984
        end
985
        else
986
        begin
987
          wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
988
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
989
          if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
990
               ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
991
          begin
992
            if (tmp_data !== data)
993
            begin
994
              fail = fail + 1;
995
              test_fail("RW bit of the MAC buffer descriptors was not written or not read");
996
              `TIME;
997
              $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
998
                        wbm_init_waits, addr, data, tmp_data);
999
            end
1000
          end
1001
          else // data should not be equal to tmp_data
1002
          begin
1003
            if (tmp_data === data)
1004
            begin
1005
              fail = fail + 1;
1006
              test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
1007
              `TIME;
1008
              $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
1009
                        wbm_init_waits, addr, data, tmp_data);
1010
            end
1011
          end
1012
        end
1013
      end
1014
    end
1015
    case (i)
1016
    0:       $display("    buffer descriptors tested with 0 bus delay");
1017
    1:       $display("    buffer descriptors tested with 1 bus delay cycle");
1018
    2:       $display("    buffer descriptors tested with 2 bus delay cycles");
1019
    3:       $display("    buffer descriptors tested with 3 bus delay cycles");
1020
    default: $display("    buffer descriptors tested with 4 bus delay cycles");
1021
    endcase
1022
  end
1023
  if(fail == 0)
1024
    test_ok;
1025
  else
1026
    fail = 0;
1027
end
1028 116 mohor
 
1029 169 mohor
  /* Register      RESET values    MAX. values
1030
     -----------------------------------------
1031
   ETH_MODER       32'h0000_A800   32'h0000_A800   Mode Register
1032
   ETH_INT         32'h0000_0000   32'h0000_0000   Interrupt Source Register
1033
   ETH_INT_MASK    32'h0000_0000   32'h0000_0000   Interrupt Mask Register
1034
   ETH_IPGT        32'h0000_0012   32'h0000_0012   Back to Bak Inter Packet Gap Register
1035
   ETH_IPGR1       32'h0000_000C   32'h0000_000C   Non Back to Back Inter Packet Gap Register 1
1036
   ETH_IPGR2       32'h0000_0012   32'h0000_0012   Non Back to Back Inter Packet Gap Register 2
1037
   ETH_PACKETLEN   32'h0040_0600   32'h0040_0600   Packet Length Register (min. and max.)
1038
   ETH_COLLCONF    32'h000F_003F   32'h000F_003F   Collision and Retry Configuration Register
1039
   ETH_TX_BD_NUM   32'h0000_0040   32'h0000_0080   Transmit Buffer Descriptor Number Register
1040
   ETH_CTRLMODER   32'h0000_0000   32'h0000_0000   Control Module Mode Register
1041
   ETH_MIIMODER    32'h0000_0064   32'h0000_0064   MII Mode Register
1042
   ETH_MIICOMMAND  32'h0000_0000   32'h0000_0000   MII Command Register
1043
   ETH_MIIADDRESS  32'h0000_0000   32'h0000_0000   MII Address Register
1044
   ETH_MIITX_DATA  32'h0000_0000   32'h0000_0000   MII Transmit Data Register
1045
   ETH_MIIRX_DATA  32'h0000_0000   32'h0000_0000   MII Receive Data Register
1046
   ETH_MIISTATUS   32'h0000_0000   32'h0000_0000   MII Status Register
1047
   ETH_MAC_ADDR0   32'h0000_0000   32'h0000_0000   MAC Individual Address Register 0
1048
   ETH_MAC_ADDR1   32'h0000_0000   32'h0000_0000   MAC Individual Address Register 1
1049
   ETH_HASH_ADDR0  32'h0000_0000   32'h0000_0000   Hash Register 0
1050
   ETH_HASH_ADDR1  32'h0000_0000   32'h0000_0000   Hash Register 1
1051
  */
1052 156 mohor
 
1053 116 mohor
 
1054 169 mohor
if ((start_task <= 2) && (end_task >= 2))
1055
begin
1056
  // TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
1057
  test_name   =
1058
  "TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
1059
  `TIME; $display(
1060
  "  TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
1061 158 mohor
 
1062 169 mohor
  // reset MAC registers
1063
  hard_reset;
1064
  for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
1065
  begin
1066
    for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
1067
    begin
1068
      addr = `ETH_BASE + i_addr;
1069
      // set ranges of R/W bits
1070
      case (addr)
1071
      `ETH_MODER:
1072
      begin
1073
        data = 32'h0000_A800;
1074
        data_max = 32'h0001_FFFF;
1075
      end
1076
      `ETH_INT: // READONLY - tested within INT test
1077
      begin
1078
        data = 32'h0000_0000;
1079
        data_max = 32'h0000_0000;
1080
      end
1081
      `ETH_INT_MASK:
1082
      begin
1083
        data = 32'h0000_0000;
1084
        data_max = 32'h0000_007F;
1085
      end
1086
      `ETH_IPGT:
1087
      begin
1088
        data = 32'h0000_0012;
1089
        data_max = 32'h0000_007F;
1090
      end
1091
      `ETH_IPGR1:
1092
      begin
1093
        data = 32'h0000_000C;
1094
        data_max = 32'h0000_007F;
1095
      end
1096
      `ETH_IPGR2:
1097
      begin
1098
        data = 32'h0000_0012;
1099
        data_max = 32'h0000_007F;
1100
      end
1101
      `ETH_PACKETLEN:
1102
      begin
1103
        data = 32'h0040_0600;
1104
        data_max = 32'hFFFF_FFFF;
1105
      end
1106
      `ETH_COLLCONF:
1107
      begin
1108
        data = 32'h000F_003F;
1109
        data_max = 32'h000F_003F;
1110
      end
1111
      `ETH_TX_BD_NUM:
1112
      begin
1113
        data = 32'h0000_0040;
1114
        data_max = 32'h0000_0080;
1115
      end
1116
      `ETH_CTRLMODER:
1117
      begin
1118
        data = 32'h0000_0000;
1119
        data_max = 32'h0000_0007;
1120
      end
1121
      `ETH_MIIMODER:
1122
      begin
1123
        data = 32'h0000_0064;
1124
        data_max = 32'h0000_03FF;
1125
      end
1126
      `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
1127
      begin
1128
        data = 32'h0000_0000;
1129
        data_max = 32'h0000_0007;
1130
      end
1131
      `ETH_MIIADDRESS:
1132
      begin
1133
        data = 32'h0000_0000;
1134
        data_max = 32'h0000_1F1F;
1135
      end
1136
      `ETH_MIITX_DATA:
1137
      begin
1138
        data = 32'h0000_0000;
1139
        data_max = 32'h0000_FFFF;
1140
      end
1141
      `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
1142
      begin
1143
        data = 32'h0000_0000;
1144
        data_max = 32'h0000_0000;
1145
      end
1146
      `ETH_MIISTATUS: // READONLY - tested within MIIM test
1147
      begin
1148
        data = 32'h0000_0000;
1149
        data_max = 32'h0000_0000;
1150
      end
1151
      `ETH_MAC_ADDR0:
1152
      begin
1153
        data = 32'h0000_0000;
1154
        data_max = 32'hFFFF_FFFF;
1155
      end
1156
      `ETH_MAC_ADDR1:
1157
      begin
1158
        data = 32'h0000_0000;
1159
        data_max = 32'h0000_FFFF;
1160
      end
1161
      `ETH_HASH_ADDR0:
1162
      begin
1163
        data = 32'h0000_0000;
1164
        data_max = 32'hFFFF_FFFF;
1165
      end
1166
      default: // `ETH_HASH_ADDR1:
1167
      begin
1168
        data = 32'h0000_0000;
1169
        data_max = 32'hFFFF_FFFF;
1170
      end
1171
      endcase
1172 116 mohor
 
1173 169 mohor
      wbm_init_waits = {$random} % 3;
1174
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1175
      if (i == 0)
1176
        wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1177
      else if (i == 2)
1178
        wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1179
      else if ((i == 1) || (i == 4))
1180
      begin
1181
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1182
        if (tmp_data !== data)
1183
        begin
1184
          fail = fail + 1;
1185
          test_fail("RESET value of the MAC register is not correct");
1186
          `TIME;
1187
          $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1188
        end
1189
      end
1190
      else // check maximum values
1191
      begin
1192
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1193
        if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
1194
        begin
1195
          if (tmp_data !== data)
1196
          begin
1197
            fail = fail + 1;
1198
            test_fail("Previous value of the TX_BD_NUM register did not remain");
1199
            `TIME;
1200
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1201
          end
1202
          // try maximum (80)
1203
          wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1204
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1205
          if (tmp_data !== data_max)
1206
          begin
1207
            fail = fail + 1;
1208
            test_fail("MAX value of the TX_BD_NUM register is not correct");
1209
            `TIME;
1210
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1211
          end
1212
          // try one less than maximum (80)
1213
          wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1214
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1215
          if (tmp_data !== (data_max - 1))
1216
          begin
1217
            fail = fail + 1;
1218
            test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
1219
            `TIME;
1220
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1221
          end
1222
          // try one more than maximum (80)
1223
          wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1224
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1225
          if (tmp_data !== (data_max - 1)) // previous data should remain in this register
1226
          begin
1227
            fail = fail + 1;
1228
            test_fail("Previous value of the TX_BD_NUM register did not remain");
1229
            `TIME;
1230
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1231
          end
1232
        end
1233
        else
1234
        begin
1235
          if (tmp_data !== data_max)
1236
          begin
1237
            fail = fail + 1;
1238
            test_fail("MAX value of the MAC register is not correct");
1239
            `TIME;
1240
            $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1241
          end
1242
        end
1243
      end
1244
    end
1245
    // reset MAC registers
1246
    if ((i == 0) || (i == 3))
1247
    begin
1248
      hard_reset;
1249
    end
1250
  end
1251
  if(fail == 0)
1252
    test_ok;
1253
  else
1254
    fail = 0;
1255
end
1256 116 mohor
 
1257
 
1258 169 mohor
if ((start_task <= 3) && (end_task >= 3))
1259
begin
1260
  // TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
1261
  test_name   = "TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
1262
  `TIME;
1263
  $display("  TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
1264 116 mohor
 
1265 169 mohor
  // reset MAC registers
1266
  hard_reset;
1267
  // reset LOGIC with soft reset
1268
  reset_mac;
1269
  reset_mii;
1270
  for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
1271
  begin
1272
    for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1273
    begin
1274
      addr = `ETH_BASE + i_addr;
1275 116 mohor
 
1276 169 mohor
      wbm_init_waits = {$random} % 3;
1277
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1278
      if (i == 0)
1279
      begin
1280
        data = 32'hFFFFFFFF;
1281
        wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1282
      end
1283
      else if (i == 2)
1284
      begin
1285
        data = 32'h00000000;
1286
        wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1287
      end
1288
      else
1289
      begin
1290
        wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1291
        if (tmp_data !== data)
1292
        begin
1293
          fail = fail + 1;
1294
          test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
1295
          `TIME;
1296
          $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1297
        end
1298
      end
1299
    end
1300
    if ((i == 0) || (i == 2))
1301
    begin
1302
      // reset MAC registers
1303
      hard_reset;
1304
      // reset LOGIC with soft reset
1305
      reset_mac;
1306
      reset_mii;
1307
    end
1308
  end
1309
  if(fail == 0)
1310
    test_ok;
1311
  else
1312
    fail = 0;
1313
end
1314 156 mohor
 
1315
 
1316 169 mohor
end
1317
endtask // test_access_to_mac_reg
1318 156 mohor
 
1319
 
1320 169 mohor
task test_mii;
1321
  input  [31:0]  start_task;
1322
  input  [31:0]  end_task;
1323
  integer        i;
1324
  integer        i1;
1325
  integer        i2;
1326
  integer        i3;
1327
  integer        cnt;
1328
  integer        fail;
1329
  reg     [8:0]  clk_div; // only 8 bits are valid!
1330
  reg     [4:0]  phy_addr;
1331
  reg     [4:0]  reg_addr;
1332
  reg     [15:0] phy_data;
1333
  reg     [15:0] tmp_data;
1334
begin
1335
// MIIM MODULE TEST
1336
test_heading("MIIM MODULE TEST");
1337
$display(" ");
1338
$display("MIIM MODULE TEST");
1339
fail = 0;
1340 156 mohor
 
1341 169 mohor
// reset MIIM LOGIC with soft reset
1342
reset_mii;
1343 116 mohor
 
1344
 
1345 169 mohor
if ((start_task <= 0) && (end_task >= 0))
1346
begin
1347
  // TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
1348
  test_name   = "TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
1349
  `TIME; $display("  TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
1350 116 mohor
 
1351 169 mohor
  wait(Mdc_O); // wait for MII clock to be 1
1352
  for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
1353
  begin
1354
    i1 = 0;
1355
    i2 = 0;
1356
    #Tp mii_set_clk_div(clk_div[7:0]);
1357
    @(posedge Mdc_O);
1358
    #Tp;
1359
    fork
1360
      begin
1361
        @(posedge Mdc_O);
1362
        #Tp;
1363
        disable count_i1;
1364
        disable count_i2;
1365
      end
1366
      begin: count_i1
1367
        forever
1368
        begin
1369
          @(posedge wb_clk);
1370
          i1 = i1 + 1;
1371
          #Tp;
1372
        end
1373
      end
1374
      begin: count_i2
1375
        forever
1376
        begin
1377
          @(negedge wb_clk);
1378
          i2 = i2 + 1;
1379
          #Tp;
1380
        end
1381
      end
1382
    join
1383
    if((clk_div[7:0] == 0) || (clk_div[7:0] == 1) || (clk_div[7:0] == 2) || (clk_div[7:0] == 3))
1384
    begin
1385
      if((i1 == i2) && (i1 == 2))
1386
      begin
1387
      end
1388
      else
1389
      begin
1390
        fail = fail + 1;
1391
        test_fail("Clock divider of MII module did'nt divide frequency corectly (it should divid with 2)");
1392
      end
1393
    end
1394
    else
1395
    begin
1396
      if((i1 == i2) && (i1 == {clk_div[7:1], 1'b0}))
1397
      begin
1398
      end
1399
      else
1400
      begin
1401
        fail = fail + 1;
1402
        test_fail("Clock divider of MII module did'nt divide frequency corectly");
1403
      end
1404
    end
1405
  end
1406
  if(fail == 0)
1407
    test_ok;
1408
  else
1409
    fail = 0;
1410 116 mohor
end
1411
 
1412
 
1413 169 mohor
if ((start_task <= 1) && (end_task >= 1))
1414
begin
1415
  // TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS
1416
  test_name   = "TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
1417
  `TIME; $display("  TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
1418
 
1419
  // set the fastest possible MII
1420
  clk_div = 0;
1421
  mii_set_clk_div(clk_div[7:0]);
1422
  // set address
1423
  reg_addr = 5'h1F;
1424
  phy_addr = 5'h1;
1425
  while(reg_addr >= 5'h4)
1426
  begin
1427
    // read request
1428
    #Tp mii_read_req(phy_addr, reg_addr);
1429
    check_mii_busy; // wait for read to finish
1430
    // read data
1431
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1432
    if (phy_data !== 16'hDEAD)
1433
    begin
1434
      test_fail("Wrong data was read from PHY from 'not used' address space");
1435
      fail = fail + 1;
1436
    end
1437
    if (reg_addr == 5'h4) // go out of for loop
1438
      reg_addr = 5'h3;
1439 116 mohor
    else
1440 169 mohor
      reg_addr = reg_addr - 5'h9;
1441
  end
1442 116 mohor
 
1443 169 mohor
  // set address
1444
  reg_addr = 5'h3;
1445
  // read request
1446
  #Tp mii_read_req(phy_addr, reg_addr);
1447
  check_mii_busy; // wait for read to finish
1448
  // read data
1449
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1450
  if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})
1451
  begin
1452
    test_fail("Wrong data was read from PHY from ID register 2");
1453
    fail = fail + 1;
1454 116 mohor
  end
1455 169 mohor
  if(fail == 0)
1456
    test_ok;
1457
  else
1458
    fail = 0;
1459
end
1460 116 mohor
 
1461
 
1462 169 mohor
if ((start_task <= 2) && (end_task >= 2))
1463
begin
1464
  // TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
1465
  test_name   = "TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
1466
  `TIME; $display("  TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
1467
 
1468
  // negate data and try to write into unwritable register
1469
  tmp_data = ~phy_data;
1470
  // write request
1471
  #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1472
  check_mii_busy; // wait for write to finish
1473
  // read request
1474
  #Tp mii_read_req(phy_addr, reg_addr);
1475
  check_mii_busy; // wait for read to finish
1476
  // read data
1477
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1478
  if (tmp_data !== phy_data)
1479
  begin
1480
    test_fail("Data was written into unwritable PHY register - ID register 2");
1481
    fail = fail + 1;
1482
  end
1483
 
1484
  // set address
1485
  reg_addr = 5'h0; // control register
1486
  // read request
1487
  #Tp mii_read_req(phy_addr, reg_addr);
1488
  check_mii_busy; // wait for read to finish
1489
  // read data
1490
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1491
  // write request
1492
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1493
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1494
  check_mii_busy; // wait for write to finish
1495
  // read request
1496
  #Tp mii_read_req(phy_addr, reg_addr);
1497
  check_mii_busy; // wait for read to finish
1498
  // read data
1499
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1500
  if (phy_data !== 16'h7DFF)
1501
  begin
1502
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1503
    fail = fail + 1;
1504
  end
1505
  // write request
1506
  #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1507
  check_mii_busy; // wait for write to finish
1508
  // read request
1509
  #Tp mii_read_req(phy_addr, reg_addr);
1510
  check_mii_busy; // wait for read to finish
1511
  // read data
1512
  #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1513
  if (phy_data !== tmp_data)
1514
  begin
1515
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1516
    fail = fail + 1;
1517
  end
1518
  if(fail == 0)
1519
    test_ok;
1520
  else
1521
    fail = 0;
1522
end
1523
 
1524
 
1525
if ((start_task <= 3) && (end_task >= 3))
1526
begin
1527
  // TEST RESET PHY THROUGH MII MANAGEMENT MODULE
1528
  test_name   = "TEST RESET PHY THROUGH MII MANAGEMENT MODULE";
1529
  `TIME; $display("  TEST RESET PHY THROUGH MII MANAGEMENT MODULE");
1530
 
1531
  // set address
1532
  reg_addr = 5'h0; // control register
1533
  // write request
1534
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1535
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1536
  check_mii_busy; // wait for write to finish
1537
  // read request
1538
  #Tp mii_read_req(phy_addr, reg_addr);
1539
  check_mii_busy; // wait for read to finish
1540
  // read data
1541
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1542
  if (phy_data !== tmp_data)
1543
  begin
1544
    test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1545
    fail = fail + 1;
1546
  end
1547
  // set reset bit - selfclearing bit in PHY
1548
  phy_data = phy_data | 16'h8000;
1549
  // write request
1550
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1551
  check_mii_busy; // wait for write to finish
1552
  // read request
1553
  #Tp mii_read_req(phy_addr, reg_addr);
1554
  check_mii_busy; // wait for read to finish
1555
  // read data
1556
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1557
  // check self clearing of reset bit
1558
  if (tmp_data[15] !== 1'b0)
1559
  begin
1560
    test_fail("Reset bit should be self cleared - control register");
1561
    fail = fail + 1;
1562
  end
1563
  // check reset value of control register
1564
  if (tmp_data !== {2'h0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 3'h0, `LED_CFG3, 8'h0})
1565
  begin
1566
    test_fail("PHY was not reset correctly AND/OR reset bit not self cleared");
1567
    fail = fail + 1;
1568
  end
1569
  if(fail == 0)
1570
    test_ok;
1571
  else
1572
    fail = 0;
1573
end
1574
 
1575
 
1576
if ((start_task <= 4) && (end_task >= 4))
1577
begin
1578
  // TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
1579
  test_name   = "TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1580
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1581
 
1582
  // set PHY to test mode
1583
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1584
  for (i = 0; i <= 1; i = i + 1)
1585
  begin
1586
    #Tp eth_phy.preamble_suppresed(i);
1587
    #Tp eth_phy.clear_test_regs;
1588
    // MII mode register
1589
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1590
              wbm_subseq_waits);
1591
    // walk one across phy address
1592
    for (phy_addr = 5'h1; phy_addr > 5'h0; phy_addr = phy_addr << 1)
1593
    begin
1594
      reg_addr = $random;
1595
      tmp_data = $random;
1596
      // write request
1597
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1598
      check_mii_busy; // wait for write to finish
1599
      // read request
1600
      #Tp mii_read_req(phy_addr, reg_addr);
1601
      check_mii_busy; // wait for read to finish
1602
      // read data
1603
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1604
      #Tp;
1605
      if (phy_data !== tmp_data)
1606
      begin
1607
        if (i)
1608
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1609
        else
1610
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1611
        fail = fail + 1;
1612
      end
1613
      @(posedge wb_clk);
1614
      #Tp;
1615
    end
1616
  end
1617
  // set PHY to normal mode
1618
  #Tp eth_phy.test_regs(0);
1619
  #Tp eth_phy.preamble_suppresed(0);
1620
  // MII mode register
1621
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1622
  if(fail == 0)
1623
    test_ok;
1624
  else
1625
    fail = 0;
1626
end
1627
 
1628
 
1629
if ((start_task <= 5) && (end_task >= 5))
1630
begin
1631
  // TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
1632
  test_name   = "TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1633
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1634
 
1635
  // set PHY to test mode
1636
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1637
  for (i = 0; i <= 1; i = i + 1)
1638
  begin
1639
    #Tp eth_phy.preamble_suppresed(i);
1640
    #Tp eth_phy.clear_test_regs;
1641
    // MII mode register
1642
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1643
              wbm_subseq_waits);
1644
    // walk one across reg address
1645
    for (reg_addr = 5'h1; reg_addr > 5'h0; reg_addr = reg_addr << 1)
1646
    begin
1647
      phy_addr = $random;
1648
      tmp_data = $random;
1649
      // write request
1650
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1651
      check_mii_busy; // wait for write to finish
1652
      // read request
1653
      #Tp mii_read_req(phy_addr, reg_addr);
1654
      check_mii_busy; // wait for read to finish
1655
      // read data
1656
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1657
      #Tp;
1658
      if (phy_data !== tmp_data)
1659
      begin
1660
        if (i)
1661
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1662
        else
1663
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1664
        fail = fail + 1;
1665
      end
1666
      @(posedge wb_clk);
1667
      #Tp;
1668
    end
1669
  end
1670
  // set PHY to normal mode
1671
  #Tp eth_phy.test_regs(0);
1672
  #Tp eth_phy.preamble_suppresed(0);
1673
  // MII mode register
1674
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1675
  if(fail == 0)
1676
    test_ok;
1677
  else
1678
    fail = 0;
1679
end
1680
 
1681
 
1682
if ((start_task <= 6) && (end_task >= 6))
1683
begin
1684
  // TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
1685
  test_name   = "TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
1686
  `TIME; $display("  TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
1687
 
1688
  // set PHY to test mode
1689
  #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1690
  for (i = 0; i <= 1; i = i + 1)
1691
  begin
1692
    #Tp eth_phy.preamble_suppresed(i);
1693
    #Tp eth_phy.clear_test_regs;
1694
    // MII mode register
1695
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1696
              wbm_subseq_waits);
1697
    // walk one across data
1698
    for (tmp_data = 16'h1; tmp_data > 16'h0; tmp_data = tmp_data << 1)
1699
    begin
1700
      phy_addr = $random;
1701
      reg_addr = $random;
1702
      // write request
1703
      #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1704
      check_mii_busy; // wait for write to finish
1705
      // read request
1706
      #Tp mii_read_req(phy_addr, reg_addr);
1707
      check_mii_busy; // wait for read to finish
1708
      // read data
1709
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1710
      #Tp;
1711
      if (phy_data !== tmp_data)
1712
      begin
1713
        if (i)
1714
          test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1715
        else
1716
          test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1717
        fail = fail + 1;
1718
      end
1719
      @(posedge wb_clk);
1720
      #Tp;
1721
    end
1722
  end
1723
  // set PHY to normal mode
1724
  #Tp eth_phy.test_regs(0);
1725
  #Tp eth_phy.preamble_suppresed(0);
1726
  // MII mode register
1727
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1728
  if(fail == 0)
1729
    test_ok;
1730
  else
1731
    fail = 0;
1732
end
1733
 
1734
 
1735
if ((start_task <= 7) && (end_task >= 7))
1736
begin
1737
  // TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
1738
  test_name   = "TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
1739
  `TIME; $display("  TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
1740
 
1741
  phy_addr = 5'h2; // wrong PHY address
1742
  // read request
1743
  #Tp mii_read_req(phy_addr, reg_addr);
1744
  check_mii_busy; // wait for read to finish
1745
  // read data
1746
  $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
1747
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1748
  if (tmp_data !== 16'hzzzz)
1749
  begin
1750
    test_fail("Data was read from PHY register with wrong PHY address - control register");
1751
    fail = fail + 1;
1752
  end
1753
  if(fail == 0)
1754
    test_ok;
1755
  else
1756
    fail = 0;
1757
end
1758
 
1759
 
1760
if ((start_task <= 8) && (end_task >= 8))
1761
begin
1762
  // TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
1763
  test_name   = "TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
1764
  `TIME; $display("  TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
1765
 
1766
  // set address
1767
  reg_addr = 5'h0; // control register
1768
  phy_addr = 5'h2; // wrong PHY address
1769
  // write request
1770
  phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1771
  #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1772
  check_mii_busy; // wait for write to finish
1773
 
1774
  phy_addr = 5'h1; // correct PHY address
1775
  // read request
1776
  #Tp mii_read_req(phy_addr, reg_addr);
1777
  check_mii_busy; // wait for read to finish
1778
  // read data
1779
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1780
  if (phy_data === tmp_data)
1781
  begin
1782
    test_fail("Data was written into PHY register with wrong PHY address - control register");
1783
    fail = fail + 1;
1784
  end
1785
  if(fail == 0)
1786
    test_ok;
1787
  else
1788
    fail = 0;
1789
end
1790
 
1791
 
1792
if ((start_task <= 9) && (end_task >= 9))
1793
begin
1794
  // TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
1795
  test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
1796
  `TIME;
1797
  $display("  TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
1798
 
1799
  for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1800
  begin
1801
    #Tp eth_phy.preamble_suppresed(i2);
1802
    // MII mode register
1803
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1804
             wbm_subseq_waits);
1805
    i = 0;
1806
    cnt = 0;
1807
    while (i < 80) // delay for sliding of writing a STOP SCAN command
1808
    begin
1809
      for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after read will be finished
1810
      begin
1811
        // set address
1812
        reg_addr = 5'h0; // control register
1813
        phy_addr = 5'h1; // correct PHY address
1814
        cnt = 0;
1815
        // read request
1816
        #Tp mii_read_req(phy_addr, reg_addr);
1817
        fork
1818
          begin
1819
            repeat(i) @(posedge Mdc_O);
1820
            // write command 0x0 into MII command register
1821
            // MII command written while read in progress
1822
            wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1823
            @(posedge wb_clk);
1824
            #Tp check_mii_busy; // wait for read to finish
1825
          end
1826
          begin
1827
            // wait for serial bus to become active
1828
            wait(Mdio_IO !== 1'bz);
1829
            // count transfer length
1830
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
1831
            begin
1832
              @(posedge Mdc_O);
1833
              #Tp cnt = cnt + 1;
1834
            end
1835
          end
1836
        join
1837
        // check transfer length
1838
        if (i2) // without preamble
1839
        begin
1840
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
1841
          begin
1842
            test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
1843
            fail = fail + 1;
1844
          end
1845
        end
1846
        else // with preamble
1847
        begin
1848
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
1849
          begin
1850
            test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
1851
            fail = fail + 1;
1852
          end
1853
        end
1854
        // check the BUSY signal to see if the bus is still IDLE
1855
        for (i1 = 0; i1 < 8; i1 = i1 + 1)
1856
          check_mii_busy; // wait for bus to become idle
1857 116 mohor
 
1858 169 mohor
        // try normal write or read after read was finished
1859
        #Tp phy_data = {8'h7D, (i[7:0] + 1)};
1860
        #Tp cnt = 0;
1861
        if (i3 == 0) // write after read
1862
        begin
1863
          // write request
1864
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1865
          // wait for serial bus to become active
1866
          wait(Mdio_IO !== 1'bz);
1867
          // count transfer length
1868
          while(Mdio_IO !== 1'bz)
1869
          begin
1870
            @(posedge Mdc_O);
1871
            #Tp cnt = cnt + 1;
1872
          end
1873
          @(posedge Mdc_O);
1874
          // read request
1875
          #Tp mii_read_req(phy_addr, reg_addr);
1876
          check_mii_busy; // wait for read to finish
1877
          // read and check data
1878
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1879
          if (phy_data !== tmp_data)
1880
          begin
1881
            test_fail("Data was not correctly written into OR read from PHY register - control register");
1882
            fail = fail + 1;
1883
          end
1884
        end
1885
        else // read after read
1886
        begin
1887
          // read request
1888
          #Tp mii_read_req(phy_addr, reg_addr);
1889
          // wait for serial bus to become active
1890
          wait(Mdio_IO !== 1'bz);
1891
          // count transfer length
1892
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
1893
          begin
1894
            @(posedge Mdc_O);
1895
            #Tp cnt = cnt + 1;
1896
          end
1897
          @(posedge Mdc_O);
1898
          check_mii_busy; // wait for read to finish
1899
          // read and check data
1900
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1901
          if (phy_data !== tmp_data)
1902
          begin
1903
            test_fail("Data was not correctly written into OR read from PHY register - control register");
1904
            fail = fail + 1;
1905
          end
1906
        end
1907
        // check if transfer was a proper length
1908
        if (i2) // without preamble
1909
        begin
1910
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
1911
          begin
1912
            test_fail("New request did not proceed correctly, after read request");
1913
            fail = fail + 1;
1914
          end
1915
        end
1916
        else // with preamble
1917
        begin
1918
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
1919
          begin
1920
            test_fail("New request did not proceed correctly, after read request");
1921
            fail = fail + 1;
1922
          end
1923
        end
1924
      end
1925
      #Tp;
1926
      // set delay of writing the command
1927
      if (i2) // without preamble
1928
      begin
1929
        case(i)
1930
          0, 1:               i = i + 1;
1931
          18, 19, 20, 21, 22,
1932
          23, 24, 25, 26, 27,
1933
          28, 29, 30, 31, 32,
1934
          33, 34, 35:         i = i + 1;
1935
          36:                 i = 80;
1936
          default:            i = 18;
1937
        endcase
1938
      end
1939
      else // with preamble
1940
      begin
1941
        case(i)
1942
          0, 1:               i = i + 1;
1943
          50, 51, 52, 53, 54,
1944
          55, 56, 57, 58, 59,
1945
          60, 61, 62, 63, 64,
1946
          65, 66, 67:         i = i + 1;
1947
          68:                 i = 80;
1948
          default:            i = 50;
1949
        endcase
1950
      end
1951
      @(posedge wb_clk);
1952
    end
1953
  end
1954
  // set PHY to normal mode
1955
  #Tp eth_phy.preamble_suppresed(0);
1956
  // MII mode register
1957
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1958
  if(fail == 0)
1959
    test_ok;
1960
  else
1961
    fail = 0;
1962
end
1963
 
1964
 
1965
if ((start_task <= 10) && (end_task >= 10))
1966
begin
1967
  // TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
1968
  test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
1969
  `TIME;
1970
  $display("  TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
1971
 
1972
  for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1973
  begin
1974
    #Tp eth_phy.preamble_suppresed(i2);
1975
    // MII mode register
1976
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1977
              wbm_subseq_waits);
1978
    i = 0;
1979
    cnt = 0;
1980
    while (i < 80) // delay for sliding of writing a STOP SCAN command
1981
    begin
1982
      for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after write will be finished
1983
      begin
1984
        // set address
1985
        reg_addr = 5'h0; // control register
1986
        phy_addr = 5'h1; // correct PHY address
1987
        cnt = 0;
1988
        // write request
1989
        phy_data = {8'h75, (i[7:0] + 1)};
1990
        #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1991
        fork
1992
          begin
1993
            repeat(i) @(posedge Mdc_O);
1994
            // write command 0x0 into MII command register
1995
            // MII command written while read in progress
1996
            wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1997
            @(posedge wb_clk);
1998
            #Tp check_mii_busy; // wait for write to finish
1999
          end
2000
          begin
2001
            // wait for serial bus to become active
2002
            wait(Mdio_IO !== 1'bz);
2003
            // count transfer length
2004
            while(Mdio_IO !== 1'bz)
2005
            begin
2006
              @(posedge Mdc_O);
2007
              #Tp cnt = cnt + 1;
2008
            end
2009
          end
2010
        join
2011
        // check transfer length
2012
        if (i2) // without preamble
2013
        begin
2014
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2015
          begin
2016
            test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2017
            fail = fail + 1;
2018
          end
2019
        end
2020
        else // with preamble
2021
        begin
2022
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2023
          begin
2024
            test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2025
            fail = fail + 1;
2026
          end
2027
        end
2028
        // check the BUSY signal to see if the bus is still IDLE
2029
        for (i1 = 0; i1 < 8; i1 = i1 + 1)
2030
          check_mii_busy; // wait for bus to become idle
2031 116 mohor
 
2032 169 mohor
        // try normal write or read after write was finished
2033
        #Tp cnt = 0;
2034
        if (i3 == 0) // write after write
2035
        begin
2036
          phy_data = {8'h7A, (i[7:0] + 1)};
2037
          // write request
2038
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2039
          // wait for serial bus to become active
2040
          wait(Mdio_IO !== 1'bz);
2041
          // count transfer length
2042
          while(Mdio_IO !== 1'bz)
2043
          begin
2044
            @(posedge Mdc_O);
2045
            #Tp cnt = cnt + 1;
2046
          end
2047
          @(posedge Mdc_O);
2048
          // read request
2049
          #Tp mii_read_req(phy_addr, reg_addr);
2050
          check_mii_busy; // wait for read to finish
2051
          // read and check data
2052
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2053
          if (phy_data !== tmp_data)
2054
          begin
2055
            test_fail("Data was not correctly written into OR read from PHY register - control register");
2056
            fail = fail + 1;
2057
          end
2058
        end
2059
        else // read after write
2060
        begin
2061
          // read request
2062
          #Tp mii_read_req(phy_addr, reg_addr);
2063
          // wait for serial bus to become active
2064
          wait(Mdio_IO !== 1'bz);
2065
          // count transfer length
2066
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2067
          begin
2068
            @(posedge Mdc_O);
2069
            #Tp cnt = cnt + 1;
2070
          end
2071
          @(posedge Mdc_O);
2072
          check_mii_busy; // wait for read to finish
2073
          // read and check data
2074
          #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2075
          if (phy_data !== tmp_data)
2076
          begin
2077
            test_fail("Data was not correctly written into OR read from PHY register - control register");
2078
            fail = fail + 1;
2079
          end
2080
        end
2081
        // check if transfer was a proper length
2082
        if (i2) // without preamble
2083
        begin
2084
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2085
          begin
2086
            test_fail("New request did not proceed correctly, after write request");
2087
            fail = fail + 1;
2088
          end
2089
        end
2090
        else // with preamble
2091
        begin
2092
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2093
          begin
2094
            test_fail("New request did not proceed correctly, after write request");
2095
            fail = fail + 1;
2096
          end
2097
        end
2098
      end
2099
      #Tp;
2100
      // set delay of writing the command
2101
      if (i2) // without preamble
2102
      begin
2103
        case(i)
2104
          0, 1:               i = i + 1;
2105
          18, 19, 20, 21, 22,
2106
          23, 24, 25, 26, 27,
2107
          28, 29, 30, 31, 32,
2108
          33, 34, 35:         i = i + 1;
2109
          36:                 i = 80;
2110
          default:            i = 18;
2111
        endcase
2112
      end
2113
      else // with preamble
2114
      begin
2115
        case(i)
2116
          0, 1:               i = i + 1;
2117
          50, 51, 52, 53, 54,
2118
          55, 56, 57, 58, 59,
2119
          60, 61, 62, 63, 64,
2120
          65, 66, 67:         i = i + 1;
2121
          68:                 i = 80;
2122
          default:            i = 50;
2123
        endcase
2124
      end
2125
      @(posedge wb_clk);
2126
    end
2127
  end
2128
  // set PHY to normal mode
2129
  #Tp eth_phy.preamble_suppresed(0);
2130
  // MII mode register
2131
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2132
  if(fail == 0)
2133
    test_ok;
2134
  else
2135
    fail = 0;
2136
end
2137
 
2138
 
2139
if ((start_task <= 11) && (end_task >= 11))
2140
begin
2141
  // TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
2142
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
2143
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
2144
 
2145
  reset_mii; // reset MII
2146
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2147
  #Tp eth_phy.link_up_down(1);
2148
  // set the MII
2149
  clk_div = 64;
2150
  mii_set_clk_div(clk_div[7:0]);
2151
  // set address
2152
  reg_addr = 5'h1; // status register
2153
  phy_addr = 5'h1; // correct PHY address
2154
 
2155
  for (i = 0; i <= 1; i = i + 1)
2156
  begin
2157
    #Tp eth_phy.preamble_suppresed(i);
2158
    // MII mode register
2159
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2160
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2161
    @(posedge Mdc_O);
2162
    // write request
2163
    #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);
2164
    // read data from MII status register - Busy and Nvalid bits
2165
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2166
 
2167
    // check MII IO signal and Busy and Nvalid bits
2168
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2169
    begin
2170
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2171
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2172
      begin
2173
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2174
        fail = fail + 1;
2175
      end
2176
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2177
      begin
2178
        test_fail("Nvalid signal was set during write");
2179
        fail = fail + 1;
2180
      end
2181
    end
2182
    else // Busy bit should already be set to '1', due to reads from MII status register
2183
    begin
2184
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2185
      begin
2186
        test_fail("Busy signal should be set after write, due to reads from MII status register");
2187
        fail = fail + 1;
2188
      end
2189
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2190
      begin
2191
        test_fail("Nvalid signal was set during write");
2192
        fail = fail + 1;
2193
      end
2194
    end
2195
 
2196
    // wait for serial bus to become active
2197
    wait(Mdio_IO !== 1'bz);
2198
    // count transfer bits
2199
    if (i)
2200
    begin
2201
      repeat(32) @(posedge Mdc_O);
2202
    end
2203 116 mohor
    else
2204 169 mohor
    begin
2205
      repeat(64) @(posedge Mdc_O);
2206
    end
2207
    // read data from MII status register - Busy and Nvalid bits
2208
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2209 116 mohor
 
2210 169 mohor
    // check MII IO signal and Busy and Nvalid bits
2211
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2212
    begin
2213
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2214
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2215
      begin
2216
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2217
        fail = fail + 1;
2218
      end
2219
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2220
      begin
2221
        test_fail("Nvalid signal was set during write");
2222
        fail = fail + 1;
2223
      end
2224
    end
2225
    else // Busy bit should still be set to '1'
2226
    begin
2227
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2228
      begin
2229
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2230
        fail = fail + 1;
2231
      end
2232
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2233
      begin
2234
        test_fail("Nvalid signal was set during write");
2235
        fail = fail + 1;
2236
      end
2237
    end
2238
 
2239
    // wait for next negative clock edge
2240
    @(negedge Mdc_O);
2241
    // read data from MII status register - Busy and Nvalid bits
2242
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2243
 
2244
    // check MII IO signal and Busy and Nvalid bits
2245
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2246
    begin
2247
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2248
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2249
      begin
2250
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2251
        fail = fail + 1;
2252
      end
2253
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2254
      begin
2255
        test_fail("Nvalid signal was set during write");
2256
        fail = fail + 1;
2257
      end
2258
    end
2259
    else // Busy bit should still be set to '1'
2260
    begin
2261
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2262
      begin
2263
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2264
        fail = fail + 1;
2265
      end
2266
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2267
      begin
2268
        test_fail("Nvalid signal was set during write");
2269
        fail = fail + 1;
2270
      end
2271
    end
2272
 
2273
    // wait for Busy to become inactive
2274
    i1 = 0;
2275
    while (i1 <= 2)
2276
    begin
2277
      // wait for next positive clock edge
2278
      @(posedge Mdc_O);
2279
      // read data from MII status register - Busy and Nvalid bits
2280
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2281
 
2282
      // check MII IO signal and Busy and Nvalid bits
2283
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2284
      begin
2285
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2286
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2287
        begin
2288
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2289
          fail = fail + 1;
2290
        end
2291
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2292
        begin
2293
          test_fail("Nvalid signal was set during write");
2294
          fail = fail + 1;
2295
        end
2296
      end
2297
      else // wait for Busy bit to be set to '0'
2298
      begin
2299
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2300
        begin
2301
          i1 = 3; // end of Busy checking
2302
        end
2303
        else
2304
        begin
2305
          if (i1 == 2)
2306
          begin
2307
            test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2308
            fail = fail + 1;
2309
          end
2310
          #Tp i1 = i1 + 1;
2311
        end
2312
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2313
        begin
2314
          test_fail("Nvalid signal was set after write");
2315
          fail = fail + 1;
2316
        end
2317
      end
2318
    end
2319 116 mohor
  end
2320 169 mohor
  // set PHY to normal mode
2321
  #Tp eth_phy.preamble_suppresed(0);
2322
  // MII mode register
2323
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2324
  if(fail == 0)
2325
    test_ok;
2326
  else
2327
    fail = 0;
2328
end
2329 116 mohor
 
2330
 
2331 169 mohor
if ((start_task <= 12) && (end_task >= 12))
2332
begin
2333
  // TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
2334
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
2335
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
2336 116 mohor
 
2337 169 mohor
  reset_mii; // reset MII
2338
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2339
  #Tp eth_phy.link_up_down(1);
2340
  // set the MII
2341
  clk_div = 64;
2342
  mii_set_clk_div(clk_div[7:0]);
2343
  // set address
2344
  reg_addr = 5'h1; // status register
2345
  phy_addr = 5'h1; // correct PHY address
2346
 
2347
  for (i = 0; i <= 1; i = i + 1)
2348
  begin
2349
    #Tp eth_phy.preamble_suppresed(i);
2350
    // MII mode register
2351
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2352
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2353
    @(posedge Mdc_O);
2354
    // read request
2355
    #Tp mii_read_req(phy_addr, reg_addr);
2356
    // read data from MII status register - Busy and Nvalid bits
2357
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2358
 
2359
    // check MII IO signal and Busy and Nvalid bits
2360
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2361
    begin
2362
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2363
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2364
      begin
2365
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2366
        fail = fail + 1;
2367
      end
2368
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2369
      begin
2370
        test_fail("Nvalid signal was set during read");
2371
        fail = fail + 1;
2372
      end
2373
    end
2374
    else // Busy bit should already be set to '1', due to reads from MII status register
2375
    begin
2376
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2377
      begin
2378
        test_fail("Busy signal should be set after read, due to reads from MII status register");
2379
        fail = fail + 1;
2380
      end
2381
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2382
      begin
2383
        test_fail("Nvalid signal was set during read");
2384
        fail = fail + 1;
2385
      end
2386
    end
2387
 
2388
    // wait for serial bus to become active
2389
    wait(Mdio_IO !== 1'bz);
2390
    // count transfer bits
2391
    if (i)
2392
    begin
2393
      repeat(31) @(posedge Mdc_O);
2394
    end
2395
    else
2396
    begin
2397
      repeat(63) @(posedge Mdc_O);
2398
    end
2399
    // wait for next negative clock edge
2400
    @(negedge Mdc_O);
2401
    // read data from MII status register - Busy and Nvalid bits
2402
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2403
 
2404
    // check MII IO signal and Busy and Nvalid bits
2405
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2406
    begin
2407
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2408
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2409
      begin
2410
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2411
        fail = fail + 1;
2412
      end
2413
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2414
      begin
2415
        test_fail("Nvalid signal was set during read");
2416
        fail = fail + 1;
2417
      end
2418
    end
2419
    else // Busy bit should still be set to '1'
2420
    begin
2421
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2422
      begin
2423
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2424
        fail = fail + 1;
2425
      end
2426
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2427
      begin
2428
        test_fail("Nvalid signal was set during read");
2429
        fail = fail + 1;
2430
      end
2431
    end
2432
 
2433
    // wait for next positive clock edge
2434
    @(posedge Mdc_O);
2435
    // read data from MII status register - Busy and Nvalid bits
2436
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2437
 
2438
    // check MII IO signal and Busy and Nvalid bits
2439
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2440
    begin
2441
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2442
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2443
      begin
2444
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2445
        fail = fail + 1;
2446
      end
2447
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2448
      begin
2449
        test_fail("Nvalid signal was set during read");
2450
        fail = fail + 1;
2451
      end
2452
    end
2453
    else // Busy bit should still be set to '1'
2454
    begin
2455
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2456
      begin
2457
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2458
        fail = fail + 1;
2459
      end
2460
      if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2461
      begin
2462
        test_fail("Nvalid signal was set during read");
2463
        fail = fail + 1;
2464
      end
2465
    end
2466
 
2467
    // wait for Busy to become inactive
2468
    i1 = 0;
2469
    while (i1 <= 2)
2470
    begin
2471
      // wait for next positive clock edge
2472
      @(posedge Mdc_O);
2473
      // read data from MII status register - Busy and Nvalid bits
2474
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2475
 
2476
      // check MII IO signal and Busy and Nvalid bits
2477
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2478
      begin
2479
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2480
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2481
        begin
2482
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2483
          fail = fail + 1;
2484
        end
2485
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2486
        begin
2487
          test_fail("Nvalid signal was set during read");
2488
          fail = fail + 1;
2489
        end
2490
      end
2491
      else // wait for Busy bit to be set to '0'
2492
      begin
2493
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2494
        begin
2495
          i1 = 3; // end of Busy checking
2496
        end
2497
        else
2498
        begin
2499
          if (i1 == 2)
2500
          begin
2501
            test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2502
            fail = fail + 1;
2503
          end
2504
          #Tp i1 = i1 + 1;
2505
        end
2506
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2507
        begin
2508
          test_fail("Nvalid signal was set after read");
2509
          fail = fail + 1;
2510
        end
2511
      end
2512
    end
2513
  end
2514
  // set PHY to normal mode
2515
  #Tp eth_phy.preamble_suppresed(0);
2516
  // MII mode register
2517
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2518
  if(fail == 0)
2519
    test_ok;
2520
  else
2521
    fail = 0;
2522
end
2523
 
2524
 
2525
if ((start_task <= 13) && (end_task >= 13))
2526
begin
2527
  // TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
2528
  test_name   = "TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
2529
  `TIME; $display("  TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
2530
 
2531
  reset_mii; // reset MII
2532
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2533
  #Tp eth_phy.link_up_down(1);
2534
  // set the MII
2535
  clk_div = 64;
2536
  mii_set_clk_div(clk_div[7:0]);
2537
  // set address
2538
  reg_addr = 5'h1; // status register
2539
  phy_addr = 5'h1; // correct PHY address
2540
 
2541
  for (i = 0; i <= 1; i = i + 1)
2542
  begin
2543
    #Tp eth_phy.preamble_suppresed(i);
2544
    // MII mode register
2545
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2546
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2547
    @(posedge Mdc_O);
2548
    // scan request
2549
    #Tp mii_scan_req(phy_addr, reg_addr);
2550
    // read data from MII status register - Busy and Nvalid bits
2551
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2552
 
2553
    // check MII IO signal and Busy and Nvalid bits
2554
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2555
    begin
2556
      test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2557
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2558
      begin
2559
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2560
        fail = fail + 1;
2561
      end
2562
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2563
      begin
2564
        test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2565
        fail = fail + 1;
2566
      end
2567
    end
2568
    else // Busy bit should already be set to '1', due to reads from MII status register
2569
    begin
2570
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2571
      begin
2572
        test_fail("Busy signal should be set after scan, due to reads from MII status register");
2573
        fail = fail + 1;
2574
      end
2575
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2576
      begin
2577
        test_fail("Nvalid signal should be set after scan, due to reads from MII status register");
2578
        fail = fail + 1;
2579
      end
2580
    end
2581
 
2582
    // wait for serial bus to become active
2583
    wait(Mdio_IO !== 1'bz);
2584
    // count transfer bits
2585
    if (i)
2586
    begin
2587
      repeat(21) @(posedge Mdc_O);
2588
    end
2589
    else
2590
    begin
2591
      repeat(53) @(posedge Mdc_O);
2592
    end
2593
    // stop scan
2594
    #Tp mii_scan_finish; // finish scan operation
2595
 
2596
    // wait for next positive clock edge
2597
    repeat(10) @(posedge Mdc_O);
2598
    // read data from MII status register - Busy and Nvalid bits
2599
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2600
 
2601
    // check MII IO signal and Busy and Nvalid bits
2602
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2603
    begin
2604
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2605
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2606
      begin
2607
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2608
        fail = fail + 1;
2609
      end
2610
      // Nvalid signal can be cleared here - it is still Testbench error
2611
    end
2612
    else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2613
    begin
2614
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2615
      begin
2616
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2617
        fail = fail + 1;
2618
      end
2619
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2620
      begin
2621
        test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2622
        fail = fail + 1;
2623
      end
2624
    end
2625
 
2626
    // wait for next negative clock edge
2627
    @(negedge Mdc_O);
2628
    // read data from MII status register - Busy and Nvalid bits
2629
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2630
 
2631
    // check MII IO signal and Busy and Nvalid bits
2632
    if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2633
    begin
2634
      test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2635
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2636
      begin
2637
        test_fail("Busy signal should be set while MII IO signal is not active anymore");
2638
        fail = fail + 1;
2639
      end
2640
      // Nvalid signal can be cleared here - it is still Testbench error
2641
    end
2642
    else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2643
    begin
2644
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2645
      begin
2646
        test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2647
        fail = fail + 1;
2648
      end
2649
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2650
      begin
2651
        test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2652
        fail = fail + 1;
2653
      end
2654
    end
2655
 
2656
    // wait for next negative clock edge
2657
    @(posedge Mdc_O);
2658
    // read data from MII status register - Busy and Nvalid bits
2659
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2660
 
2661
    // check MII IO signal and Busy and Nvalid bits
2662
    if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2663
    begin
2664
      test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2665
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2666
      begin
2667
        test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2668
        fail = fail + 1;
2669
      end
2670
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2671
      begin
2672
        test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2673
        fail = fail + 1;
2674
      end
2675
    end
2676
    else // Busy bit should still be set to '1', Nvalid bit can be set to '0'
2677
    begin
2678
      if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2679
      begin
2680
        test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2681
        fail = fail + 1;
2682
      end
2683
      if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2684
      begin
2685
        i2 = 1; // check finished
2686
      end
2687
      else
2688
      begin
2689
        i2 = 0; // check must continue
2690
      end
2691
    end
2692
 
2693
    // wait for Busy to become inactive
2694
    i1 = 0;
2695
    while ((i1 <= 2) || (i2 == 0))
2696
    begin
2697
      // wait for next positive clock edge
2698
      @(posedge Mdc_O);
2699
      // read data from MII status register - Busy and Nvalid bits
2700
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2701
 
2702
      // check MII IO signal and Busy and Nvalid bits
2703
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2704
      begin
2705
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2706
        if (i1 <= 2)
2707
        begin
2708
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2709
          begin
2710
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2711
            fail = fail + 1;
2712
          end
2713
        end
2714
        if (i2 == 0)
2715
        begin
2716
          if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2717
          begin
2718
            test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2719
            fail = fail + 1;
2720
          end
2721
        end
2722
      end
2723
      else // wait for Busy bit to be set to '0'
2724
      begin
2725
        if (i1 <= 2)
2726
        begin
2727
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2728
          begin
2729
            i1 = 3; // end of Busy checking
2730
          end
2731
          else
2732
          begin
2733
            if (i1 == 2)
2734
            begin
2735
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2736
              fail = fail + 1;
2737
            end
2738
            #Tp i1 = i1 + 1;
2739
          end
2740
        end
2741
        if (i2 == 0)
2742
        begin
2743
          if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2744
          begin
2745
            i2 = 1;
2746
          end
2747
          else
2748
          begin
2749
            test_fail("Nvalid signal should be cleared after MII IO signal become HIGH Z");
2750
            fail = fail + 1;
2751
          end
2752
        end
2753
      end
2754
    end
2755
  end
2756
  // set PHY to normal mode
2757
  #Tp eth_phy.preamble_suppresed(0);
2758
  // MII mode register
2759
  wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2760
  if(fail == 0)
2761
    test_ok;
2762
  else
2763
    fail = 0;
2764
end
2765
 
2766
 
2767
if ((start_task <= 14) && (end_task >= 14))
2768
begin
2769
  // TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
2770
  test_name   = "TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
2771
  `TIME; $display("  TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
2772
 
2773
  reset_mii; // reset MII
2774
  // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2775
  #Tp eth_phy.link_up_down(1);
2776
  // set MII speed
2777
  clk_div = 6;
2778
  mii_set_clk_div(clk_div[7:0]);
2779
  // set address
2780
  reg_addr = 5'h1; // status register
2781
  phy_addr = 5'h1; // correct PHY address
2782
 
2783
  // read request
2784
  #Tp mii_read_req(phy_addr, reg_addr);
2785
  check_mii_busy; // wait for read to finish
2786
  // read data from PHY status register - remember LINK-UP status
2787
  #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2788
 
2789
  for (i = 0; i <= 1; i = i + 1)
2790
  begin
2791
    #Tp eth_phy.preamble_suppresed(i);
2792
    // MII mode register
2793
    wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2794
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2795
    if (i)
2796
    begin
2797
      // change saved data when preamble is suppressed
2798
      #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
2799
    end
2800
 
2801
    // scan request
2802
    #Tp mii_scan_req(phy_addr, reg_addr);
2803
    check_mii_scan_valid; // wait for scan to make first data valid
2804
 
2805
    fork
2806
    begin
2807
      repeat(2) @(posedge Mdc_O);
2808
      // read data from PHY status register
2809
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2810
      if (phy_data !== tmp_data)
2811
      begin
2812
        test_fail("Data was not correctly scaned from status register");
2813
        fail = fail + 1;
2814
      end
2815
      // read data from MII status register
2816
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2817
      if (phy_data[0] !== 1'b0)
2818
      begin
2819
        test_fail("Link FAIL bit was set in the MII status register");
2820
        fail = fail + 1;
2821
      end
2822
    end
2823
    begin
2824
    // Completely check second scan
2825
      #Tp cnt = 0;
2826
      // wait for serial bus to become active - second scan
2827
      wait(Mdio_IO !== 1'bz);
2828
      // count transfer length
2829
      while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
2830
      begin
2831
        @(posedge Mdc_O);
2832
        #Tp cnt = cnt + 1;
2833
      end
2834
      // check transfer length
2835
      if (i) // without preamble
2836
      begin
2837
        if (cnt != 33) // at this value Mdio_IO is HIGH Z
2838
        begin
2839
          test_fail("Second scan request did not proceed correctly");
2840
          fail = fail + 1;
2841
        end
2842
      end
2843
      else // with preamble
2844
      begin
2845
        if (cnt != 65) // at this value Mdio_IO is HIGH Z
2846
        begin
2847
          test_fail("Second scan request did not proceed correctly");
2848
          fail = fail + 1;
2849
        end
2850
      end
2851
    end
2852
    join
2853
    // check third to fifth scans
2854
    for (i3 = 0; i3 <= 2; i3 = i3 + 1)
2855
    begin
2856
      fork
2857
      begin
2858
        repeat(2) @(posedge Mdc_O);
2859
        // read data from PHY status register
2860
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2861
        if (phy_data !== tmp_data)
2862
        begin
2863
          test_fail("Data was not correctly scaned from status register");
2864
          fail = fail + 1;
2865
        end
2866
        // read data from MII status register
2867
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2868
        if (phy_data[0] !== 1'b0)
2869
        begin
2870
          test_fail("Link FAIL bit was set in the MII status register");
2871
          fail = fail + 1;
2872
        end
2873
        if (i3 == 2) // after fourth scan read
2874
        begin
2875
          @(posedge Mdc_O);
2876
          // change saved data
2877
          #Tp tmp_data = tmp_data & 16'hFFFB; // put bit 3 to ZERO
2878
          // set link down
2879
          #Tp eth_phy.link_up_down(0);
2880
        end
2881
      end
2882
      begin
2883
      // Completely check scans
2884
        #Tp cnt = 0;
2885
        // wait for serial bus to become active - second scan
2886
        wait(Mdio_IO !== 1'bz);
2887
        // count transfer length
2888
        while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
2889
        begin
2890
          @(posedge Mdc_O);
2891
          #Tp cnt = cnt + 1;
2892
        end
2893
        // check transfer length
2894
        if (i) // without preamble
2895
        begin
2896
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
2897
          begin
2898
            test_fail("Fifth scan request did not proceed correctly");
2899
            fail = fail + 1;
2900
          end
2901
        end
2902
        else // with preamble
2903
        begin
2904
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
2905
          begin
2906
            test_fail("Fifth scan request did not proceed correctly");
2907
            fail = fail + 1;
2908
          end
2909
        end
2910
      end
2911
      join
2912
    end
2913
 
2914
    fork
2915
    begin
2916
      repeat(2) @(posedge Mdc_O);
2917
      // read data from PHY status register
2918
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2919
      if (phy_data !== tmp_data)
2920
      begin
2921
        test_fail("Data was not correctly scaned from status register");
2922
        fail = fail + 1;
2923
      end
2924
      // read data from MII status register
2925
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2926
      if (phy_data[0] === 1'b0)
2927
      begin
2928
        test_fail("Link FAIL bit was not set in the MII status register");
2929
        fail = fail + 1;
2930
      end
2931
      // wait to see if data stayed latched
2932
      repeat(4) @(posedge Mdc_O);
2933
      // read data from PHY status register
2934
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2935
      if (phy_data !== tmp_data)
2936
      begin
2937
        test_fail("Data was not latched correctly in status register");
2938
        fail = fail + 1;
2939
      end
2940
      // read data from MII status register
2941
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2942
      if (phy_data[0] === 1'b0)
2943
      begin
2944
        test_fail("Link FAIL bit was not set in the MII status register");
2945
        fail = fail + 1;
2946
      end
2947
      // change saved data
2948
      #Tp tmp_data = tmp_data | 16'h0004; // put bit 2 to ONE
2949
      // set link up
2950
      #Tp eth_phy.link_up_down(1);
2951
    end
2952
    begin
2953
    // Wait for sixth scan
2954
      // wait for serial bus to become active - sixth scan
2955
      wait(Mdio_IO !== 1'bz);
2956
      // wait for serial bus to become inactive - turn-around cycle in sixth scan
2957
      wait(Mdio_IO === 1'bz);
2958
      // wait for serial bus to become active - end of turn-around cycle in sixth scan
2959
      wait(Mdio_IO !== 1'bz);
2960
      // wait for serial bus to become inactive - end of sixth scan
2961
      wait(Mdio_IO === 1'bz);
2962
    end
2963
    join
2964
 
2965
    @(posedge Mdc_O);
2966
    // read data from PHY status register
2967
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2968
    if (phy_data !== tmp_data)
2969
    begin
2970
      test_fail("Data was not correctly scaned from status register");
2971
      fail = fail + 1;
2972
    end
2973
    // read data from MII status register
2974
    #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2975
    if (phy_data[0] !== 1'b0)
2976
    begin
2977
      test_fail("Link FAIL bit was set in the MII status register");
2978