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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Blame information for rev 281

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1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet.v                                               ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 169 mohor
////      - Tadej Markovic, tadej@opencores.org                   ////
10 243 tadejm
////      - Igor Mohor,     igorM@opencores.org                  ////
11 116 mohor
////                                                              ////
12 169 mohor
////  All additional information is available in the Readme.txt   ////
13 116 mohor
////  file.                                                       ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2001, 2002 Authors                             ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 281 mohor
// Revision 1.27  2003/01/30 13:38:15  mohor
46
// Underrun test fixed. Many other tests fixed.
47
//
48 279 mohor
// Revision 1.26  2003/01/22 19:40:10  tadejm
49
// Backup version. Not fully working.
50
//
51 274 tadejm
// Revision 1.25  2002/11/27 16:21:55  mohor
52
// Full duplex control frames tested.
53
//
54 267 mohor
// Revision 1.24  2002/11/22 17:29:42  mohor
55
// Flow control test almost finished.
56
//
57 266 mohor
// Revision 1.23  2002/11/22 02:12:16  mohor
58
// test_mac_full_duplex_flow_control tests pretty much finished.
59
// TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
60
// FRM. AT 4 TX BD ( 10Mbps ) finished.
61
// TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
62
// TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
63
//
64 263 mohor
// Revision 1.22  2002/11/21 13:56:50  mohor
65
// test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
66
// finished.
67
//
68 260 mohor
// Revision 1.21  2002/11/19 20:27:45  mohor
69
// Temp version.
70
//
71 254 mohor
// Revision 1.20  2002/11/19 17:41:19  tadejm
72
// Just some updates.
73
//
74 252 tadejm
// Revision 1.19  2002/11/14 13:12:47  tadejm
75
// Late collision is not reported any more.
76
//
77 243 tadejm
// Revision 1.18  2002/10/18 17:03:34  tadejm
78
// Changed BIST scan signals.
79
//
80 227 tadejm
// Revision 1.17  2002/10/18 13:58:22  tadejm
81
// Some code changed due to bug fixes.
82
//
83 223 tadejm
// Revision 1.16  2002/10/09 13:16:51  tadejm
84
// Just back-up; not completed testbench and some testcases are not
85
// wotking properly yet.
86
//
87 209 tadejm
// Revision 1.15  2002/09/20 14:29:12  tadej
88
// Full duplex tests modified and testbench bug repaired.
89
//
90 194 tadej
// Revision 1.14  2002/09/18 17:56:38  tadej
91
// Some additional reports added
92
//
93 192 tadej
// Revision 1.13  2002/09/16 17:53:49  tadej
94
// Full duplex test improved.
95
//
96 182 tadej
// Revision 1.12  2002/09/16 15:10:42  mohor
97
// MIIM test look better.
98
//
99 181 mohor
// Revision 1.11  2002/09/13 19:18:04  mohor
100
// Bench outputs data to display every 128 bytes.
101
//
102 180 mohor
// Revision 1.10  2002/09/13 18:44:29  mohor
103
// Beautiful tests merget together
104
//
105 179 mohor
// Revision 1.9  2002/09/13 18:41:45  mohor
106
// Rearanged testcases
107
//
108 178 mohor
// Revision 1.8  2002/09/13 14:50:15  mohor
109
// Bug in MIIM fixed.
110
//
111 177 mohor
// Revision 1.7  2002/09/13 12:29:14  mohor
112
// Headers changed.
113
//
114 170 mohor
// Revision 1.6  2002/09/13 11:57:20  mohor
115
// New testbench. Thanks to Tadej M - "The Spammer".
116
//
117 121 mohor
// Revision 1.2  2002/07/19 14:02:47  mohor
118
// Clock mrx_clk set to 2.5 MHz.
119
//
120 117 mohor
// Revision 1.1  2002/07/19 13:57:53  mohor
121
// Testing environment also includes traffic cop, memory interface and host
122
// interface.
123 116 mohor
//
124
//
125
//
126
//
127 117 mohor
//
128 116 mohor
 
129
 
130 169 mohor
`include "eth_phy_defines.v"
131
`include "wb_model_defines.v"
132 116 mohor
`include "tb_eth_defines.v"
133
`include "eth_defines.v"
134
`include "timescale.v"
135
 
136
module tb_ethernet();
137
 
138
 
139 169 mohor
reg           wb_clk;
140
reg           wb_rst;
141
wire          wb_int;
142 116 mohor
 
143 169 mohor
wire          mtx_clk;  // This goes to PHY
144
wire          mrx_clk;  // This goes to PHY
145 116 mohor
 
146
wire   [3:0]  MTxD;
147
wire          MTxEn;
148
wire          MTxErr;
149
 
150 169 mohor
wire   [3:0]  MRxD;     // This goes to PHY
151
wire          MRxDV;    // This goes to PHY
152
wire          MRxErr;   // This goes to PHY
153
wire          MColl;    // This goes to PHY
154
wire          MCrs;     // This goes to PHY
155 116 mohor
 
156
wire          Mdi_I;
157
wire          Mdo_O;
158
wire          Mdo_OE;
159 169 mohor
tri           Mdio_IO;
160 116 mohor
wire          Mdc_O;
161
 
162
 
163 169 mohor
parameter Tp = 1;
164 116 mohor
 
165 121 mohor
 
166 116 mohor
// Ethernet Slave Interface signals
167 169 mohor
wire [31:0] eth_sl_wb_adr;
168 116 mohor
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
169
wire  [3:0] eth_sl_wb_sel_i;
170
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
171
 
172
// Ethernet Master Interface signals
173
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
174
wire  [3:0] eth_ma_wb_sel_o;
175
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
176
 
177
 
178
 
179
 
180
// Connecting Ethernet top module
181 169 mohor
eth_top eth_top
182 116 mohor
(
183
  // WISHBONE common
184 169 mohor
  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),
185 116 mohor
 
186
  // WISHBONE slave
187 169 mohor
  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
188
  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
189
  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
190 116 mohor
 
191
  // WISHBONE master
192
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
193
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
194
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
195
 
196
  //TX
197
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
198
 
199
  //RX
200
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
201
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
202
 
203
  // MIIM
204
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
205
 
206 169 mohor
  .int_o(wb_int)
207 227 tadejm
 
208
  // Bist
209
`ifdef ETH_BIST
210
  ,
211
  .scanb_rst      (1'b0),
212
  .scanb_clk      (1'b0),
213
  .scanb_si       (1'b0),
214
  .scanb_so       (),
215
  .scanb_en       (1'b0)
216
`endif
217 116 mohor
);
218
 
219
 
220
 
221 169 mohor
// Connecting Ethernet PHY Module
222
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
223
assign Mdi_I   = Mdio_IO;
224
integer phy_log_file_desc;
225
 
226
eth_phy eth_phy
227 116 mohor
(
228 169 mohor
  // WISHBONE reset
229
  .m_rst_n_i(!wb_rst),
230 116 mohor
 
231 169 mohor
  // MAC TX
232
  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),
233
 
234
  // MAC RX
235
  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),
236
  .mcoll_o(MColl),        .mcrs_o(MCrs),
237
 
238
  // MIIM
239
  .mdc_i(Mdc_O),          .md_io(Mdio_IO),
240
 
241
  // SYSTEM
242
  .phy_log(phy_log_file_desc)
243 116 mohor
);
244
 
245
 
246 169 mohor
 
247
// Connecting WB Master as Host Interface
248
integer host_log_file_desc;
249
 
250
WB_MASTER_BEHAVIORAL wb_master
251 116 mohor
(
252 169 mohor
    .CLK_I(wb_clk),
253
    .RST_I(wb_rst),
254
    .TAG_I({`WB_TAG_WIDTH{1'b0}}),
255
    .TAG_O(),
256
    .ACK_I(eth_sl_wb_ack_o),
257
    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
258
    .CYC_O(eth_sl_wb_cyc_i),
259
    .DAT_I(eth_sl_wb_dat_o),
260
    .DAT_O(eth_sl_wb_dat_i),
261
    .ERR_I(eth_sl_wb_err_o),
262
    .RTY_I(1'b0),  // inactive (1'b0)
263
    .SEL_O(eth_sl_wb_sel_i),
264
    .STB_O(eth_sl_wb_stb_i),
265
    .WE_O (eth_sl_wb_we_i),
266
    .CAB_O()       // NOT USED for now!
267
);
268
 
269
assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
270
 
271
 
272
 
273
// Connecting WB Slave as Memory Interface Module
274
integer memory_log_file_desc;
275
 
276
WB_SLAVE_BEHAVIORAL wb_slave
277
(
278
    .CLK_I(wb_clk),
279
    .RST_I(wb_rst),
280
    .ACK_O(eth_ma_wb_ack_i),
281
    .ADR_I(eth_ma_wb_adr_o),
282
    .CYC_I(eth_ma_wb_cyc_o),
283
    .DAT_O(eth_ma_wb_dat_i),
284
    .DAT_I(eth_ma_wb_dat_o),
285
    .ERR_O(eth_ma_wb_err_i),
286
    .RTY_O(),      // NOT USED for now!
287
    .SEL_I(eth_ma_wb_sel_o),
288
    .STB_I(eth_ma_wb_stb_o),
289
    .WE_I (eth_ma_wb_we_o),
290
    .CAB_I(1'b0)   // inactive (1'b0)
291
);
292
 
293
 
294
 
295
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
296
integer wb_s_mon_log_file_desc ;
297
integer wb_m_mon_log_file_desc ;
298
 
299
WB_BUS_MON wb_eth_slave_bus_mon
300
(
301 116 mohor
  // WISHBONE common
302 169 mohor
  .CLK_I(wb_clk),
303
  .RST_I(wb_rst),
304 116 mohor
 
305 169 mohor
  // WISHBONE slave
306
  .ACK_I(eth_sl_wb_ack_o),
307
  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),
308
  .CYC_O(eth_sl_wb_cyc_i),
309
  .DAT_I(eth_sl_wb_dat_o),
310
  .DAT_O(eth_sl_wb_dat_i),
311
  .ERR_I(eth_sl_wb_err_o),
312
  .RTY_I(1'b0),
313
  .SEL_O(eth_sl_wb_sel_i),
314
  .STB_O(eth_sl_wb_stb_i),
315
  .WE_O (eth_sl_wb_we_i),
316
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
317
  .TAG_O(),
318
  .CAB_O(1'b0),
319
  .log_file_desc (wb_s_mon_log_file_desc)
320
);
321
 
322
WB_BUS_MON wb_eth_master_bus_mon
323
(
324
  // WISHBONE common
325
  .CLK_I(wb_clk),
326
  .RST_I(wb_rst),
327
 
328 116 mohor
  // WISHBONE master
329 169 mohor
  .ACK_I(eth_ma_wb_ack_i),
330
  .ADDR_O(eth_ma_wb_adr_o),
331
  .CYC_O(eth_ma_wb_cyc_o),
332
  .DAT_I(eth_ma_wb_dat_i),
333
  .DAT_O(eth_ma_wb_dat_o),
334
  .ERR_I(eth_ma_wb_err_i),
335
  .RTY_I(1'b0),
336
  .SEL_O(eth_ma_wb_sel_o),
337
  .STB_O(eth_ma_wb_stb_o),
338
  .WE_O (eth_ma_wb_we_o),
339
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
340
  .TAG_O(),
341
  .CAB_O(1'b0),
342
  .log_file_desc(wb_m_mon_log_file_desc)
343 116 mohor
);
344
 
345
 
346
 
347 169 mohor
reg         StartTB;
348
integer     tb_log_file;
349 116 mohor
 
350 169 mohor
initial
351
begin
352
  tb_log_file = $fopen("../log/eth_tb.log");
353
  if (tb_log_file < 2)
354
  begin
355
    $display("*E Could not open/create testbench log file in ../log/ directory!");
356
    $finish;
357
  end
358
  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");
359
  $fdisplay(tb_log_file, " ");
360 116 mohor
 
361 169 mohor
  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");
362
  if (phy_log_file_desc < 2)
363
  begin
364
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");
365
    $finish;
366
  end
367
  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");
368
  $fdisplay(phy_log_file_desc, " ");
369
 
370
  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");
371
  if (memory_log_file_desc < 2)
372
  begin
373
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");
374
    $finish;
375
  end
376
  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");
377
  $fdisplay(memory_log_file_desc, " ");
378
 
379
  host_log_file_desc = $fopen("../log/eth_tb_host.log");
380
  if (host_log_file_desc < 2)
381
  begin
382
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");
383
    $finish;
384
  end
385
  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");
386
  $fdisplay(host_log_file_desc, " ");
387
 
388
  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");
389
  if (wb_s_mon_log_file_desc < 2)
390
  begin
391
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");
392
    $finish;
393
  end
394
  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");
395
  $fdisplay(wb_s_mon_log_file_desc, " ");
396
  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
397
  $fdisplay(wb_s_mon_log_file_desc, " ");
398
 
399
  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");
400
  if (wb_m_mon_log_file_desc < 2)
401
  begin
402
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");
403
    $finish;
404
  end
405
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
406
  $fdisplay(wb_m_mon_log_file_desc, " ");
407
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
408
  $fdisplay(wb_m_mon_log_file_desc, " ");
409
 
410 243 tadejm
  // Reset pulse
411
  wb_rst =  1'b1;
412
  #423 wb_rst =  1'b0;
413
 
414 169 mohor
  // Clear memories
415
  clear_memories;
416 243 tadejm
  clear_buffer_descriptors;
417 169 mohor
 
418
  #423 StartTB  =  1'b1;
419
end
420
 
421
 
422
 
423
// Generating wb_clk clock
424 116 mohor
initial
425
begin
426 169 mohor
  wb_clk=0;
427
//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    
428 274 tadejm
//  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    
429 169 mohor
//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    
430
//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    
431 274 tadejm
  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    
432 209 tadejm
//  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    
433 169 mohor
//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz
434
//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    
435
//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz
436
//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    
437 116 mohor
end
438
 
439
 
440
 
441 169 mohor
integer      tests_successfull;
442
integer      tests_failed;
443
reg [799:0]  test_name; // used for tb_log_file
444 121 mohor
 
445 169 mohor
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
446
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
447
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
448
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
449
 
450 274 tadejm
reg          wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working
451
 
452
 
453 116 mohor
initial
454
begin
455 169 mohor
  wait(StartTB);  // Start of testbench
456
 
457
  // Initial global values
458
  tests_successfull = 0;
459
  tests_failed = 0;
460 274 tadejm
 
461
  wbm_working = 0;
462 169 mohor
 
463
  wbm_init_waits = 4'h1;
464
  wbm_subseq_waits = 4'h3;
465
  wbs_waits = 4'h1;
466
  wbs_retries = 8'h2;
467
  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
468
 
469 274 tadejm
  // set DIFFERENT mrx_clk to mtx_clk!
470
//  eth_phy.set_mrx_equal_mtx = 1'b0;
471 169 mohor
 
472
  //  Call tests
473
  //  ----------
474 274 tadejm
//    test_access_to_mac_reg(0, 0);           // 0 - 3
475 194 tadej
//    test_mii(0, 17);                        // 0 - 17
476 169 mohor
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
477
  eth_phy.carrier_sense_real_delay(0);
478 279 mohor
    test_mac_full_duplex_transmit(0, 21);    // 0 - (21)
479 281 mohor
    test_mac_full_duplex_receive(0, 13);     // 0 - 13
480
    test_mac_full_duplex_flow_control(0, 4);  // 0 - 4
481 274 tadejm
                                              // 4 is executed, everything is OK
482
//    test_mac_half_duplex_flow(0, 0);
483 169 mohor
 
484 243 tadejm
  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
485 169 mohor
  eth_phy.carrier_sense_real_delay(1);
486
 
487
 
488
  // Finish test's logs
489
  test_summary;
490
  $display("\n\n END of SIMULATION");
491
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
492
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);
493
 
494
  $stop;
495 116 mohor
end
496 169 mohor
 
497 116 mohor
 
498 169 mohor
 
499
//////////////////////////////////////////////////////////////
500
// Test tasks
501
//////////////////////////////////////////////////////////////
502
 
503
task test_access_to_mac_reg;
504
  input  [31:0]  start_task;
505
  input  [31:0]  end_task;
506
  integer        bit_start_1;
507
  integer        bit_end_1;
508
  integer        bit_start_2;
509
  integer        bit_end_2;
510
  integer        num_of_reg;
511
  integer        i_addr;
512
  integer        i_data;
513
  integer        i_length;
514
  integer        tmp_data;
515
  reg    [31:0]  tx_bd_num;
516
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
517
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
518
  integer        i;
519
  integer        i1;
520
  integer        i2;
521
  integer        i3;
522
  integer        fail;
523 178 mohor
  integer        test_num;
524 169 mohor
  reg    [31:0]  addr;
525
  reg    [31:0]  data;
526
  reg    [31:0]  data_max;
527 116 mohor
begin
528 169 mohor
// ACCESS TO MAC REGISTERS TEST
529
test_heading("ACCESS TO MAC REGISTERS TEST");
530
$display(" ");
531
$display("ACCESS TO MAC REGISTERS TEST");
532
fail = 0;
533
 
534 192 tadej
// reset MAC registers
535
hard_reset;
536
// reset MAC and MII LOGIC with soft reset
537 274 tadejm
//reset_mac;
538
//reset_mii;
539 169 mohor
 
540 192 tadej
 
541 178 mohor
//////////////////////////////////////////////////////////////////////
542
////                                                              ////
543
////  test_access_to_mac_reg:                                     ////
544
////                                                              ////
545
////  0: Walking 1 with single cycles across MAC regs.            ////
546
////  1: Walking 1 with single cycles across MAC buffer descript. ////
547
////  2: Test max reg. values and reg. values after writing       ////
548
////     inverse reset values and hard reset of the MAC           ////
549
////  3: Test buffer desc. RAM preserving values after hard reset ////
550
////     of the MAC and resetting the logic                       ////
551
////                                                              ////
552
//////////////////////////////////////////////////////////////////////
553 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
554 169 mohor
begin
555
 
556 178 mohor
  ////////////////////////////////////////////////////////////////////
557
  ////                                                            ////
558
  ////  Walking 1 with single cycles across MAC regs.             ////
559
  ////                                                            ////
560
  ////////////////////////////////////////////////////////////////////
561
  if (test_num == 0) // Walking 1 with single cycles across MAC regs.
562 194 tadej
  begin
563
    // TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
564
    test_name   = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
565
    `TIME; $display("  TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
566 178 mohor
 
567 194 tadej
    data = 0;
568
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
569
      begin
570
        wbm_init_waits = i;
571
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
572
        for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
573
          begin
574
            addr = `ETH_BASE + i_addr;
575
            // set ranges of R/W bits
576
            case (addr)
577
              `ETH_MODER:
578
                begin
579
                  bit_start_1 = 0;
580
                  bit_end_1   = 16;
581
                  bit_start_2 = 32; // not used
582
                  bit_end_2   = 32; // not used
583
                end
584
              `ETH_INT: // READONLY - tested within INT test
585
                begin
586
                  bit_start_1 = 32; // not used
587
                  bit_end_1   = 32; // not used
588
                  bit_start_2 = 32; // not used
589
                  bit_end_2   = 32; // not used
590
                end
591
              `ETH_INT_MASK:
592
                begin
593
                  bit_start_1 = 0;
594
                  bit_end_1   = 6;
595
                  bit_start_2 = 32; // not used
596
                  bit_end_2   = 32; // not used
597
                end
598
              `ETH_IPGT:
599
                begin
600
                  bit_start_1 = 0;
601
                  bit_end_1   = 6;
602
                  bit_start_2 = 32; // not used
603
                  bit_end_2   = 32; // not used
604
                end
605
              `ETH_IPGR1:
606
                begin
607
                  bit_start_1 = 0;
608
                  bit_end_1   = 6;
609
                  bit_start_2 = 32; // not used
610
                  bit_end_2   = 32; // not used
611
                end
612
              `ETH_IPGR2:
613
                begin
614
                  bit_start_1 = 0;
615
                  bit_end_1   = 6;
616
                  bit_start_2 = 32; // not used
617
                  bit_end_2   = 32; // not used
618
                end
619
              `ETH_PACKETLEN:
620
                begin
621
                  bit_start_1 = 0;
622
                  bit_end_1   = 31;
623
                  bit_start_2 = 32; // not used
624
                  bit_end_2   = 32; // not used
625
                end
626
              `ETH_COLLCONF:
627
                begin
628
                  bit_start_1 = 0;
629
                  bit_end_1   = 5;
630
                  bit_start_2 = 16;
631
                  bit_end_2   = 19;
632
                end
633
              `ETH_TX_BD_NUM:
634
                begin
635
                  bit_start_1 = 0;
636
                  bit_end_1   = 7;
637
                  bit_start_2 = 32; // not used
638
                  bit_end_2   = 32; // not used
639
                end
640
              `ETH_CTRLMODER:
641
                begin
642
                  bit_start_1 = 0;
643
                  bit_end_1   = 2;
644
                  bit_start_2 = 32; // not used
645
                  bit_end_2   = 32; // not used
646
                end
647
              `ETH_MIIMODER:
648
                begin
649
                  bit_start_1 = 0;
650
                  bit_end_1   = 9;
651
                  bit_start_2 = 32; // not used
652
                  bit_end_2   = 32; // not used
653
                end
654
              `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
655
                begin
656
                  bit_start_1 = 32; // not used
657
                  bit_end_1   = 32; // not used
658
                  bit_start_2 = 32; // not used
659
                  bit_end_2   = 32; // not used
660
                end
661
              `ETH_MIIADDRESS:
662
                begin
663
                  bit_start_1 = 0;
664
                  bit_end_1   = 4;
665
                  bit_start_2 = 8;
666
                  bit_end_2   = 12;
667
                end
668
              `ETH_MIITX_DATA:
669
                begin
670
                  bit_start_1 = 0;
671
                  bit_end_1   = 15;
672
                  bit_start_2 = 32; // not used
673
                  bit_end_2   = 32; // not used
674
                end
675
              `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
676
                begin
677
                  bit_start_1 = 32; // not used
678
                  bit_end_1   = 32; // not used
679
                  bit_start_2 = 32; // not used
680
                  bit_end_2   = 32; // not used
681
                end
682
              `ETH_MIISTATUS: // READONLY - tested within MIIM test
683
                begin
684
                  bit_start_1 = 32; // not used
685
                  bit_end_1   = 32; // not used
686
                  bit_start_2 = 32; // not used
687
                  bit_end_2   = 32; // not used
688
                end
689
              `ETH_MAC_ADDR0:
690
                begin
691
                  bit_start_1 = 0;
692
                  bit_end_1   = 31;
693
                  bit_start_2 = 32; // not used
694
                  bit_end_2   = 32; // not used
695 178 mohor
                  end
696 194 tadej
              `ETH_MAC_ADDR1:
697
                begin
698
                  bit_start_1 = 0;
699
                  bit_end_1   = 15;
700
                  bit_start_2 = 32; // not used
701
                  bit_end_2   = 32; // not used
702
                end
703
              `ETH_HASH_ADDR0:
704
                begin
705
                  bit_start_1 = 0;
706
                  bit_end_1   = 31;
707
                  bit_start_2 = 32; // not used
708
                  bit_end_2   = 32; // not used
709
                end
710
              default: // `ETH_HASH_ADDR1:
711
                begin
712
                  bit_start_1 = 0;
713
                  bit_end_1   = 31;
714
                  bit_start_2 = 32; // not used
715
                  bit_end_2   = 32; // not used
716
                end
717
            endcase
718
 
719
            for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
720
              begin
721
                data = 1'b1 << i_data;
722
                if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
723
                  ;
724
                else
725 178 mohor
                  begin
726 194 tadej
                    wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
727 274 tadejm
                    wait (wbm_working == 0);
728 194 tadej
                    wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
729
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
730
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
731
                      begin
732
                        if (tmp_data !== data)
733 178 mohor
                        begin
734 194 tadej
                          fail = fail + 1;
735
                          test_fail("RW bit of the MAC register was not written or not read");
736
                          `TIME;
737
                          $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
738
                                    wbm_init_waits, addr, data, tmp_data);
739
                        end
740
                      end
741
                    else // data should not be equal to tmp_data
742
                      begin
743
                        if (tmp_data === data)
744 178 mohor
                          begin
745
                            fail = fail + 1;
746 194 tadej
                            test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
747 178 mohor
                            `TIME;
748 194 tadej
                            $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
749 178 mohor
                                      wbm_init_waits, addr, data, tmp_data);
750
                          end
751 194 tadej
                      end
752
                  end
753
              end
754
          end
755
      end
756 209 tadejm
    // INTERMEDIATE DISPLAYS (The only one)
757
    $display("    ->buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
758 194 tadej
    if(fail == 0)
759
      test_ok;
760
    else
761
      fail = 0;    // Errors were reported previously
762
  end
763 178 mohor
 
764
 
765
  ////////////////////////////////////////////////////////////////////
766
  ////                                                            ////
767
  ////  Walking 1 with single cycles across MAC buffer descript.  ////
768
  ////                                                            ////
769
  ////////////////////////////////////////////////////////////////////
770
  if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
771 169 mohor
  begin
772 194 tadej
    // TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
773
    test_name   = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
774
    `TIME; $display("  TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
775 178 mohor
 
776
    data = 0;
777
    // set TX and RX buffer descriptors
778
    tx_bd_num = 32'h40;
779
    wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
780
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
781
    begin
782 169 mohor
      wbm_init_waits = i;
783
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
784 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
785 169 mohor
      begin
786
        addr = `ETH_BASE + i_addr;
787 178 mohor
        if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
788
        begin
789
          // set ranges of R/W bits
790
          case (addr[3])
791
            1'b0: // buffer control bits
792
            begin
793
              bit_start_1 = 0;
794
              bit_end_1   = 31; // 8;
795
              bit_start_2 = 11;
796
              bit_end_2   = 31;
797
            end
798
            default: // 1'b1: // buffer pointer
799
            begin
800
              bit_start_1 = 0;
801
              bit_end_1   = 31;
802
              bit_start_2 = 32; // not used
803
              bit_end_2   = 32; // not used
804
            end
805
          endcase
806
        end
807
        else // RX buffer descriptors
808
        begin
809
          // set ranges of R/W bits
810
          case (addr[3])
811
            1'b0: // buffer control bits
812
            begin
813
              bit_start_1 = 0;
814
              bit_end_1   = 31; // 7;
815
              bit_start_2 = 13;
816
              bit_end_2   = 31;
817
            end
818
            default: // 1'b1: // buffer pointer
819
            begin
820
              bit_start_1 = 0;
821
              bit_end_1   = 31;
822
              bit_start_2 = 32; // not used
823
              bit_end_2   = 32; // not used
824
            end
825
          endcase
826
        end
827
 
828 169 mohor
        for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
829
        begin
830
          data = 1'b1 << i_data;
831 178 mohor
          if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
832
            ;
833 169 mohor
          else
834
          begin
835
            wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
836
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
837
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
838
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
839
            begin
840
              if (tmp_data !== data)
841
              begin
842
                fail = fail + 1;
843 178 mohor
                test_fail("RW bit of the MAC buffer descriptors was not written or not read");
844 169 mohor
                `TIME;
845
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
846
                          wbm_init_waits, addr, data, tmp_data);
847
              end
848
            end
849
            else // data should not be equal to tmp_data
850
            begin
851
              if (tmp_data === data)
852
              begin
853
                fail = fail + 1;
854 178 mohor
                test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
855 169 mohor
                `TIME;
856
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
857
                          wbm_init_waits, addr, data, tmp_data);
858
              end
859
            end
860
          end
861
        end
862
      end
863 178 mohor
      // INTERMEDIATE DISPLAYS
864
      case (i)
865 209 tadejm
        0:       $display("    ->buffer descriptors tested with 0 bus delay");
866
        1:       $display("    ->buffer descriptors tested with 1 bus delay cycle");
867
        2:       $display("    ->buffer descriptors tested with 2 bus delay cycles");
868
        3:       $display("    ->buffer descriptors tested with 3 bus delay cycles");
869
        default: $display("    ->buffer descriptors tested with 4 bus delay cycles");
870 178 mohor
      endcase
871
    end
872
    if(fail == 0)
873
      test_ok;
874
    else
875
      fail = 0;
876 169 mohor
  end
877 178 mohor
 
878
 
879
  ////////////////////////////////////////////////////////////////////
880
  ////                                                            ////
881
  ////  Test max reg. values and reg. values after writing        ////
882
  ////  inverse reset values and hard reset of the MAC            ////
883
  ////                                                            ////
884
  ////////////////////////////////////////////////////////////////////
885
  if (test_num == 2) // Start this task
886 169 mohor
  begin
887 194 tadej
    // TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
888 178 mohor
    test_name   =
889 194 tadej
      "TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
890 178 mohor
    `TIME; $display(
891 194 tadej
      "  TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
892 178 mohor
 
893
    // reset MAC registers
894
    hard_reset;
895
    for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
896 169 mohor
    begin
897 178 mohor
      for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
898 169 mohor
      begin
899 178 mohor
        addr = `ETH_BASE + i_addr;
900
        // set ranges of R/W bits
901
        case (addr)
902
          `ETH_MODER:
903 169 mohor
          begin
904 178 mohor
            data = 32'h0000_A800;
905
            data_max = 32'h0001_FFFF;
906 169 mohor
          end
907 178 mohor
          `ETH_INT: // READONLY - tested within INT test
908 169 mohor
          begin
909 178 mohor
            data = 32'h0000_0000;
910
            data_max = 32'h0000_0000;
911 169 mohor
          end
912
          `ETH_INT_MASK:
913 178 mohor
          begin
914
            data = 32'h0000_0000;
915
            data_max = 32'h0000_007F;
916
          end
917 169 mohor
          `ETH_IPGT:
918 178 mohor
          begin
919
            data = 32'h0000_0012;
920
            data_max = 32'h0000_007F;
921
          end
922 169 mohor
          `ETH_IPGR1:
923 178 mohor
          begin
924
            data = 32'h0000_000C;
925
            data_max = 32'h0000_007F;
926
          end
927 169 mohor
          `ETH_IPGR2:
928 178 mohor
          begin
929
            data = 32'h0000_0012;
930
            data_max = 32'h0000_007F;
931
          end
932 169 mohor
          `ETH_PACKETLEN:
933 178 mohor
          begin
934
            data = 32'h0040_0600;
935
            data_max = 32'hFFFF_FFFF;
936
          end
937 169 mohor
          `ETH_COLLCONF:
938 178 mohor
          begin
939
            data = 32'h000F_003F;
940
            data_max = 32'h000F_003F;
941
          end
942 169 mohor
          `ETH_TX_BD_NUM:
943 178 mohor
          begin
944
            data = 32'h0000_0040;
945
            data_max = 32'h0000_0080;
946
          end
947 169 mohor
          `ETH_CTRLMODER:
948 178 mohor
          begin
949
            data = 32'h0000_0000;
950
            data_max = 32'h0000_0007;
951
          end
952 169 mohor
          `ETH_MIIMODER:
953 178 mohor
          begin
954
            data = 32'h0000_0064;
955
            data_max = 32'h0000_03FF;
956
          end
957 169 mohor
          `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
958 178 mohor
          begin
959
            data = 32'h0000_0000;
960
            data_max = 32'h0000_0007;
961
          end
962 169 mohor
          `ETH_MIIADDRESS:
963 178 mohor
          begin
964
            data = 32'h0000_0000;
965
            data_max = 32'h0000_1F1F;
966
          end
967 169 mohor
          `ETH_MIITX_DATA:
968 178 mohor
          begin
969
            data = 32'h0000_0000;
970
            data_max = 32'h0000_FFFF;
971
          end
972 169 mohor
          `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
973
          begin
974 178 mohor
            data = 32'h0000_0000;
975
            data_max = 32'h0000_0000;
976 169 mohor
          end
977 178 mohor
          `ETH_MIISTATUS: // READONLY - tested within MIIM test
978 169 mohor
          begin
979 178 mohor
            data = 32'h0000_0000;
980
            data_max = 32'h0000_0000;
981 169 mohor
          end
982 178 mohor
          `ETH_MAC_ADDR0:
983 169 mohor
          begin
984 178 mohor
            data = 32'h0000_0000;
985
            data_max = 32'hFFFF_FFFF;
986 169 mohor
          end
987 178 mohor
          `ETH_MAC_ADDR1:
988 169 mohor
          begin
989 178 mohor
            data = 32'h0000_0000;
990
            data_max = 32'h0000_FFFF;
991 169 mohor
          end
992 178 mohor
          `ETH_HASH_ADDR0:
993 169 mohor
          begin
994 178 mohor
            data = 32'h0000_0000;
995
            data_max = 32'hFFFF_FFFF;
996 169 mohor
          end
997 178 mohor
          default: // `ETH_HASH_ADDR1:
998 169 mohor
          begin
999 178 mohor
            data = 32'h0000_0000;
1000
            data_max = 32'hFFFF_FFFF;
1001 169 mohor
          end
1002
        endcase
1003 178 mohor
 
1004
        wbm_init_waits = {$random} % 3;
1005
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1006
        if (i == 0)
1007 274 tadejm
        begin
1008 178 mohor
          wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1009 274 tadejm
        end
1010 178 mohor
        else if (i == 2)
1011 274 tadejm
        begin
1012 178 mohor
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1013 274 tadejm
        end
1014 178 mohor
        else if ((i == 1) || (i == 4))
1015 169 mohor
        begin
1016 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1017
          if (tmp_data !== data)
1018
          begin
1019
            fail = fail + 1;
1020
            test_fail("RESET value of the MAC register is not correct");
1021
            `TIME;
1022
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1023
          end
1024 169 mohor
        end
1025 178 mohor
        else // check maximum values
1026 169 mohor
        begin
1027
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1028 178 mohor
          if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
1029 169 mohor
          begin
1030
            if (tmp_data !== data)
1031
            begin
1032
              fail = fail + 1;
1033 178 mohor
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1034 169 mohor
              `TIME;
1035 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1036 169 mohor
            end
1037 178 mohor
            // try maximum (80)
1038
            wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1039
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1040
            if (tmp_data !== data_max)
1041
            begin
1042
              fail = fail + 1;
1043
              test_fail("MAX value of the TX_BD_NUM register is not correct");
1044
              `TIME;
1045
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1046
            end
1047
            // try one less than maximum (80)
1048
            wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1049
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1050
            if (tmp_data !== (data_max - 1))
1051
            begin
1052
              fail = fail + 1;
1053
              test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
1054
              `TIME;
1055
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1056
            end
1057
            // try one more than maximum (80)
1058
            wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1059
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1060
            if (tmp_data !== (data_max - 1)) // previous data should remain in this register
1061
            begin
1062
              fail = fail + 1;
1063
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1064
              `TIME;
1065
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1066
            end
1067 169 mohor
          end
1068 178 mohor
          else
1069 169 mohor
          begin
1070 178 mohor
            if (tmp_data !== data_max)
1071 169 mohor
            begin
1072
              fail = fail + 1;
1073 178 mohor
              test_fail("MAX value of the MAC register is not correct");
1074 169 mohor
              `TIME;
1075 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1076 169 mohor
            end
1077
          end
1078
        end
1079
      end
1080 178 mohor
      // reset MAC registers
1081
      if ((i == 0) || (i == 3))
1082
        hard_reset;
1083 169 mohor
    end
1084 178 mohor
    if(fail == 0)
1085
      test_ok;
1086
    else
1087
      fail = 0;
1088 169 mohor
  end
1089 116 mohor
 
1090 156 mohor
 
1091 181 mohor
  ////////////////////////////////////////////////////////////////////
1092
  ////                                                            ////
1093
  ////  Test buffer desc. ram preserving values after hard reset  ////
1094
  ////  of the mac and reseting the logic                         ////
1095
  ////                                                            ////
1096
  ////////////////////////////////////////////////////////////////////
1097 178 mohor
  if (test_num == 3) // Start this task
1098 169 mohor
  begin
1099 194 tadej
    // TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
1100
    test_name   = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
1101 178 mohor
    `TIME;
1102 194 tadej
    $display("  TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
1103 178 mohor
 
1104
    // reset MAC registers
1105
    hard_reset;
1106
    // reset LOGIC with soft reset
1107 274 tadejm
//    reset_mac;
1108
//    reset_mii;
1109 178 mohor
    for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
1110 169 mohor
    begin
1111 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1112 169 mohor
      begin
1113 178 mohor
        addr = `ETH_BASE + i_addr;
1114
 
1115
        wbm_init_waits = {$random} % 3;
1116
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1117
        if (i == 0)
1118 169 mohor
        begin
1119 178 mohor
          data = 32'hFFFFFFFF;
1120
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1121 169 mohor
        end
1122 178 mohor
        else if (i == 2)
1123 169 mohor
        begin
1124 178 mohor
          data = 32'h00000000;
1125
          wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1126 169 mohor
        end
1127
        else
1128
        begin
1129 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1130
          if (tmp_data !== data)
1131 169 mohor
          begin
1132
            fail = fail + 1;
1133 178 mohor
            test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
1134 169 mohor
            `TIME;
1135 178 mohor
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1136 169 mohor
          end
1137
        end
1138
      end
1139 178 mohor
      if ((i == 0) || (i == 2))
1140
      begin
1141
        // reset MAC registers
1142
        hard_reset;
1143
        // reset LOGIC with soft reset
1144 274 tadejm
//        reset_mac;
1145
//        reset_mii;
1146 178 mohor
      end
1147 169 mohor
    end
1148 178 mohor
    if(fail == 0)
1149
      test_ok;
1150
    else
1151
    fail = 0;
1152 169 mohor
  end
1153 116 mohor
 
1154
 
1155 178 mohor
  if (test_num == 4) // Start this task
1156 169 mohor
  begin
1157 194 tadej
        /*  // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
1158
          test_name   = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
1159
          `TIME; $display("  TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
1160 178 mohor
 
1161
          data = 0;
1162
          burst_data = 0;
1163
          burst_tmp_data = 0;
1164
          i_length = 10; // two bursts for length 20
1165
          for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
1166
          begin
1167
            for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
1168
            begin
1169
              wbm_init_waits = i;
1170
              wbm_subseq_waits = i1;
1171
              #1;
1172
              for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
1173
              begin
1174
                data = 1'b1 << i_data;
1175
                #1;
1176
                for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
1177
                begin
1178
                  burst_data = burst_data << 32;
1179
                  // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
1180
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1181
                  begin
1182
                    #1 burst_data[31:0] = 0;
1183
                  end
1184
                  else
1185
                  begin
1186
                    #1 burst_data[31:0] = data;
1187
                  end
1188
                end
1189
                #1;
1190
                // 2 burst writes
1191
                addr = `ETH_BASE; // address of a first burst
1192
                wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1193
                burst_tmp_data = burst_data >> (32 * i_length);
1194
                addr = addr + 32'h28; // address of a second burst
1195
                wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1196
                #1;
1197
                // 2 burst reads
1198
                addr = `ETH_BASE; // address of a first burst
1199
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1200
                         wbm_init_waits, wbm_subseq_waits); // first burst
1201
                burst_tmp_data = burst_tmp_data << (32 * i_length);
1202
                addr = addr + 32'h28; // address of a second burst
1203
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1204
                         wbm_init_waits, wbm_subseq_waits); // second burst
1205
                #1;
1206
                for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
1207
                begin
1208
                  // set ranges of R/W bits
1209
                  case (`ETH_BASE + i2)
1210
                  `ETH_MODER:
1211
                    begin
1212
                      bit_start_1 = 0;
1213
                      bit_end_1   = 16;
1214
                      bit_start_2 = 32; // not used
1215
                      bit_end_2   = 32; // not used
1216
                    end
1217
                  `ETH_INT: // READONLY - tested within INT test
1218
                    begin
1219
                      bit_start_1 = 32; // not used
1220
                      bit_end_1   = 32; // not used
1221
                      bit_start_2 = 32; // not used
1222
                      bit_end_2   = 32; // not used
1223
                    end
1224
                  `ETH_INT_MASK:
1225
                    begin
1226
                      bit_start_1 = 0;
1227
                      bit_end_1   = 6;
1228
                      bit_start_2 = 32; // not used
1229
                      bit_end_2   = 32; // not used
1230
                    end
1231
                  `ETH_IPGT:
1232
                    begin
1233
                      bit_start_1 = 0;
1234
                      bit_end_1   = 6;
1235
                      bit_start_2 = 32; // not used
1236
                      bit_end_2   = 32; // not used
1237
                    end
1238
                  `ETH_IPGR1:
1239
                    begin
1240
                      bit_start_1 = 0;
1241
                      bit_end_1   = 6;
1242
                      bit_start_2 = 32; // not used
1243
                      bit_end_2   = 32; // not used
1244
                    end
1245
                  `ETH_IPGR2:
1246
                    begin
1247
                      bit_start_1 = 0;
1248
                      bit_end_1   = 6;
1249
                      bit_start_2 = 32; // not used
1250
                      bit_end_2   = 32; // not used
1251
                    end
1252
                  `ETH_PACKETLEN:
1253
                    begin
1254
                      bit_start_1 = 0;
1255
                      bit_end_1   = 31;
1256
                      bit_start_2 = 32; // not used
1257
                      bit_end_2   = 32; // not used
1258
                    end
1259
                  `ETH_COLLCONF:
1260
                    begin
1261
                      bit_start_1 = 0;
1262
                      bit_end_1   = 5;
1263
                      bit_start_2 = 16;
1264
                      bit_end_2   = 19;
1265
                    end
1266
                  `ETH_TX_BD_NUM:
1267
                    begin
1268
                      bit_start_1 = 0;
1269
                      bit_end_1   = 7;
1270
                      bit_start_2 = 32; // not used
1271
                      bit_end_2   = 32; // not used
1272
                    end
1273
                  `ETH_CTRLMODER:
1274
                    begin
1275
                      bit_start_1 = 0;
1276
                      bit_end_1   = 2;
1277
                      bit_start_2 = 32; // not used
1278
                      bit_end_2   = 32; // not used
1279
                    end
1280
                  `ETH_MIIMODER:
1281
                    begin
1282
                      bit_start_1 = 0;
1283
                      bit_end_1   = 9;
1284
                      bit_start_2 = 32; // not used
1285
                      bit_end_2   = 32; // not used
1286
                    end
1287
                  `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
1288
                    begin
1289
                      bit_start_1 = 32; // not used
1290
                      bit_end_1   = 32; // not used
1291
                      bit_start_2 = 32; // not used
1292
                      bit_end_2   = 32; // not used
1293
                    end
1294
                  `ETH_MIIADDRESS:
1295
                    begin
1296
                      bit_start_1 = 0;
1297
                      bit_end_1   = 4;
1298
                      bit_start_2 = 8;
1299
                      bit_end_2   = 12;
1300
                    end
1301
                  `ETH_MIITX_DATA:
1302
                    begin
1303
                      bit_start_1 = 0;
1304
                      bit_end_1   = 15;
1305
                      bit_start_2 = 32; // not used
1306
                      bit_end_2   = 32; // not used
1307
                    end
1308
                  `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
1309
                    begin
1310
                      bit_start_1 = 32; // not used
1311
                      bit_end_1   = 32; // not used
1312
                      bit_start_2 = 32; // not used
1313
                      bit_end_2   = 32; // not used
1314
                    end
1315
                  `ETH_MIISTATUS: // READONLY - tested within MIIM test
1316
                    begin
1317
                      bit_start_1 = 32; // not used
1318
                      bit_end_1   = 32; // not used
1319
                      bit_start_2 = 32; // not used
1320
                      bit_end_2   = 32; // not used
1321
                    end
1322
                  `ETH_MAC_ADDR0:
1323
                    begin
1324
                      bit_start_1 = 0;
1325
                      bit_end_1   = 31;
1326
                      bit_start_2 = 32; // not used
1327
                      bit_end_2   = 32; // not used
1328
                    end
1329
                  `ETH_MAC_ADDR1:
1330
                    begin
1331
                      bit_start_1 = 0;
1332
                      bit_end_1   = 15;
1333
                      bit_start_2 = 32; // not used
1334
                      bit_end_2   = 32; // not used
1335
                    end
1336
                  `ETH_HASH_ADDR0:
1337
                    begin
1338
                      bit_start_1 = 0;
1339
                      bit_end_1   = 31;
1340
                      bit_start_2 = 32; // not used
1341
                      bit_end_2   = 32; // not used
1342
                    end
1343
                  default: // `ETH_HASH_ADDR1:
1344
                    begin
1345
                      bit_start_1 = 0;
1346
                      bit_end_1   = 31;
1347
                      bit_start_2 = 32; // not used
1348
                      bit_end_2   = 32; // not used
1349
                    end
1350
                  endcase
1351
                  #1;
1352
                  // 3 LSBits of MIICOMMAND are NOT written !!!
1353
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1354
                  begin
1355
                    if (burst_tmp_data[31:0] !== burst_data[31:0])
1356
                    begin
1357
                      fail = fail + 1;
1358
                      test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
1359
                      `TIME;
1360
                      $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1361
                                wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1362
                    end
1363
                  end
1364
                  else
1365
                  begin
1366
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
1367
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
1368
                    begin
1369
                      if (burst_tmp_data[31:0] !== burst_data[31:0])
1370
                      begin
1371
                        fail = fail + 1;
1372
                        test_fail("RW bit of the MAC register was not written or not read");
1373
                        `TIME;
1374
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1375
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1376
                      end
1377
                    end
1378
                    else // data should not be equal to tmp_data
1379
                    begin
1380
                      if (burst_tmp_data[31:0] === burst_data[31:0])
1381
                      begin
1382
                        fail = fail + 1;
1383
                        test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
1384
                        `TIME;
1385
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1386
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1387
                      end
1388
                    end
1389
                  end
1390
                  burst_tmp_data = burst_tmp_data >> 32;
1391
                  burst_data = burst_data >> 32;
1392
                end
1393
              end
1394
            end
1395
          end
1396
          if(fail == 0)
1397
            test_ok;
1398
          else
1399
            fail = 0;*/
1400
  end
1401 116 mohor
 
1402 169 mohor
end
1403 156 mohor
 
1404 169 mohor
end
1405
endtask // test_access_to_mac_reg
1406 156 mohor
 
1407
 
1408 169 mohor
task test_mii;
1409
  input  [31:0]  start_task;
1410
  input  [31:0]  end_task;
1411
  integer        i;
1412
  integer        i1;
1413
  integer        i2;
1414
  integer        i3;
1415
  integer        cnt;
1416
  integer        fail;
1417 181 mohor
  integer        test_num;
1418 169 mohor
  reg     [8:0]  clk_div; // only 8 bits are valid!
1419
  reg     [4:0]  phy_addr;
1420
  reg     [4:0]  reg_addr;
1421
  reg     [15:0] phy_data;
1422
  reg     [15:0] tmp_data;
1423
begin
1424
// MIIM MODULE TEST
1425
test_heading("MIIM MODULE TEST");
1426
$display(" ");
1427
$display("MIIM MODULE TEST");
1428
fail = 0;
1429 156 mohor
 
1430 192 tadej
// reset MAC registers
1431
hard_reset;
1432
// reset MAC and MII LOGIC with soft reset
1433 274 tadejm
//reset_mac;
1434
//reset_mii;
1435 116 mohor
 
1436 194 tadej
 
1437 181 mohor
//////////////////////////////////////////////////////////////////////
1438
////                                                              ////
1439
////  test_mii:                                                   ////
1440
////                                                              ////
1441
////  0:  Test clock divider of mii management module with all    ////
1442
////      possible frequences.                                    ////
1443
////  1:  Test various readings from 'real' phy registers.        ////
1444
////  2:  Test various writings to 'real' phy registers (control  ////
1445
////      and non writable registers)                             ////
1446
////  3:  Test reset phy through mii management module            ////
1447
////  4:  Test 'walking one' across phy address (with and without ////
1448
////      preamble)                                               ////
1449
////  5:  Test 'walking one' across phy's register address (with  ////
1450
////      and without preamble)                                   ////
1451
////  6:  Test 'walking one' across phy's data (with and without  ////
1452
////      preamble)                                               ////
1453
////  7:  Test reading from phy with wrong phy address (host      ////
1454
////      reading high 'z' data)                                  ////
1455
////  8:  Test writing to phy with wrong phy address and reading  ////
1456
////      from correct one                                        ////
1457
////  9:  Test sliding stop scan command immediately after read   ////
1458
////      request (with and without preamble)                     ////
1459
//// 10:  Test sliding stop scan command immediately after write  ////
1460
////      request (with and without preamble)                     ////
1461
//// 11:  Test busy and nvalid status durations during write      ////
1462
////      (with and without preamble)                             ////
1463
//// 12:  Test busy and nvalid status durations during write      ////
1464
////      (with and without preamble)                             ////
1465
//// 13:  Test busy and nvalid status durations during scan (with ////
1466
////      and without preamble)                                   ////
1467
//// 14:  Test scan status from phy with detecting link-fail bit  ////
1468
////      (with and without preamble)                             ////
1469
//// 15:  Test scan status from phy with sliding link-fail bit    ////
1470
////      (with and without preamble)                             ////
1471
//// 16:  Test sliding stop scan command immediately after scan   ////
1472
////      request (with and without preamble)                     ////
1473
//// 17:  Test sliding stop scan command after 2. scan (with and  ////
1474
////      without preamble)                                       ////
1475
////                                                              ////
1476
//////////////////////////////////////////////////////////////////////
1477 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
1478 169 mohor
begin
1479 194 tadej
 
1480 181 mohor
  ////////////////////////////////////////////////////////////////////
1481
  ////                                                            ////
1482
  ////  Test clock divider of mii management module with all      ////
1483
  ////  possible frequences.                                      ////
1484
  ////                                                            ////
1485
  ////////////////////////////////////////////////////////////////////
1486
  if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
1487 169 mohor
  begin
1488 194 tadej
    // TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
1489
    test_name   = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
1490
    `TIME; $display("  TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
1491 181 mohor
 
1492
    wait(Mdc_O); // wait for MII clock to be 1
1493
    for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
1494
    begin
1495
      i1 = 0;
1496
      i2 = 0;
1497
      #Tp mii_set_clk_div(clk_div[7:0]);
1498
      @(posedge Mdc_O);
1499
      #Tp;
1500
      fork
1501 169 mohor
        begin
1502 181 mohor
          @(posedge Mdc_O);
1503 169 mohor
          #Tp;
1504 181 mohor
          disable count_i1;
1505
          disable count_i2;
1506 169 mohor
        end
1507 181 mohor
        begin: count_i1
1508
          forever
1509
          begin
1510
            @(posedge wb_clk);
1511
            i1 = i1 + 1;
1512
            #Tp;
1513
          end
1514
        end
1515
        begin: count_i2
1516
          forever
1517
          begin
1518
            @(negedge wb_clk);
1519
            i2 = i2 + 1;
1520
            #Tp;
1521
          end
1522
        end
1523
      join
1524
      if((clk_div[7:0] == 0) || (clk_div[7:0] == 1) || (clk_div[7:0] == 2) || (clk_div[7:0] == 3))
1525
      begin
1526
        if((i1 == i2) && (i1 == 2))
1527 169 mohor
        begin
1528
        end
1529 181 mohor
        else
1530
        begin
1531
          fail = fail + 1;
1532 209 tadejm
          test_fail("Clock divider of MII module did'nt divide frequency corectly (it should divide by 2)");
1533 181 mohor
        end
1534 169 mohor
      end
1535
      else
1536
      begin
1537 181 mohor
        if((i1 == i2) && (i1 == {clk_div[7:1], 1'b0}))
1538
        begin
1539
        end
1540
        else
1541
        begin
1542
          fail = fail + 1;
1543
          test_fail("Clock divider of MII module did'nt divide frequency corectly");
1544
        end
1545 169 mohor
      end
1546
    end
1547 181 mohor
    if(fail == 0)
1548
      test_ok;
1549 169 mohor
    else
1550 181 mohor
      fail = 0;
1551
  end
1552
 
1553
 
1554
  ////////////////////////////////////////////////////////////////////
1555
  ////                                                            ////
1556
  ////  Test various readings from 'real' phy registers.          ////
1557
  ////                                                            ////
1558
  ////////////////////////////////////////////////////////////////////
1559
  if (test_num == 1) // Test various readings from 'real' phy registers.
1560
  begin
1561 194 tadej
    // TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
1562
    test_name   = "TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
1563
    `TIME; $display("  TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
1564 181 mohor
 
1565
    // set the fastest possible MII
1566
    clk_div = 0;
1567
    mii_set_clk_div(clk_div[7:0]);
1568
    // set address
1569
    reg_addr = 5'h1F;
1570
    phy_addr = 5'h1;
1571
    while(reg_addr >= 5'h4)
1572 169 mohor
    begin
1573 181 mohor
      // read request
1574
      #Tp mii_read_req(phy_addr, reg_addr);
1575
      check_mii_busy; // wait for read to finish
1576
      // read data
1577 274 tadejm
      wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1578 181 mohor
      if (phy_data !== 16'hDEAD)
1579 169 mohor
      begin
1580 181 mohor
        test_fail("Wrong data was read from PHY from 'not used' address space");
1581
        fail = fail + 1;
1582 169 mohor
      end
1583 181 mohor
      if (reg_addr == 5'h4) // go out of for loop
1584
        reg_addr = 5'h3;
1585 169 mohor
      else
1586 181 mohor
        reg_addr = reg_addr - 5'h9;
1587 169 mohor
    end
1588 181 mohor
 
1589
    // set address
1590
    reg_addr = 5'h3;
1591
    // read request
1592
    #Tp mii_read_req(phy_addr, reg_addr);
1593
    check_mii_busy; // wait for read to finish
1594
    // read data
1595 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1596 181 mohor
    if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})
1597
    begin
1598
      test_fail("Wrong data was read from PHY from ID register 2");
1599
      fail = fail + 1;
1600
    end
1601
    if(fail == 0)
1602
      test_ok;
1603
    else
1604
      fail = 0;
1605 169 mohor
  end
1606 116 mohor
 
1607
 
1608 181 mohor
  ////////////////////////////////////////////////////////////////////
1609
  ////                                                            ////
1610
  ////  Test various writings to 'real' phy registers (control    ////
1611
  ////  and non writable registers)                               ////
1612
  ////                                                            ////
1613
  ////////////////////////////////////////////////////////////////////
1614
  if (test_num == 2) // 
1615 169 mohor
  begin
1616 194 tadej
    // TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
1617
    test_name   = "TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
1618
    `TIME; $display("  TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
1619 181 mohor
 
1620
    // negate data and try to write into unwritable register
1621
    tmp_data = ~phy_data;
1622
    // write request
1623
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1624
    check_mii_busy; // wait for write to finish
1625 169 mohor
    // read request
1626
    #Tp mii_read_req(phy_addr, reg_addr);
1627
    check_mii_busy; // wait for read to finish
1628
    // read data
1629 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1630 181 mohor
    if (tmp_data !== phy_data)
1631
    begin
1632
      test_fail("Data was written into unwritable PHY register - ID register 2");
1633
      fail = fail + 1;
1634
    end
1635
 
1636
    // set address
1637
    reg_addr = 5'h0; // control register
1638
    // read request
1639
    #Tp mii_read_req(phy_addr, reg_addr);
1640
    check_mii_busy; // wait for read to finish
1641
    // read data
1642 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1643 181 mohor
    // write request
1644
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1645
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1646
    check_mii_busy; // wait for write to finish
1647
    // read request
1648
    #Tp mii_read_req(phy_addr, reg_addr);
1649
    check_mii_busy; // wait for read to finish
1650
    // read data
1651 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1652 181 mohor
    if (phy_data !== 16'h7DFF)
1653 169 mohor
    begin
1654 181 mohor
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1655 169 mohor
      fail = fail + 1;
1656
    end
1657 181 mohor
    // write request
1658
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1659
    check_mii_busy; // wait for write to finish
1660
    // read request
1661
    #Tp mii_read_req(phy_addr, reg_addr);
1662
    check_mii_busy; // wait for read to finish
1663
    // read data
1664 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1665 181 mohor
    if (phy_data !== tmp_data)
1666
    begin
1667
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1668
      fail = fail + 1;
1669
    end
1670
    if(fail == 0)
1671
      test_ok;
1672 116 mohor
    else
1673 181 mohor
      fail = 0;
1674 169 mohor
  end
1675 116 mohor
 
1676
 
1677 181 mohor
  ////////////////////////////////////////////////////////////////////
1678
  ////                                                            ////
1679
  ////  Test reset phy through mii management module              ////
1680
  ////                                                            ////
1681
  ////////////////////////////////////////////////////////////////////
1682
  if (test_num == 3) // 
1683 169 mohor
  begin
1684 194 tadej
    // TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE
1685
    test_name   = "TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE";
1686
    `TIME; $display("  TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE");
1687 181 mohor
 
1688
    // set address
1689
    reg_addr = 5'h0; // control register
1690
    // write request
1691
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1692
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1693
    check_mii_busy; // wait for write to finish
1694
    // read request
1695
    #Tp mii_read_req(phy_addr, reg_addr);
1696
    check_mii_busy; // wait for read to finish
1697
    // read data
1698 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1699 181 mohor
    if (phy_data !== tmp_data)
1700
    begin
1701
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1702
      fail = fail + 1;
1703
    end
1704
    // set reset bit - selfclearing bit in PHY
1705
    phy_data = phy_data | 16'h8000;
1706
    // write request
1707
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1708
    check_mii_busy; // wait for write to finish
1709
    // read request
1710
    #Tp mii_read_req(phy_addr, reg_addr);
1711
    check_mii_busy; // wait for read to finish
1712
    // read data
1713 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1714 181 mohor
    // check self clearing of reset bit
1715
    if (tmp_data[15] !== 1'b0)
1716
    begin
1717
      test_fail("Reset bit should be self cleared - control register");
1718
      fail = fail + 1;
1719
    end
1720
    // check reset value of control register
1721
    if (tmp_data !== {2'h0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 3'h0, `LED_CFG3, 8'h0})
1722
    begin
1723
      test_fail("PHY was not reset correctly AND/OR reset bit not self cleared");
1724
      fail = fail + 1;
1725
    end
1726
    if(fail == 0)
1727
      test_ok;
1728
    else
1729
      fail = 0;
1730 169 mohor
  end
1731
 
1732
 
1733 181 mohor
  ////////////////////////////////////////////////////////////////////
1734
  ////                                                            ////
1735
  ////  Test 'walking one' across phy address (with and without   ////
1736
  ////  preamble)                                                 ////
1737
  ////                                                            ////
1738
  ////////////////////////////////////////////////////////////////////
1739
  if (test_num == 4) // 
1740 169 mohor
  begin
1741 194 tadej
    // TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
1742
    test_name   = "TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1743
    `TIME; $display("  TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1744 181 mohor
 
1745
    // set PHY to test mode
1746
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1747
    for (i = 0; i <= 1; i = i + 1)
1748 169 mohor
    begin
1749 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1750
      #Tp eth_phy.clear_test_regs;
1751
      // MII mode register
1752
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1753
                wbm_subseq_waits);
1754
      // walk one across phy address
1755
      for (phy_addr = 5'h1; phy_addr > 5'h0; phy_addr = phy_addr << 1)
1756 169 mohor
      begin
1757 181 mohor
        reg_addr = $random;
1758
        tmp_data = $random;
1759
        // write request
1760
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1761
        check_mii_busy; // wait for write to finish
1762
        // read request
1763
        #Tp mii_read_req(phy_addr, reg_addr);
1764
        check_mii_busy; // wait for read to finish
1765
        // read data
1766 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1767 181 mohor
        #Tp;
1768
        if (phy_data !== tmp_data)
1769
        begin
1770
          if (i)
1771
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1772
          else
1773
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1774
          fail = fail + 1;
1775
        end
1776
        @(posedge wb_clk);
1777
        #Tp;
1778 169 mohor
      end
1779
    end
1780 181 mohor
    // set PHY to normal mode
1781
    #Tp eth_phy.test_regs(0);
1782
    #Tp eth_phy.preamble_suppresed(0);
1783
    // MII mode register
1784
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1785
    if(fail == 0)
1786
      test_ok;
1787
    else
1788
      fail = 0;
1789 169 mohor
  end
1790
 
1791
 
1792 181 mohor
  ////////////////////////////////////////////////////////////////////
1793
  ////                                                            ////
1794
  ////  Test 'walking one' across phy's register address (with    ////
1795
  ////  and without preamble)                                     ////
1796
  ////                                                            ////
1797
  ////////////////////////////////////////////////////////////////////
1798
  if (test_num == 5) // 
1799 169 mohor
  begin
1800 194 tadej
    // TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
1801
    test_name   = "TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1802
    `TIME; $display("  TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1803 181 mohor
 
1804
    // set PHY to test mode
1805
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1806
    for (i = 0; i <= 1; i = i + 1)
1807 169 mohor
    begin
1808 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1809
      #Tp eth_phy.clear_test_regs;
1810
      // MII mode register
1811
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1812
                wbm_subseq_waits);
1813
      // walk one across reg address
1814
      for (reg_addr = 5'h1; reg_addr > 5'h0; reg_addr = reg_addr << 1)
1815 169 mohor
      begin
1816 181 mohor
        phy_addr = $random;
1817
        tmp_data = $random;
1818
        // write request
1819
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1820
        check_mii_busy; // wait for write to finish
1821
        // read request
1822
        #Tp mii_read_req(phy_addr, reg_addr);
1823
        check_mii_busy; // wait for read to finish
1824
        // read data
1825 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1826 181 mohor
        #Tp;
1827
        if (phy_data !== tmp_data)
1828
        begin
1829
          if (i)
1830
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1831
          else
1832
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1833
          fail = fail + 1;
1834
        end
1835
        @(posedge wb_clk);
1836
        #Tp;
1837 169 mohor
      end
1838
    end
1839 181 mohor
    // set PHY to normal mode
1840
    #Tp eth_phy.test_regs(0);
1841
    #Tp eth_phy.preamble_suppresed(0);
1842
    // MII mode register
1843
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1844
    if(fail == 0)
1845
      test_ok;
1846
    else
1847
      fail = 0;
1848 169 mohor
  end
1849
 
1850
 
1851 181 mohor
  ////////////////////////////////////////////////////////////////////
1852
  ////                                                            ////
1853
  ////  Test 'walking one' across phy's data (with and without    ////
1854
  ////  preamble)                                                 ////
1855
  ////                                                            ////
1856
  ////////////////////////////////////////////////////////////////////
1857
  if (test_num == 6) // 
1858 169 mohor
  begin
1859 194 tadej
    // TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
1860
    test_name   = "TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
1861
    `TIME; $display("  TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
1862 181 mohor
 
1863
    // set PHY to test mode
1864
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1865
    for (i = 0; i <= 1; i = i + 1)
1866 169 mohor
    begin
1867 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1868
      #Tp eth_phy.clear_test_regs;
1869
      // MII mode register
1870
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1871
                wbm_subseq_waits);
1872
      // walk one across data
1873
      for (tmp_data = 16'h1; tmp_data > 16'h0; tmp_data = tmp_data << 1)
1874 169 mohor
      begin
1875 181 mohor
        phy_addr = $random;
1876
        reg_addr = $random;
1877
        // write request
1878
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1879
        check_mii_busy; // wait for write to finish
1880
        // read request
1881
        #Tp mii_read_req(phy_addr, reg_addr);
1882
        check_mii_busy; // wait for read to finish
1883
        // read data
1884 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1885 181 mohor
        #Tp;
1886
        if (phy_data !== tmp_data)
1887
        begin
1888
          if (i)
1889
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1890
          else
1891
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1892
          fail = fail + 1;
1893
        end
1894
        @(posedge wb_clk);
1895
        #Tp;
1896 169 mohor
      end
1897
    end
1898 181 mohor
    // set PHY to normal mode
1899
    #Tp eth_phy.test_regs(0);
1900
    #Tp eth_phy.preamble_suppresed(0);
1901
    // MII mode register
1902
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1903
    if(fail == 0)
1904
      test_ok;
1905
    else
1906
      fail = 0;
1907 169 mohor
  end
1908
 
1909
 
1910 181 mohor
  ////////////////////////////////////////////////////////////////////
1911
  ////                                                            ////
1912
  ////  Test reading from phy with wrong phy address (host        ////
1913
  ////  reading high 'z' data)                                    ////
1914
  ////                                                            ////
1915
  ////////////////////////////////////////////////////////////////////
1916
  if (test_num == 7) // 
1917 169 mohor
  begin
1918 194 tadej
    // TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
1919
    test_name   = "TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
1920
    `TIME; $display("  TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
1921 181 mohor
 
1922
    phy_addr = 5'h2; // wrong PHY address
1923
    // read request
1924
    #Tp mii_read_req(phy_addr, reg_addr);
1925
    check_mii_busy; // wait for read to finish
1926
    // read data
1927
    $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
1928 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1929 181 mohor
    if (tmp_data !== 16'hzzzz)
1930
    begin
1931
      test_fail("Data was read from PHY register with wrong PHY address - control register");
1932
      fail = fail + 1;
1933
    end
1934
    if(fail == 0)
1935
      test_ok;
1936
    else
1937
      fail = 0;
1938 169 mohor
  end
1939
 
1940
 
1941 181 mohor
  ////////////////////////////////////////////////////////////////////
1942
  ////                                                            ////
1943
  ////  Test writing to phy with wrong phy address and reading    ////
1944
  ////  from correct one                                          ////
1945
  ////                                                            ////
1946
  ////////////////////////////////////////////////////////////////////
1947
  if (test_num == 8) // 
1948 169 mohor
  begin
1949 194 tadej
    // TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
1950
    test_name   = "TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
1951
    `TIME; $display("  TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
1952 181 mohor
 
1953
    // set address
1954
    reg_addr = 5'h0; // control register
1955
    phy_addr = 5'h2; // wrong PHY address
1956
    // write request
1957
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1958
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1959
    check_mii_busy; // wait for write to finish
1960
 
1961
    phy_addr = 5'h1; // correct PHY address
1962
    // read request
1963
    #Tp mii_read_req(phy_addr, reg_addr);
1964
    check_mii_busy; // wait for read to finish
1965
    // read data
1966 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1967 181 mohor
    if (phy_data === tmp_data)
1968
    begin
1969
      test_fail("Data was written into PHY register with wrong PHY address - control register");
1970
      fail = fail + 1;
1971
    end
1972
    if(fail == 0)
1973
      test_ok;
1974
    else
1975
      fail = 0;
1976 169 mohor
  end
1977
 
1978
 
1979 181 mohor
  ////////////////////////////////////////////////////////////////////
1980
  ////                                                            ////
1981
  ////  Test sliding stop scan command immediately after read     ////
1982
  ////  request (with and without preamble)                       ////
1983
  ////                                                            ////
1984
  ////////////////////////////////////////////////////////////////////
1985
  if (test_num == 9) // 
1986 169 mohor
  begin
1987 194 tadej
    // TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
1988
    test_name = "TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
1989 181 mohor
    `TIME;
1990 194 tadej
    $display("  TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
1991 181 mohor
 
1992
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1993 169 mohor
    begin
1994 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
1995
      // MII mode register
1996
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1997
               wbm_subseq_waits);
1998
      i = 0;
1999
      cnt = 0;
2000
      while (i < 80) // delay for sliding of writing a STOP SCAN command
2001 169 mohor
      begin
2002 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after read will be finished
2003
        begin
2004
          // set address
2005
          reg_addr = 5'h0; // control register
2006
          phy_addr = 5'h1; // correct PHY address
2007
          cnt = 0;
2008
          // read request
2009
          #Tp mii_read_req(phy_addr, reg_addr);
2010
          fork
2011
            begin
2012
              repeat(i) @(posedge Mdc_O);
2013
              // write command 0x0 into MII command register
2014
              // MII command written while read in progress
2015
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2016
              @(posedge wb_clk);
2017
              #Tp check_mii_busy; // wait for read to finish
2018
            end
2019
            begin
2020
              // wait for serial bus to become active
2021
              wait(Mdio_IO !== 1'bz);
2022
              // count transfer length
2023
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2024
              begin
2025
                @(posedge Mdc_O);
2026
                #Tp cnt = cnt + 1;
2027
              end
2028
            end
2029
          join
2030
          // check transfer length
2031
          if (i2) // without preamble
2032 169 mohor
          begin
2033 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2034
            begin
2035
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2036
              fail = fail + 1;
2037
            end
2038 169 mohor
          end
2039 181 mohor
          else // with preamble
2040 169 mohor
          begin
2041 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2042
            begin
2043
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2044
              fail = fail + 1;
2045
            end
2046
          end
2047
          // check the BUSY signal to see if the bus is still IDLE
2048
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2049
            check_mii_busy; // wait for bus to become idle
2050
 
2051
          // try normal write or read after read was finished
2052
          #Tp phy_data = {8'h7D, (i[7:0] + 1)};
2053
          #Tp cnt = 0;
2054
          if (i3 == 0) // write after read
2055
          begin
2056
            // write request
2057
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2058 169 mohor
            // wait for serial bus to become active
2059
            wait(Mdio_IO !== 1'bz);
2060
            // count transfer length
2061 181 mohor
            while(Mdio_IO !== 1'bz)
2062 169 mohor
            begin
2063
              @(posedge Mdc_O);
2064
              #Tp cnt = cnt + 1;
2065
            end
2066 181 mohor
            @(posedge Mdc_O);
2067
            // read request
2068
            #Tp mii_read_req(phy_addr, reg_addr);
2069
            check_mii_busy; // wait for read to finish
2070
            // read and check data
2071 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2072 181 mohor
            if (phy_data !== tmp_data)
2073
            begin
2074
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2075
              fail = fail + 1;
2076
            end
2077 169 mohor
          end
2078 181 mohor
          else // read after read
2079 169 mohor
          begin
2080 181 mohor
            // read request
2081
            #Tp mii_read_req(phy_addr, reg_addr);
2082
            // wait for serial bus to become active
2083
            wait(Mdio_IO !== 1'bz);
2084
            // count transfer length
2085
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2086
            begin
2087
              @(posedge Mdc_O);
2088
              #Tp cnt = cnt + 1;
2089
            end
2090 169 mohor
            @(posedge Mdc_O);
2091 181 mohor
            check_mii_busy; // wait for read to finish
2092
            // read and check data
2093 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2094 181 mohor
            if (phy_data !== tmp_data)
2095
            begin
2096
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2097
              fail = fail + 1;
2098
            end
2099 169 mohor
          end
2100 181 mohor
          // check if transfer was a proper length
2101
          if (i2) // without preamble
2102 169 mohor
          begin
2103 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2104
            begin
2105
              test_fail("New request did not proceed correctly, after read request");
2106
              fail = fail + 1;
2107
            end
2108 169 mohor
          end
2109 181 mohor
          else // with preamble
2110 169 mohor
          begin
2111 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2112
            begin
2113
              test_fail("New request did not proceed correctly, after read request");
2114
              fail = fail + 1;
2115
            end
2116 169 mohor
          end
2117
        end
2118 181 mohor
        #Tp;
2119
        // set delay of writing the command
2120 169 mohor
        if (i2) // without preamble
2121
        begin
2122 181 mohor
          case(i)
2123
            0, 1:               i = i + 1;
2124
            18, 19, 20, 21, 22,
2125
            23, 24, 25, 26, 27,
2126
            28, 29, 30, 31, 32,
2127
            33, 34, 35:         i = i + 1;
2128
            36:                 i = 80;
2129
            default:            i = 18;
2130
          endcase
2131 169 mohor
        end
2132
        else // with preamble
2133
        begin
2134 181 mohor
          case(i)
2135
            0, 1:               i = i + 1;
2136
            50, 51, 52, 53, 54,
2137
            55, 56, 57, 58, 59,
2138
            60, 61, 62, 63, 64,
2139
            65, 66, 67:         i = i + 1;
2140
            68:                 i = 80;
2141
            default:            i = 50;
2142
          endcase
2143 169 mohor
        end
2144 181 mohor
        @(posedge wb_clk);
2145 169 mohor
      end
2146
    end
2147 181 mohor
    // set PHY to normal mode
2148
    #Tp eth_phy.preamble_suppresed(0);
2149
    // MII mode register
2150
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2151
    if(fail == 0)
2152
      test_ok;
2153
    else
2154
      fail = 0;
2155 169 mohor
  end
2156
 
2157
 
2158 181 mohor
  ////////////////////////////////////////////////////////////////////
2159
  ////                                                            ////
2160
  ////  Test sliding stop scan command immediately after write    ////
2161
  ////  request (with and without preamble)                       ////
2162
  ////                                                            ////
2163
  ////////////////////////////////////////////////////////////////////
2164
  if (test_num == 10) // 
2165 169 mohor
  begin
2166 194 tadej
    // TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
2167
    test_name = "TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
2168 181 mohor
    `TIME;
2169 194 tadej
    $display("  TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
2170 181 mohor
 
2171
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
2172 169 mohor
    begin
2173 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
2174
      // MII mode register
2175
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
2176
                wbm_subseq_waits);
2177
      i = 0;
2178
      cnt = 0;
2179
      while (i < 80) // delay for sliding of writing a STOP SCAN command
2180 169 mohor
      begin
2181 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after write will be finished
2182
        begin
2183
          // set address
2184
          reg_addr = 5'h0; // control register
2185
          phy_addr = 5'h1; // correct PHY address
2186
          cnt = 0;
2187
          // write request
2188
          phy_data = {8'h75, (i[7:0] + 1)};
2189
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2190
          fork
2191
            begin
2192
              repeat(i) @(posedge Mdc_O);
2193
              // write command 0x0 into MII command register
2194
              // MII command written while read in progress
2195
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2196
              @(posedge wb_clk);
2197
              #Tp check_mii_busy; // wait for write to finish
2198
            end
2199
            begin
2200
              // wait for serial bus to become active
2201
              wait(Mdio_IO !== 1'bz);
2202
              // count transfer length
2203
              while(Mdio_IO !== 1'bz)
2204
              begin
2205
                @(posedge Mdc_O);
2206
                #Tp cnt = cnt + 1;
2207
              end
2208
            end
2209
          join
2210
          // check transfer length
2211
          if (i2) // without preamble
2212 169 mohor
          begin
2213 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2214
            begin
2215
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2216
              fail = fail + 1;
2217
            end
2218 169 mohor
          end
2219 181 mohor
          else // with preamble
2220 169 mohor
          begin
2221 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2222
            begin
2223
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2224
              fail = fail + 1;
2225
            end
2226
          end
2227
          // check the BUSY signal to see if the bus is still IDLE
2228
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2229
            check_mii_busy; // wait for bus to become idle
2230
 
2231
          // try normal write or read after write was finished
2232
          #Tp cnt = 0;
2233
          if (i3 == 0) // write after write
2234
          begin
2235
            phy_data = {8'h7A, (i[7:0] + 1)};
2236
            // write request
2237
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2238 169 mohor
            // wait for serial bus to become active
2239
            wait(Mdio_IO !== 1'bz);
2240
            // count transfer length
2241
            while(Mdio_IO !== 1'bz)
2242
            begin
2243
              @(posedge Mdc_O);
2244
              #Tp cnt = cnt + 1;
2245
            end
2246 181 mohor
            @(posedge Mdc_O);
2247
            // read request
2248
            #Tp mii_read_req(phy_addr, reg_addr);
2249
            check_mii_busy; // wait for read to finish
2250
            // read and check data
2251 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2252 181 mohor
            if (phy_data !== tmp_data)
2253
            begin
2254
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2255
              fail = fail + 1;
2256
            end
2257 169 mohor
          end
2258 181 mohor
          else // read after write
2259 169 mohor
          begin
2260 181 mohor
            // read request
2261
            #Tp mii_read_req(phy_addr, reg_addr);
2262
            // wait for serial bus to become active
2263
            wait(Mdio_IO !== 1'bz);
2264
            // count transfer length
2265
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2266
            begin
2267
              @(posedge Mdc_O);
2268
              #Tp cnt = cnt + 1;
2269
            end
2270 169 mohor
            @(posedge Mdc_O);
2271 181 mohor
            check_mii_busy; // wait for read to finish
2272
            // read and check data
2273 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2274 181 mohor
            if (phy_data !== tmp_data)
2275
            begin
2276
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2277
              fail = fail + 1;
2278
            end
2279 169 mohor
          end
2280 181 mohor
          // check if transfer was a proper length
2281
          if (i2) // without preamble
2282 169 mohor
          begin
2283 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2284
            begin
2285
              test_fail("New request did not proceed correctly, after write request");
2286
              fail = fail + 1;
2287
            end
2288 169 mohor
          end
2289 181 mohor
          else // with preamble
2290 169 mohor
          begin
2291 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2292
            begin
2293
              test_fail("New request did not proceed correctly, after write request");
2294
              fail = fail + 1;
2295
            end
2296 169 mohor
          end
2297
        end
2298 181 mohor
        #Tp;
2299
        // set delay of writing the command
2300 169 mohor
        if (i2) // without preamble
2301
        begin
2302 181 mohor
          case(i)
2303
            0, 1:               i = i + 1;
2304
            18, 19, 20, 21, 22,
2305
            23, 24, 25, 26, 27,
2306
            28, 29, 30, 31, 32,
2307
            33, 34, 35:         i = i + 1;
2308
            36:                 i = 80;
2309
            default:            i = 18;
2310
          endcase
2311 169 mohor
        end
2312
        else // with preamble
2313
        begin
2314 181 mohor
          case(i)
2315
            0, 1:               i = i + 1;
2316
            50, 51, 52, 53, 54,
2317
            55, 56, 57, 58, 59,
2318
            60, 61, 62, 63, 64,
2319
            65, 66, 67:         i = i + 1;
2320
            68:                 i = 80;
2321
            default:            i = 50;
2322
          endcase
2323 169 mohor
        end
2324 181 mohor
        @(posedge wb_clk);
2325 169 mohor
      end
2326
    end
2327 181 mohor
    // set PHY to normal mode
2328
    #Tp eth_phy.preamble_suppresed(0);
2329
    // MII mode register
2330
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2331
    if(fail == 0)
2332
      test_ok;
2333
    else
2334
      fail = 0;
2335 169 mohor
  end
2336
 
2337
 
2338 181 mohor
  ////////////////////////////////////////////////////////////////////
2339
  ////                                                            ////
2340
  ////  Test busy and nvalid status durations during write (with  ////
2341
  ////  and without preamble)                                     ////
2342
  ////                                                            ////
2343
  ////////////////////////////////////////////////////////////////////
2344
  if (test_num == 11) // 
2345 169 mohor
  begin
2346 194 tadej
    // TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
2347
    test_name   = "TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
2348
    `TIME; $display("  TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
2349 181 mohor
 
2350
    reset_mii; // reset MII
2351
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2352
    #Tp eth_phy.link_up_down(1);
2353
    // set the MII
2354
    clk_div = 64;
2355
    mii_set_clk_div(clk_div[7:0]);
2356
    // set address
2357
    reg_addr = 5'h1; // status register
2358
    phy_addr = 5'h1; // correct PHY address
2359
 
2360
    for (i = 0; i <= 1; i = i + 1)
2361 169 mohor
    begin
2362 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2363
      // MII mode register
2364
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2365
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2366
      @(posedge Mdc_O);
2367
      // write request
2368
      #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);
2369
      // read data from MII status register - Busy and Nvalid bits
2370 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2371 181 mohor
 
2372
      // check MII IO signal and Busy and Nvalid bits
2373
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2374 169 mohor
      begin
2375 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2376
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2377
        begin
2378
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2379
          fail = fail + 1;
2380
        end
2381
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2382
        begin
2383
          test_fail("Nvalid signal was set during write");
2384
          fail = fail + 1;
2385
        end
2386 169 mohor
      end
2387 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2388 169 mohor
      begin
2389 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2390
        begin
2391
          test_fail("Busy signal should be set after write, due to reads from MII status register");
2392
          fail = fail + 1;
2393
        end
2394
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2395
        begin
2396
          test_fail("Nvalid signal was set during write");
2397
          fail = fail + 1;
2398
        end
2399 169 mohor
      end
2400 181 mohor
 
2401
      // wait for serial bus to become active
2402
      wait(Mdio_IO !== 1'bz);
2403
      // count transfer bits
2404
      if (i)
2405 169 mohor
      begin
2406 181 mohor
        repeat(32) @(posedge Mdc_O);
2407 169 mohor
      end
2408 181 mohor
      else
2409 169 mohor
      begin
2410 181 mohor
        repeat(64) @(posedge Mdc_O);
2411 169 mohor
      end
2412 181 mohor
      // read data from MII status register - Busy and Nvalid bits
2413 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2414 181 mohor
 
2415
      // check MII IO signal and Busy and Nvalid bits
2416
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2417 169 mohor
      begin
2418 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2419
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2420
        begin
2421
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2422
          fail = fail + 1;
2423
        end
2424
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2425
        begin
2426
          test_fail("Nvalid signal was set during write");
2427
          fail = fail + 1;
2428
        end
2429 169 mohor
      end
2430 181 mohor
      else // Busy bit should still be set to '1'
2431 169 mohor
      begin
2432 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2433
        begin
2434
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2435
          fail = fail + 1;
2436
        end
2437
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2438
        begin
2439
          test_fail("Nvalid signal was set during write");
2440
          fail = fail + 1;
2441
        end
2442 169 mohor
      end
2443 181 mohor
 
2444
      // wait for next negative clock edge
2445
      @(negedge Mdc_O);
2446 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2447 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2448 181 mohor
 
2449 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2450
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2451
      begin
2452
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2453
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2454
        begin
2455
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2456
          fail = fail + 1;
2457
        end
2458
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2459
        begin
2460
          test_fail("Nvalid signal was set during write");
2461
          fail = fail + 1;
2462
        end
2463
      end
2464 181 mohor
      else // Busy bit should still be set to '1'
2465 169 mohor
      begin
2466
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2467
        begin
2468 181 mohor
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2469
          fail = fail + 1;
2470 169 mohor
        end
2471 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2472 169 mohor
        begin
2473 181 mohor
          test_fail("Nvalid signal was set during write");
2474
          fail = fail + 1;
2475
        end
2476
      end
2477
 
2478
      // wait for Busy to become inactive
2479
      i1 = 0;
2480
      while (i1 <= 2)
2481
      begin
2482
        // wait for next positive clock edge
2483
        @(posedge Mdc_O);
2484
        // read data from MII status register - Busy and Nvalid bits
2485 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2486 181 mohor
 
2487
        // check MII IO signal and Busy and Nvalid bits
2488
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2489
        begin
2490
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2491
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2492 169 mohor
          begin
2493 181 mohor
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2494 169 mohor
            fail = fail + 1;
2495
          end
2496 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2497
          begin
2498
            test_fail("Nvalid signal was set during write");
2499
            fail = fail + 1;
2500
          end
2501 169 mohor
        end
2502 181 mohor
        else // wait for Busy bit to be set to '0'
2503 169 mohor
        begin
2504 181 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2505
          begin
2506
            i1 = 3; // end of Busy checking
2507
          end
2508
          else
2509
          begin
2510
            if (i1 == 2)
2511
            begin
2512
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2513
              fail = fail + 1;
2514
            end
2515
            #Tp i1 = i1 + 1;
2516
          end
2517
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2518
          begin
2519
            test_fail("Nvalid signal was set after write");
2520
            fail = fail + 1;
2521
          end
2522 169 mohor
        end
2523
      end
2524
    end
2525 181 mohor
    // set PHY to normal mode
2526
    #Tp eth_phy.preamble_suppresed(0);
2527
    // MII mode register
2528
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2529
    if(fail == 0)
2530
      test_ok;
2531
    else
2532
      fail = 0;
2533 116 mohor
  end
2534
 
2535
 
2536 181 mohor
  ////////////////////////////////////////////////////////////////////
2537
  ////                                                            ////
2538
  ////  Test busy and nvalid status durations during write (with  ////
2539
  ////  and without preamble)                                     ////
2540
  ////                                                            ////
2541
  ////////////////////////////////////////////////////////////////////
2542
  if (test_num == 12) // 
2543 169 mohor
  begin
2544 194 tadej
    // TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
2545
    test_name   = "TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
2546
    `TIME; $display("  TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
2547 181 mohor
 
2548
    reset_mii; // reset MII
2549
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2550
    #Tp eth_phy.link_up_down(1);
2551
    // set the MII
2552
    clk_div = 64;
2553
    mii_set_clk_div(clk_div[7:0]);
2554
    // set address
2555
    reg_addr = 5'h1; // status register
2556
    phy_addr = 5'h1; // correct PHY address
2557
 
2558
    for (i = 0; i <= 1; i = i + 1)
2559 169 mohor
    begin
2560 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2561
      // MII mode register
2562
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2563
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2564 169 mohor
      @(posedge Mdc_O);
2565 181 mohor
      // read request
2566
      #Tp mii_read_req(phy_addr, reg_addr);
2567 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2568 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2569 181 mohor
 
2570 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2571
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2572
      begin
2573 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2574 169 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2575
        begin
2576 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2577 169 mohor
          fail = fail + 1;
2578
        end
2579
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2580
        begin
2581
          test_fail("Nvalid signal was set during read");
2582
          fail = fail + 1;
2583
        end
2584
      end
2585 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2586 169 mohor
      begin
2587
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2588
        begin
2589 181 mohor
          test_fail("Busy signal should be set after read, due to reads from MII status register");
2590
          fail = fail + 1;
2591 169 mohor
        end
2592
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2593
        begin
2594 181 mohor
          test_fail("Nvalid signal was set during read");
2595 169 mohor
          fail = fail + 1;
2596
        end
2597
      end
2598 181 mohor
 
2599
      // wait for serial bus to become active
2600
      wait(Mdio_IO !== 1'bz);
2601
      // count transfer bits
2602
      if (i)
2603 169 mohor
      begin
2604 181 mohor
        repeat(31) @(posedge Mdc_O);
2605 169 mohor
      end
2606 181 mohor
      else
2607 169 mohor
      begin
2608 181 mohor
        repeat(63) @(posedge Mdc_O);
2609 169 mohor
      end
2610 181 mohor
      // wait for next negative clock edge
2611
      @(negedge Mdc_O);
2612
      // read data from MII status register - Busy and Nvalid bits
2613 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2614 181 mohor
 
2615
      // check MII IO signal and Busy and Nvalid bits
2616
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2617 169 mohor
      begin
2618 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2619
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2620
        begin
2621
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2622
          fail = fail + 1;
2623
        end
2624
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2625
        begin
2626
          test_fail("Nvalid signal was set during read");
2627
          fail = fail + 1;
2628
        end
2629 169 mohor
      end
2630 181 mohor
      else // Busy bit should still be set to '1'
2631 169 mohor
      begin
2632 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2633
        begin
2634
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2635
          fail = fail + 1;
2636
        end
2637
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2638
        begin
2639
          test_fail("Nvalid signal was set during read");
2640
          fail = fail + 1;
2641
        end
2642 169 mohor
      end
2643 181 mohor
 
2644 169 mohor
      // wait for next positive clock edge
2645
      @(posedge Mdc_O);
2646
      // read data from MII status register - Busy and Nvalid bits
2647 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2648 181 mohor
 
2649 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2650
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2651
      begin
2652
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2653 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2654 169 mohor
        begin
2655 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2656
          fail = fail + 1;
2657
        end
2658
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2659
        begin
2660
          test_fail("Nvalid signal was set during read");
2661
          fail = fail + 1;
2662
        end
2663
      end
2664
      else // Busy bit should still be set to '1'
2665
      begin
2666
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2667
        begin
2668
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2669
          fail = fail + 1;
2670
        end
2671
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2672
        begin
2673
          test_fail("Nvalid signal was set during read");
2674
          fail = fail + 1;
2675
        end
2676
      end
2677
 
2678
      // wait for Busy to become inactive
2679
      i1 = 0;
2680
      while (i1 <= 2)
2681
      begin
2682
        // wait for next positive clock edge
2683
        @(posedge Mdc_O);
2684
        // read data from MII status register - Busy and Nvalid bits
2685 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2686 181 mohor
 
2687
        // check MII IO signal and Busy and Nvalid bits
2688
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2689
        begin
2690
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2691 169 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2692
          begin
2693
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2694
            fail = fail + 1;
2695
          end
2696 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2697 169 mohor
          begin
2698 181 mohor
            test_fail("Nvalid signal was set during read");
2699 169 mohor
            fail = fail + 1;
2700
          end
2701
        end
2702 181 mohor
        else // wait for Busy bit to be set to '0'
2703 169 mohor
        begin
2704
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2705
          begin
2706
            i1 = 3; // end of Busy checking
2707
          end
2708
          else
2709
          begin
2710
            if (i1 == 2)
2711
            begin
2712
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2713
              fail = fail + 1;
2714
            end
2715
            #Tp i1 = i1 + 1;
2716
          end
2717 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2718 169 mohor
          begin
2719 181 mohor
            test_fail("Nvalid signal was set after read");
2720 169 mohor
            fail = fail + 1;
2721
          end
2722
        end
2723
      end
2724
    end
2725 181 mohor
    // set PHY to normal mode
2726
    #Tp eth_phy.preamble_suppresed(0);
2727
    // MII mode register
2728
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2729
    if(fail == 0)
2730
      test_ok;
2731
    else
2732
      fail = 0;
2733 169 mohor
  end
2734
 
2735
 
2736 181 mohor
  ////////////////////////////////////////////////////////////////////
2737
  ////                                                            ////
2738
  ////  Test busy and nvalid status durations during scan (with   ////
2739
  ////  and without preamble)                                     ////
2740
  ////                                                            ////
2741
  ////////////////////////////////////////////////////////////////////
2742
  if (test_num == 13) // 
2743 169 mohor
  begin
2744 194 tadej
    // TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
2745
    test_name   = "TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
2746
    `TIME; $display("  TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
2747 181 mohor
 
2748
    reset_mii; // reset MII
2749
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2750
    #Tp eth_phy.link_up_down(1);
2751
    // set the MII
2752
    clk_div = 64;
2753
    mii_set_clk_div(clk_div[7:0]);
2754
    // set address
2755
    reg_addr = 5'h1; // status register
2756
    phy_addr = 5'h1; // correct PHY address
2757
 
2758
    for (i = 0; i <= 1; i = i + 1)
2759 169 mohor
    begin
2760 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2761
      // MII mode register
2762
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2763
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2764
      @(posedge Mdc_O);
2765
      // scan request
2766
      #Tp mii_scan_req(phy_addr, reg_addr);
2767
      // read data from MII status register - Busy and Nvalid bits
2768 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2769 181 mohor
 
2770
      // check MII IO signal and Busy and Nvalid bits
2771
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2772 169