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[/] [ethmac/] [trunk/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 338

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1 169 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  File name "wb_bus_mon.v"                                    ////
4
////                                                              ////
5 315 tadejm
////  This file is part of the "PCI bridge" project               ////
6
////  http://www.opencores.org/cores/pci/                         ////
7 169 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9 315 tadejm
////      - mihad@opencores.org                                   ////
10
////      - Miha Dolenc                                           ////
11 169 mohor
////                                                              ////
12 315 tadejm
////  All additional information is avaliable in the README.pdf   ////
13 169 mohor
////  file.                                                       ////
14
////                                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18 315 tadejm
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
19 169 mohor
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 315 tadejm
// Revision 1.3  2002/10/09 13:16:51  tadejm
47
// Just back-up; not completed testbench and some testcases are not
48
// wotking properly yet.
49
//
50 209 tadejm
// Revision 1.2  2002/09/13 12:29:14  mohor
51
// Headers changed.
52
//
53 170 mohor
// Revision 1.1  2002/09/13 11:57:20  mohor
54
// New testbench. Thanks to Tadej M - "The Spammer".
55
//
56 169 mohor
// Revision 1.1  2002/02/01 13:39:43  mihad
57
// Initial testbench import. Still under development
58
//
59
// Revision 1.1  2001/08/06 18:12:58  mihad
60
// Pocasi delamo kompletno zadevo
61
//
62
//
63
 
64 209 tadejm
`include "timescale.v"
65 169 mohor
`include "wb_model_defines.v"
66
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
67
// monitors for any illegal combinations appearing on the bus.
68
module WB_BUS_MON(
69
                    CLK_I,
70
                    RST_I,
71
                    ACK_I,
72
                    ADDR_O,
73
                    CYC_O,
74
                    DAT_I,
75
                    DAT_O,
76
                    ERR_I,
77
                    RTY_I,
78
                    SEL_O,
79
                    STB_O,
80
                    WE_O,
81
                    TAG_I,
82
                    TAG_O,
83
                    CAB_O,
84 315 tadejm
                    check_CTI,
85 169 mohor
                    log_file_desc
86
                  ) ;
87
 
88
input                           CLK_I  ;
89
input                           RST_I  ;
90
input                           ACK_I  ;
91
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
92
input                           CYC_O  ;
93
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
94
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
95
input                           ERR_I  ;
96
input                           RTY_I  ;
97
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
98
input                           STB_O  ;
99
input                           WE_O   ;
100
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
101
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
102
input                           CAB_O  ;
103 315 tadejm
input                           check_CTI ;
104 169 mohor
input [31:0] log_file_desc ;
105
 
106 315 tadejm
always@(posedge CLK_I)
107 169 mohor
begin
108 315 tadejm
    if (RST_I !== 1'b0)
109 169 mohor
    begin
110
        // when reset is applied, all control signals must be low
111 315 tadejm
        if (CYC_O !== 1'b0)
112 169 mohor
        begin
113 315 tadejm
            message_out("CYC_O active under reset") ;
114 169 mohor
        end
115 315 tadejm
 
116
        if (STB_O !== 1'b0)
117 169 mohor
        begin
118 315 tadejm
            message_out("STB_O active under reset") ;
119 169 mohor
        end
120 315 tadejm
 
121
        if (ACK_I !== 1'b0)
122
            message_out("ACK_I active under reset") ;
123
 
124
        if (ERR_I !== 1'b0)
125 169 mohor
        begin
126 315 tadejm
            message_out("ERR_I active under reset") ;
127 169 mohor
        end
128 315 tadejm
 
129
        if (RTY_I !== 1'b0)
130 169 mohor
        begin
131 315 tadejm
            message_out("RTY_I active under reset") ;
132 169 mohor
        end
133 315 tadejm
 
134 169 mohor
    end // reset
135
    else
136 315 tadejm
    if (CYC_O !== 1'b1)
137 169 mohor
    begin
138
        // when cycle indicator is low, all control signals must be low
139 315 tadejm
        if (STB_O !== 1'b0)
140 169 mohor
        begin
141 315 tadejm
            message_out("STB_O active without CYC_O being active") ;
142 169 mohor
        end
143 315 tadejm
 
144
        if (ACK_I !== 1'b0)
145 169 mohor
        begin
146 315 tadejm
            message_out("ACK_I active without CYC_O being active") ;
147 169 mohor
        end
148 315 tadejm
 
149
        if (ERR_I !== 1'b0)
150 169 mohor
        begin
151 315 tadejm
            message_out("ERR_I active without CYC_O being active") ;
152 169 mohor
        end
153 315 tadejm
 
154
        if (RTY_I !== 1'b0)
155 169 mohor
        begin
156 315 tadejm
            message_out("RTY_I active without CYC_O being active") ;
157 169 mohor
        end
158 315 tadejm
 
159 169 mohor
    end // ~CYC_O
160
end
161
 
162 315 tadejm
reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
163
reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
164 169 mohor
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
165
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
166 315 tadejm
reg [`WB_TAG_WIDTH-1:0] previous_tag ;
167 169 mohor
reg                     previous_stb ;
168
reg                     previous_ack ;
169
reg                     previous_err ;
170
reg                     previous_rty ;
171
reg                     previous_cyc ;
172 315 tadejm
reg                     previous_we  ;
173 169 mohor
 
174
always@(posedge CLK_I or posedge RST_I)
175
begin
176
    if (RST_I)
177
    begin
178 315 tadejm
        previous_stb        <= 1'b0 ;
179
        previous_ack        <= 1'b0 ;
180
        previous_err        <= 1'b0 ;
181
        previous_rty        <= 1'b0 ;
182
        previous_cyc        <= 1'b0 ;
183
        previous_tag        <= 'd0  ;
184
        previous_we         <= 1'b0 ;
185
        previous_data_o     <= 0    ;
186
        previous_data_i     <= 0    ;
187
        previous_address    <= 0    ;
188
        previous_sel        <= 0    ;
189 169 mohor
    end
190
    else
191
    begin
192 315 tadejm
        previous_stb        <= STB_O    ;
193
        previous_ack        <= ACK_I    ;
194
        previous_err        <= ERR_I    ;
195
        previous_rty        <= RTY_I    ;
196
        previous_cyc        <= CYC_O    ;
197
        previous_tag        <= TAG_O    ;
198
        previous_we         <= WE_O     ;
199
        previous_data_o     <= DAT_O    ;
200
        previous_data_i     <= DAT_I    ;
201
        previous_address    <= ADDR_O   ;
202
        previous_sel        <= SEL_O    ;
203 169 mohor
    end
204
end
205
 
206
// cycle monitor
207
always@(posedge CLK_I)
208 315 tadejm
begin:cycle_monitor_blk
209
    reg master_can_change ;
210
    reg slave_can_change  ;
211
 
212
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
213 169 mohor
    begin
214 315 tadejm
        // check for two control signals active at same edge
215
        if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
216 169 mohor
        begin
217 315 tadejm
            message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
218
        end
219 169 mohor
 
220 315 tadejm
        if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
221
        begin
222
            message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
223
        end
224 169 mohor
 
225 315 tadejm
        if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
226
        begin
227
            message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
228
        end
229 169 mohor
 
230 315 tadejm
        if (previous_cyc === 1'b1)
231
        begin
232
            if (previous_stb === 1'b1)
233
            begin
234
                if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
235
                    master_can_change = 1'b1 ;
236
                else
237
                    master_can_change = 1'b0 ;
238 169 mohor
            end
239
            else
240
            begin
241 315 tadejm
                master_can_change = 1'b1 ;
242 169 mohor
            end
243
 
244 315 tadejm
            if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
245 169 mohor
            begin
246 315 tadejm
                if (previous_stb === 1'b1)
247
                    slave_can_change = 1'b1 ;
248
                else
249
                    slave_can_change = 1'b0 ;
250 169 mohor
            end
251 315 tadejm
            else
252 169 mohor
            begin
253 315 tadejm
                slave_can_change = 1'b1 ;
254 169 mohor
            end
255 315 tadejm
        end
256
        else
257
        begin
258
            master_can_change = 1'b1 ;
259
            slave_can_change  = 1'b1 ;
260
        end
261
    end
262
    else
263
    begin
264
        master_can_change = 1'b1 ;
265
        slave_can_change  = 1'b1 ;
266
    end
267 169 mohor
 
268 315 tadejm
    if (master_can_change !== 1'b1)
269
    begin
270
        if (CYC_O !== previous_cyc)
271
        begin
272
            message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
273
        end
274
 
275
        if (STB_O !== previous_stb)
276
        begin
277
            message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
278
        end
279
 
280
        if (TAG_O !== previous_tag)
281
        begin
282
            message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
283
        end
284
 
285
        if (ADDR_O !== previous_address)
286
        begin
287
            message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
288
        end
289
 
290
        if (SEL_O !== previous_sel)
291
        begin
292
            message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
293
        end
294
 
295
        if (WE_O !== previous_we)
296
        begin
297
            message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
298
        end
299
 
300
        if (WE_O !== 1'b0)
301
        begin
302
            if (DAT_O !== previous_data_o)
303 169 mohor
            begin
304 315 tadejm
                message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
305 169 mohor
            end
306 315 tadejm
        end
307
    end
308 169 mohor
 
309 315 tadejm
    if (slave_can_change !== 1'b1)
310 169 mohor
    begin
311 315 tadejm
        if (previous_ack !== ACK_I)
312 169 mohor
        begin
313 315 tadejm
            message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
314 169 mohor
        end
315 315 tadejm
 
316
        if (previous_rty !== RTY_I)
317
        begin
318
            message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
319
        end
320
 
321
        if (previous_err !== ERR_I)
322
        begin
323
            message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
324
        end
325
 
326
        if (previous_data_i !== DAT_I)
327
        begin
328
            message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
329
        end
330 169 mohor
    end
331
end // cycle monitor
332
 
333
// CAB_O monitor - CAB_O musn't change during one cycle
334
reg [1:0] first_cab_val ;
335
always@(posedge CLK_I or RST_I)
336
begin
337
    if ((CYC_O === 0) || RST_I)
338
        first_cab_val <= 2'b00 ;
339
    else
340
    begin
341
        // cycle in progress - is this first clock edge in a cycle ?
342
        if (first_cab_val[1] === 1'b0)
343
            first_cab_val <= {1'b1, CAB_O} ;
344
        else if ( first_cab_val[0] !== CAB_O )
345
        begin
346 315 tadejm
            $display("CAB_O value changed during cycle") ;
347
            $fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
348 169 mohor
        end
349
    end
350
end // CAB_O monitor
351
 
352 315 tadejm
// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts
353
reg [2:0] first_cti_val ;
354
always@(posedge CLK_I or posedge RST_I)
355
begin
356
    if (RST_I)
357
        first_cti_val <= 3'b000 ;
358
    // logging for burst cycle
359
    else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty || previous_err)))
360
    begin
361
        message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;
362
        $display("CTI_O didn't change to '111' when end of burst") ;
363
        $fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;
364
        first_cti_val <= 3'b000 ;
365
    end
366
    else if (CYC_O === 0)
367
        first_cti_val <= 3'b000 ;
368
    else
369
    begin
370
        if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I || ERR_I || RTY_I))
371
            first_cti_val <= 3'b001 ;
372
        else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
373
            first_cti_val <= 3'b010 ;
374
        else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I || ERR_I || RTY_I))
375
            first_cti_val <= 3'b011 ;
376
        else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
377
            first_cti_val <= 3'b010 ;
378
        // logging for clasic cycles
379
        else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))
380
        begin
381
            message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;
382
            $display("CTI_O change during CYC_O when clasic cycle") ;
383
            $fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;
384
        end
385
        // logging for end of burs cycle
386
        else if (check_CTI && (first_cti_val == 3'b010))
387
        begin
388
            message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;
389
            $display("CTI_O change to '111' before end of burst") ;
390
            $fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;
391
        end
392
    end
393
end
394
 
395 169 mohor
// WE_O monitor for consecutive address bursts
396
reg [1:0] first_we_val ;
397
always@(posedge CLK_I or posedge RST_I)
398
begin
399
    if (~CYC_O || ~CAB_O || RST_I)
400
        first_we_val <= 2'b00 ;
401
    else
402
    if (STB_O)
403
    begin
404
        // cycle in progress - is this first clock edge in a cycle ?
405
        if (first_we_val[1] == 1'b0)
406
            first_we_val <= {1'b1, WE_O} ;
407
        else if ( first_we_val[0] != WE_O )
408
        begin
409 315 tadejm
            $display("WE_O value changed during CAB cycle") ;
410
            $fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
411 169 mohor
        end
412
    end
413
end // CAB_O monitor
414
 
415
// address monitor for consecutive address bursts
416
reg [`WB_ADDR_WIDTH:0] address ;
417
always@(posedge CLK_I or posedge RST_I)
418
begin
419
    if (~CYC_O || ~CAB_O || RST_I)
420
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
421
    else
422
    begin
423
        if (STB_O && ACK_I)
424
        begin
425
            if (address[`WB_ADDR_WIDTH] == 1'b0)
426 315 tadejm
            begin
427
                address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
428
            end
429 169 mohor
            else
430
            begin
431
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
432
                begin
433 315 tadejm
                    $display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
434
                    message_out("Consecutive address burst address incrementing incorrect") ;
435 169 mohor
                end
436
                else
437 315 tadejm
                    address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
438 169 mohor
            end
439
        end
440
    end
441
end // address monitor
442
 
443
// data monitor
444
always@(posedge CLK_I or posedge RST_I)
445 315 tadejm
begin:data_monitor_blk
446
    reg                       last_valid_we     ;
447
    reg [`WB_SEL_WIDTH - 1:0] last_valid_sel    ;
448
 
449
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
450 169 mohor
    begin
451 315 tadejm
        if (STB_O !== 1'b0)
452 169 mohor
        begin
453 315 tadejm
            last_valid_we   = WE_O  ;
454
            last_valid_sel  = SEL_O ;
455
 
456
            if ( (ADDR_O ^ ADDR_O) !== 0 )
457 169 mohor
            begin
458 315 tadejm
                message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
459 169 mohor
            end
460 315 tadejm
 
461
            if ( (SEL_O ^ SEL_O) !== 0 )
462
            begin
463
                message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
464
            end
465 169 mohor
 
466 315 tadejm
            if ( WE_O )
467
            begin
468
                if (
469
                    ( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
470
                    ( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
471
                    ( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
472
                    ( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
473
                   )
474
                begin
475
                    message_out("Master provided invalid data during write and qualified it with STB_O") ;
476
                    $display("Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
477
                    $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
478
                end
479
            end
480
 
481
            if ((TAG_O ^ TAG_O) !== 0)
482
            begin
483
                message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
484
            end
485 169 mohor
        end
486 315 tadejm
 
487
        if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
488 169 mohor
        begin
489
            if (
490 315 tadejm
                ( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
491
                ( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
492
                ( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
493
                ( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
494 169 mohor
               )
495
            begin
496 315 tadejm
                message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
497
                $display("Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
498
                $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
499 169 mohor
            end
500
        end
501
    end
502 315 tadejm
    else
503
    begin
504
        last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
505
        last_valid_we  = 1'bx ;
506
    end
507 169 mohor
end
508
 
509 315 tadejm
task message_out ;
510
    input [7999:0] message_i ;
511 169 mohor
begin
512 315 tadejm
    $display("Time: %t", $time) ;
513
    $display("%m, %0s", message_i) ;
514
    $fdisplay(log_file_desc, "Time: %t", $time) ;
515
    $fdisplay(log_file_desc, "%m, %0s", message_i) ;
516 169 mohor
end
517 315 tadejm
endtask // display message
518
 
519 169 mohor
endmodule // BUS_MON

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