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[/] [ethmac/] [trunk/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 346

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1 169 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  File name "wb_master_behavioral.v"                          ////
4
////                                                              ////
5 170 mohor
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 169 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Miha Dolenc (mihad@opencores.org)                     ////
10
////                                                              ////
11 170 mohor
////  All additional information is available in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14 169 mohor
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 170 mohor
//// Copyright (C) 2002  Authors                                  ////
17 169 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 170 mohor
// Revision 1.1  2002/09/13 11:57:20  mohor
45
// New testbench. Thanks to Tadej M - "The Spammer".
46
//
47 169 mohor
// Revision 1.1  2002/07/29 11:25:20  mihad
48
// Adding test bench for memory interface
49
//
50
// Revision 1.1  2002/02/01 13:39:43  mihad
51
// Initial testbench import. Still under development
52
//
53
 
54
`include "wb_model_defines.v"
55
`include "timescale.v"
56
module WB_MASTER_BEHAVIORAL
57
(
58
    CLK_I,
59
    RST_I,
60
    TAG_I,
61
    TAG_O,
62
    ACK_I,
63
    ADR_O,
64
    CYC_O,
65
    DAT_I,
66
    DAT_O,
67
    ERR_I,
68
    RTY_I,
69
    SEL_O,
70
    STB_O,
71
    WE_O,
72
    CAB_O
73
);
74
 
75
    input                    CLK_I;
76
    input                    RST_I;
77
    input    `WB_TAG_TYPE    TAG_I;
78
    output   `WB_TAG_TYPE    TAG_O;
79
    input                    ACK_I;
80
    output   `WB_ADDR_TYPE   ADR_O;
81
    output                   CYC_O;
82
    input    `WB_DATA_TYPE   DAT_I;
83
    output   `WB_DATA_TYPE   DAT_O;
84
    input                    ERR_I;
85
    input                    RTY_I;
86
    output   `WB_SEL_TYPE    SEL_O;
87
    output                   STB_O;
88
    output                   WE_O;
89
    output                   CAB_O;
90
 
91
// instantiate low level master module
92
WB_MASTER32 wbm_low_level
93
(
94
    .CLK_I(CLK_I),
95
    .RST_I(RST_I),
96
    .TAG_I(TAG_I),
97
    .TAG_O(TAG_O),
98
    .ACK_I(ACK_I),
99
    .ADR_O(ADR_O),
100
    .CYC_O(CYC_O),
101
    .DAT_I(DAT_I),
102
    .DAT_O(DAT_O),
103
    .ERR_I(ERR_I),
104
    .RTY_I(RTY_I),
105
    .SEL_O(SEL_O),
106
    .STB_O(STB_O),
107
    .WE_O(WE_O),
108
    .CAB_O(CAB_O)
109
) ;
110
 
111
// block read and write buffers definition
112
// single write buffer
113
reg `WRITE_STIM_TYPE  blk_write_data    [0:(`MAX_BLK_SIZE - 1)] ;
114
// read stimulus buffer - addresses, tags, selects etc.
115
reg `READ_STIM_TYPE   blk_read_data_in  [0:(`MAX_BLK_SIZE - 1)] ;
116
// read return buffer - data and tags received while performing block reads
117
reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
118
 
119
// single write task
120
task wb_single_write ;
121
    input `WRITE_STIM_TYPE write_data ;
122
    input `WB_TRANSFER_FLAGS   write_flags ;
123
    inout `WRITE_RETURN_TYPE return ;
124
    reg in_use ;
125
    reg cab ;
126
    reg ok ;
127
    integer cyc_count ;
128
    integer rty_count ;
129
    reg retry ;
130
begin:main
131
 
132
    return`TB_ERROR_BIT = 1'b0 ;
133
    cab = 0 ;
134
    return`CYC_ACTUAL_TRANSFER = 0 ;
135
    rty_count = 0 ;
136
 
137
    // check if task was called before previous call finished
138
    if ( in_use === 1 )
139
    begin
140
        $display("*E, wb_single_write routine re-entered! Time %t ", $time) ;
141
        return`TB_ERROR_BIT = 1'b1 ;
142
        disable main ;
143
    end
144
 
145
    in_use = 1 ;
146
 
147
    retry = 1 ;
148
 
149
    while (retry === 1)
150
    begin
151
        // synchronize operation to clock
152
        @(posedge CLK_I) ;
153
 
154
        wbm_low_level.start_cycle(cab, 1'b1, ok) ;
155
        if ( ok !== 1 )
156
        begin
157
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
158
            return`TB_ERROR_BIT = 1'b1 ;
159
            disable main ;
160
        end
161
 
162
        // first insert initial wait states
163
        cyc_count = write_flags`INIT_WAITS ;
164
        while ( cyc_count > 0 )
165
        begin
166
            @(posedge CLK_I) ;
167
            cyc_count = cyc_count - 1 ;
168
        end
169
 
170
        wbm_low_level.wbm_write(write_data, return) ;
171
 
172
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
173
        begin
174
            if ( rty_count === `WB_TB_MAX_RTY )
175
            begin
176
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
177
                 retry = 0 ;
178
            end
179
            else
180
            begin
181
                retry     = 1 ;
182
                rty_count = rty_count + 1 ;
183
            end
184
        end
185
        else
186
            retry = 0 ;
187
 
188
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
189
        if ( return`TB_ERROR_BIT !== 0 )
190
        begin
191
            @(posedge CLK_I) ;
192
            wbm_low_level.end_cycle ;
193
            disable main ;
194
        end
195
 
196
        cyc_count = write_flags`SUBSEQ_WAITS ;
197
        while ( cyc_count > 0 )
198
        begin
199
            @(posedge CLK_I) ;
200
            cyc_count = cyc_count - 1 ;
201
        end
202
 
203
        wbm_low_level.end_cycle ;
204
    end
205
 
206
    in_use = 0 ;
207
 
208
end //main
209
endtask // wb_single_write
210
 
211
task wb_single_read ;
212
    input `READ_STIM_TYPE read_data ;
213
    input `WB_TRANSFER_FLAGS   read_flags ;
214
    inout `READ_RETURN_TYPE return ;
215
    reg in_use ;
216
    reg cab ;
217
    reg ok ;
218
    integer cyc_count ;
219
    integer rty_count ;
220
    reg retry ;
221
begin:main
222
 
223
    return`TB_ERROR_BIT = 1'b0 ;
224
    cab = 0 ;
225
    rty_count = 0 ;
226
    return`CYC_ACTUAL_TRANSFER = 0 ;
227
 
228
    // check if task was called before previous call finished
229
    if ( in_use === 1 )
230
    begin
231
        $display("*E, wb_single_read routine re-entered! Time %t ", $time) ;
232
        return`TB_ERROR_BIT = 1'b1 ;
233
        disable main ;
234
    end
235
 
236
    in_use = 1 ;
237
 
238
    retry = 1 ;
239
 
240
    while (retry === 1)
241
    begin
242
        // synchronize operation to clock
243
        @(posedge CLK_I) ;
244
 
245
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
246
        if ( ok !== 1 )
247
        begin
248
            $display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;
249
            return`TB_ERROR_BIT = 1'b1 ;
250
            disable main ;
251
        end
252
 
253
        // first insert initial wait states
254
        cyc_count = read_flags`INIT_WAITS ;
255
        while ( cyc_count > 0 )
256
        begin
257
            @(posedge CLK_I) ;
258
            cyc_count = cyc_count - 1 ;
259
        end
260
 
261
        wbm_low_level.wbm_read(read_data, return) ;
262
 
263
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
264
        begin
265
           if ( rty_count === `WB_TB_MAX_RTY )
266
            begin
267
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;
268
                 retry = 0 ;
269
            end
270
            else
271
            begin
272
                retry     = 1 ;
273
                rty_count = rty_count + 1 ;
274
            end
275
        end
276
        else
277
        begin
278
            retry = 0 ;
279
        end
280
 
281
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
282
        if ( return`TB_ERROR_BIT !== 0 )
283
        begin
284
            @(posedge CLK_I) ;
285
            wbm_low_level.end_cycle ;
286
            disable main ;
287
        end
288
 
289
        cyc_count = read_flags`SUBSEQ_WAITS ;
290
        while ( cyc_count > 0 )
291
        begin
292
            @(posedge CLK_I) ;
293
            cyc_count = cyc_count - 1 ;
294
        end
295
 
296
        wbm_low_level.end_cycle ;
297
    end
298
 
299
    in_use = 0 ;
300
 
301
end //main
302
endtask // wb_single_read
303
 
304
task wb_RMW_read ;
305
    input `READ_STIM_TYPE read_data ;
306
    input `WB_TRANSFER_FLAGS   read_flags ;
307
    inout `READ_RETURN_TYPE return ;
308
    reg in_use ;
309
    reg cab ;
310
    reg ok ;
311
    integer cyc_count ;
312
    integer rty_count ;
313
    reg retry ;
314
begin:main
315
 
316
    return`TB_ERROR_BIT = 1'b0 ;
317
    cab = 0 ;
318
    rty_count = 0 ;
319
    return`CYC_ACTUAL_TRANSFER = 0 ;
320
 
321
    // check if task was called before previous call finished
322
    if ( in_use === 1 )
323
    begin
324
        $display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;
325
        return`TB_ERROR_BIT = 1'b1 ;
326
        disable main ;
327
    end
328
 
329
    in_use = 1 ;
330
 
331
    retry = 1 ;
332
 
333
    while (retry === 1)
334
    begin
335
        // synchronize operation to clock
336
        @(posedge CLK_I) ;
337
 
338
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
339
        if ( ok !== 1 )
340
        begin
341
            $display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;
342
            return`TB_ERROR_BIT = 1'b1 ;
343
            disable main ;
344
        end
345
 
346
        // first insert initial wait states
347
        cyc_count = read_flags`INIT_WAITS ;
348
        while ( cyc_count > 0 )
349
        begin
350
            @(posedge CLK_I) ;
351
            cyc_count = cyc_count - 1 ;
352
        end
353
 
354
        wbm_low_level.wbm_read(read_data, return) ;
355
 
356
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
357
        begin
358
           if ( rty_count === `WB_TB_MAX_RTY )
359
            begin
360
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;
361
                 retry = 0 ;
362
            end
363
            else
364
            begin
365
                retry     = 1 ;
366
                rty_count = rty_count + 1 ;
367
            end
368
        end
369
        else
370
        begin
371
            retry = 0 ;
372
        end
373
 
374
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
375
        if ( return`TB_ERROR_BIT !== 0 )
376
        begin
377
            @(posedge CLK_I) ;
378
            wbm_low_level.end_cycle ;
379
            disable main ;
380
        end
381
 
382
        cyc_count = read_flags`SUBSEQ_WAITS ;
383
        while ( cyc_count > 0 )
384
        begin
385
            @(posedge CLK_I) ;
386
            cyc_count = cyc_count - 1 ;
387
        end
388
 
389
        if (retry === 1)
390
            wbm_low_level.end_cycle ;
391
        else
392
            wbm_low_level.modify_cycle ;
393
    end
394
 
395
    in_use = 0 ;
396
 
397
end //main
398
endtask // wb_RMW_read
399
 
400
task wb_RMW_write ;
401
    input `WRITE_STIM_TYPE write_data ;
402
    input `WB_TRANSFER_FLAGS   write_flags ;
403
    inout `WRITE_RETURN_TYPE return ;
404
    reg in_use ;
405
    reg cab ;
406
    reg ok ;
407
    integer cyc_count ;
408
    integer rty_count ;
409
    reg retry ;
410
begin:main
411
 
412
    return`TB_ERROR_BIT = 1'b0 ;
413
    cab = 0 ;
414
    return`CYC_ACTUAL_TRANSFER = 0 ;
415
    rty_count = 0 ;
416
 
417
    // check if task was called before previous call finished
418
    if ( in_use === 1 )
419
    begin
420
        $display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;
421
        return`TB_ERROR_BIT = 1'b1 ;
422
        disable main ;
423
    end
424
 
425
    in_use = 1 ;
426
 
427
    retry = 1 ;
428
 
429
    while (retry === 1)
430
    begin
431
        // synchronize operation to clock
432
        //@(posedge CLK_I) ;
433
        ok = 1 ;
434
        if (rty_count !== 0)
435
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
436
 
437
        if ( ok !== 1 )
438
        begin
439
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
440
            return`TB_ERROR_BIT = 1'b1 ;
441
            disable main ;
442
        end
443
 
444
        // first insert initial wait states
445
        cyc_count = write_flags`INIT_WAITS ;
446
        while ( cyc_count > 0 )
447
        begin
448
            @(posedge CLK_I) ;
449
            cyc_count = cyc_count - 1 ;
450
        end
451
 
452
        wbm_low_level.wbm_write(write_data, return) ;
453
 
454
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
455
        begin
456
            if ( rty_count === `WB_TB_MAX_RTY )
457
            begin
458
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
459
                 retry = 0 ;
460
            end
461
            else
462
            begin
463
                retry     = 1 ;
464
                rty_count = rty_count + 1 ;
465
            end
466
        end
467
        else
468
            retry = 0 ;
469
 
470
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
471
        if ( return`TB_ERROR_BIT !== 0 )
472
        begin
473
            @(posedge CLK_I) ;
474
            wbm_low_level.end_cycle ;
475
            disable main ;
476
        end
477
 
478
        cyc_count = write_flags`SUBSEQ_WAITS ;
479
        while ( cyc_count > 0 )
480
        begin
481
            @(posedge CLK_I) ;
482
            cyc_count = cyc_count - 1 ;
483
        end
484
 
485
        wbm_low_level.end_cycle ;
486
    end
487
 
488
    in_use = 0 ;
489
 
490
end //main
491
endtask // wb_RMW_write
492
 
493
task wb_block_write ;
494
    input  `WB_TRANSFER_FLAGS write_flags ;
495
    inout  `WRITE_RETURN_TYPE return ;
496
 
497
    reg in_use ;
498
    reg `WRITE_STIM_TYPE  current_write ;
499
    reg cab ;
500
    reg ok ;
501
    integer cyc_count ;
502
    integer rty_count ;
503
    reg end_blk ;
504
begin:main
505
 
506
    return`CYC_ACTUAL_TRANSFER = 0 ;
507
    rty_count = 0 ;
508
 
509
    // check if task was called before previous call finished
510
    if ( in_use === 1 )
511
    begin
512
        $display("*E, wb_block_write routine re-entered! Time %t ", $time) ;
513
        return`TB_ERROR_BIT = 1'b1 ;
514
        disable main ;
515
    end
516
 
517
    if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
518
    begin
519
        $display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;
520
        return`TB_ERROR_BIT = 1'b1 ;
521
        disable main ;
522
    end
523
 
524
    in_use = 1 ;
525
    @(posedge CLK_I) ;
526
    cab = write_flags`WB_TRANSFER_CAB ;
527
    wbm_low_level.start_cycle(cab, 1'b1, ok) ;
528
    if ( ok !== 1 )
529
    begin
530
        $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
531
        return`TB_ERROR_BIT = 1'b1 ;
532
        disable main ;
533
    end
534
 
535
    // insert initial wait states
536
    cyc_count = write_flags`INIT_WAITS ;
537
    while ( cyc_count > 0 )
538
    begin
539
        @(posedge CLK_I) ;
540
        cyc_count = cyc_count - 1 ;
541
    end
542
 
543
    end_blk = 0 ;
544
    while (end_blk === 0)
545
    begin
546
        // collect data for current data beat
547
        current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
548
        wbm_low_level.wbm_write(current_write, return) ;
549
 
550
        // check result of write operation
551
        // check for severe test error
552
        if (return`TB_ERROR_BIT !== 0)
553
        begin
554
           @(posedge CLK_I) ;
555
           wbm_low_level.end_cycle ;
556
           disable main ;
557
        end
558
 
559
        // slave returned error or error signal had invalid value
560
        if (return`CYC_ERR !== 0)
561
            end_blk = 1 ;
562
 
563
        if (
564
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
565
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
566
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
567
           )
568
        begin
569
            end_blk = 1 ;
570
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;
571
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
572
        end
573
 
574
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
575
            end_blk = 1 ;
576
 
577
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
578
        begin
579
            if ( rty_count === `WB_TB_MAX_RTY )
580
            begin
581
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
582
                 end_blk = 1 ;
583
            end
584
            else
585
            begin
586
                rty_count = rty_count + 1 ;
587
            end
588
        end
589
        else
590
            rty_count = 0 ;
591
 
592
        // check if slave responded at all
593
        if (return`CYC_RESPONSE === 0)
594
            end_blk = 1 ;
595
 
596
        // check if all intended data was transfered
597
        if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
598
            end_blk = 1 ;
599
 
600
        // insert subsequent wait cycles, if transfer is supposed to continue
601
        if ( end_blk === 0 )
602
        begin
603
            cyc_count = write_flags`SUBSEQ_WAITS ;
604
            while ( cyc_count > 0 )
605
            begin
606
                @(posedge CLK_I) ;
607
                cyc_count = cyc_count - 1 ;
608
            end
609
        end
610
 
611
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
612
        begin
613
            wbm_low_level.end_cycle ;
614
            @(posedge CLK_I) ;
615
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
616
            if ( ok !== 1 )
617
            begin
618
                $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
619
                return`TB_ERROR_BIT = 1'b1 ;
620
                end_blk = 1 ;
621
            end
622
        end
623
    end //while
624
 
625
    wbm_low_level.end_cycle ;
626
    in_use = 0 ;
627
end //main
628
endtask //wb_block_write
629
 
630
task wb_block_read ;
631
    input  `WB_TRANSFER_FLAGS      read_flags ;
632
    inout `READ_RETURN_TYPE       return ;
633
 
634
    reg in_use ;
635
    reg `READ_STIM_TYPE  current_read ;
636
    reg cab ;
637
    reg ok ;
638
    integer cyc_count ;
639
    integer rty_count ;
640
    reg end_blk ;
641
    integer transfered ;
642
begin:main
643
 
644
    return`CYC_ACTUAL_TRANSFER = 0 ;
645
    transfered = 0 ;
646
    rty_count = 0 ;
647
 
648
    // check if task was called before previous call finished
649
    if ( in_use === 1 )
650
    begin
651
        $display("*E, wb_block_read routine re-entered! Time %t ", $time) ;
652
        return`TB_ERROR_BIT = 1'b1 ;
653
        disable main ;
654
    end
655
 
656
    if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
657
    begin
658
        $display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;
659
        return`TB_ERROR_BIT = 1'b1 ;
660
        disable main ;
661
    end
662
 
663
    in_use = 1 ;
664
    @(posedge CLK_I) ;
665
    cab = read_flags`WB_TRANSFER_CAB ;
666
 
667
    wbm_low_level.start_cycle(cab, 1'b0, ok) ;
668
 
669
    if ( ok !== 1 )
670
    begin
671
        $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
672
        return`TB_ERROR_BIT = 1'b1 ;
673
        disable main ;
674
    end
675
 
676
    // insert initial wait states
677
    cyc_count = read_flags`INIT_WAITS ;
678
    while ( cyc_count > 0 )
679
    begin
680
        @(posedge CLK_I) ;
681
        cyc_count = cyc_count - 1 ;
682
    end
683
 
684
    end_blk = 0 ;
685
    while (end_blk === 0)
686
    begin
687
        // collect data for current data beat
688
        current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
689
 
690
        wbm_low_level.wbm_read(current_read, return) ;
691
 
692
        if ( transfered !== return`CYC_ACTUAL_TRANSFER )
693
        begin
694
            blk_read_data_out[transfered] = return ;
695
            transfered = return`CYC_ACTUAL_TRANSFER ;
696
        end
697
 
698
        // check result of read operation
699
        // check for severe test error
700
        if (return`TB_ERROR_BIT !== 0)
701
        begin
702
           @(posedge CLK_I) ;
703
           wbm_low_level.end_cycle ;
704
           disable main ;
705
        end
706
 
707
        // slave returned error or error signal had invalid value
708
        if (return`CYC_ERR !== 0)
709
            end_blk = 1 ;
710
 
711
        if (
712
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
713
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
714
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
715
           )
716
        begin
717
            end_blk = 1 ;
718
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;
719
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
720
        end
721
 
722
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
723
            end_blk = 1 ;
724
 
725
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
726
        begin
727
            if ( rty_count === `WB_TB_MAX_RTY )
728
            begin
729
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
730
                 end_blk = 1 ;
731
            end
732
            else
733
            begin
734
                rty_count = rty_count + 1 ;
735
            end
736
        end
737
        else
738
            rty_count = 0 ;
739
 
740
        // check if slave responded at all
741
        if (return`CYC_RESPONSE === 0)
742
            end_blk = 1 ;
743
 
744
        // check if all intended data was transfered
745
        if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
746
            end_blk = 1 ;
747
 
748
        // insert subsequent wait cycles, if transfer is supposed to continue
749
        if ( end_blk === 0 )
750
        begin
751
            cyc_count = read_flags`SUBSEQ_WAITS ;
752
            while ( cyc_count > 0 )
753
            begin
754
                @(posedge CLK_I) ;
755
                cyc_count = cyc_count - 1 ;
756
            end
757
        end
758
 
759
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
760
        begin
761
            wbm_low_level.end_cycle ;
762
            @(posedge CLK_I) ;
763
            wbm_low_level.start_cycle(cab, 1'b0, ok) ;
764
            if ( ok !== 1 )
765
            begin
766
                $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
767
                return`TB_ERROR_BIT = 1'b1 ;
768
                end_blk = 1 ;
769
            end
770
        end
771
    end //while
772
 
773
    wbm_low_level.end_cycle ;
774
    in_use = 0 ;
775
end //main
776
endtask //wb_block_read
777
 
778
endmodule
779
 

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