OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [wb_model_defines.v] - Blame information for rev 346

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 170 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  File name "wb_model_defines.v"                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 170 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Miha Dolenc (mihad@opencores.org)                     ////
10
////                                                              ////
11
////  All additional information is available in the README.pdf   ////
12
////  file.                                                       ////
13
////                                                              ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2002 Authors                                   ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 315 tadejm
// Revision 1.2  2002/09/13 12:29:14  mohor
46
// Headers changed.
47 170 mohor
//
48
//
49
//
50 315 tadejm
//
51 170 mohor
 
52 169 mohor
// WISHBONE frequency in GHz
53
`define WB_FREQ 0.100
54
 
55
// memory frequency in GHz
56
`define MEM_FREQ 0.100
57
 
58
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
59
`define Tsetup 4
60
`define Thold  1
61
 
62
// how many clock cycles should model wait for design's response - integer 32 bit value
63
`define WAIT_FOR_RESPONSE 1023
64
 
65
// maximum number of transactions allowed in single call to block or cab transfer routines
66
`define MAX_BLK_SIZE  1024
67
 
68
// maximum retry terminations allowed for WISHBONE master to repeat an access
69
`define WB_TB_MAX_RTY 0
70
 
71
 
72
// some common types and defines
73
`define WB_ADDR_WIDTH 32
74
`define WB_DATA_WIDTH 32
75
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
76 315 tadejm
`define WB_TAG_WIDTH 5
77 169 mohor
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
78
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
79
`define WB_SEL_TYPE  [(`WB_SEL_WIDTH  - 1):0]
80
`define WB_TAG_TYPE  [(`WB_TAG_WIDTH  - 1):0]
81
 
82
// read cycle stimulus - consists of:
83
//    - address field - which address read will be performed from
84
//    - sel field     - what byte select value should be
85
//    - tag field     - what tag values should be put on the bus
86
`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
87
`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
88
`define READ_ADDRESS  [(`WB_ADDR_WIDTH - 1):0]
89
`define READ_SEL      [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
90
`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
91
 
92
// read cycle return type consists of:
93
//    - read data field
94
//    - tag field received from WISHBONE
95
//    - wishbone slave response fields - ACK, ERR and RTY
96
//    - test bench error indicator (when testcase has not used wb master model properly)
97
//    - how much data was actually transfered
98
`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
99
`define READ_DATA        [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
100
`define READ_TAG_RET     [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
101
`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
102
 
103
// write cycle stimulus type consists of
104
//    - address field
105
//    - data field
106
//    - sel field
107
//    - tag field
108
`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
109
`define WRITE_ADDRESS       [(`WB_ADDR_WIDTH - 1):0]
110
`define WRITE_DATA          [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
111
`define WRITE_SEL           [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
112
`define WRITE_TAG_STIM      [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
113
 
114
// length of WRITE_STIMULUS
115
`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
116
 
117
// write cycle return type consists of:
118
//    - test bench error indicator (when testcase has not used wb master model properly)
119
//    - wishbone slave response fields - ACK, ERR and RTY
120
//    - tag field received from WISHBONE
121
//    - how much data was actually transfered
122
`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
123
`define WRITE_TAG_RET     [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
124
 
125
// this four fields are common to both read and write routines return values
126
`define TB_ERROR_BIT [0]
127
`define CYC_ACK [1]
128
`define CYC_RTY [2]
129
`define CYC_ERR [3]
130
`define CYC_RESPONSE [3:1]
131
`define CYC_ACTUAL_TRANSFER [35:4]
132
 
133
// block transfer flags
134
`define WB_TRANSFER_FLAGS [41:0]
135
// consists of:
136
// - number of transfer cycles to perform
137
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
138
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
139
// - number of initial wait states to insert
140
// - number of subsequent wait states to insert
141
`define WB_TRANSFER_SIZE     [41:10]
142
`define WB_TRANSFER_AUTO_RTY [8]
143
`define WB_TRANSFER_CAB      [9]
144
`define INIT_WAITS           [3:0]
145
`define SUBSEQ_WAITS         [7:4]
146
 
147
// wb slave response
148
`define ACK_RESPONSE  3'b100
149
`define ERR_RESPONSE  3'b010
150
`define RTY_RESPONSE  3'b001
151
`define NO_RESPONSE   3'b000

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.