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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Blame information for rev 129

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_cop.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
//
 
`include "tb_eth_defines.v"
`include "timescale.v"
 
module eth_cop
(
  // WISHBONE common
  wb_clk_i, wb_rst_i,
 
  // WISHBONE MASTER 1
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
  m1_wb_err_o,
 
  // WISHBONE MASTER 2
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
  m2_wb_err_o,
 
  // WISHBONE slave 1
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
        s1_wb_dat_o,
 
  // WISHBONE slave 2
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
        s2_wb_dat_o
);
 
parameter Tp=1;
 
// WISHBONE common
input wb_clk_i, wb_rst_i;
 
// WISHBONE MASTER 1
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
input   [3:0] m1_wb_sel_i;
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
output [31:0] m1_wb_dat_o;
output        m1_wb_ack_o, m1_wb_err_o;
 
// WISHBONE MASTER 2
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
input   [3:0] m2_wb_sel_i;
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
output [31:0] m2_wb_dat_o;
output        m2_wb_ack_o, m2_wb_err_o;
 
// WISHBONE slave 1
input  [31:0] s1_wb_dat_i;
input         s1_wb_ack_i, s1_wb_err_i;
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
output  [3:0] s1_wb_sel_o;
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
 
// WISHBONE slave 2
input  [31:0] s2_wb_dat_i;
input         s2_wb_ack_i, s2_wb_err_i;
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
output  [3:0] s2_wb_sel_o;
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
 
reg           m1_in_progress;
reg           m2_in_progress;
reg    [31:0] s1_wb_adr_o;
reg     [3:0] s1_wb_sel_o;
reg           s1_wb_we_o;
reg    [31:0] s1_wb_dat_o;
reg           s1_wb_cyc_o;
reg           s1_wb_stb_o;
reg    [31:0] s2_wb_adr_o;
reg     [3:0] s2_wb_sel_o;
reg           s2_wb_we_o;
reg    [31:0] s2_wb_dat_o;
reg           s2_wb_cyc_o;
reg           s2_wb_stb_o;
 
reg           m1_wb_ack_o;
reg    [31:0] m1_wb_dat_o;
reg           m2_wb_ack_o;
reg    [31:0] m2_wb_dat_o;
 
reg           m1_wb_err_o;
reg           m2_wb_err_o;
 
wire m_wb_access_finished;
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      m1_in_progress <=#Tp 0;
      m2_in_progress <=#Tp 0;
      s1_wb_adr_o    <=#Tp 0;
      s1_wb_sel_o    <=#Tp 0;
      s1_wb_we_o     <=#Tp 0;
      s1_wb_dat_o    <=#Tp 0;
      s1_wb_cyc_o    <=#Tp 0;
      s1_wb_stb_o    <=#Tp 0;
      s2_wb_adr_o    <=#Tp 0;
      s2_wb_sel_o    <=#Tp 0;
      s2_wb_we_o     <=#Tp 0;
      s2_wb_dat_o    <=#Tp 0;
      s2_wb_cyc_o    <=#Tp 0;
      s2_wb_stb_o    <=#Tp 0;
    end
  else
    begin
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
        5'b00_10_0, 5'b00_11_0 :
          begin
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
            if(`M1_ADDRESSED_S1)
              begin
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
                s1_wb_we_o  <=#Tp m1_wb_we_i;
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
                s1_wb_cyc_o <=#Tp 1'b1;
                s1_wb_stb_o <=#Tp 1'b1;
              end
            else if(`M1_ADDRESSED_S2)
              begin
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
                s2_wb_we_o  <=#Tp m1_wb_we_i;
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
                s2_wb_cyc_o <=#Tp 1'b1;
                s2_wb_stb_o <=#Tp 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b00_01_0 :
          begin
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
            if(`M2_ADDRESSED_S1)
              begin
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
                s1_wb_we_o  <=#Tp m2_wb_we_i;
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
                s1_wb_cyc_o <=#Tp 1'b1;
                s1_wb_stb_o <=#Tp 1'b1;
              end
            else if(`M2_ADDRESSED_S2)
              begin
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
                s2_wb_we_o  <=#Tp m2_wb_we_i;
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
                s2_wb_cyc_o <=#Tp 1'b1;
                s2_wb_stb_o <=#Tp 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b10_10_1, 5'b10_11_1 :
          begin
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
            if(`M1_ADDRESSED_S1)
              begin
                s1_wb_cyc_o <=#Tp 1'b0;
                s1_wb_stb_o <=#Tp 1'b0;
              end
            else if(`M1_ADDRESSED_S2)
              begin
                s2_wb_cyc_o <=#Tp 1'b0;
                s2_wb_stb_o <=#Tp 1'b0;
              end
          end
        5'b01_01_1, 5'b01_11_1 :
          begin
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
            if(`M2_ADDRESSED_S1)
              begin
                s1_wb_cyc_o <=#Tp 1'b0;
                s1_wb_stb_o <=#Tp 1'b0;
              end
            else if(`M2_ADDRESSED_S2)
              begin
                s2_wb_cyc_o <=#Tp 1'b0;
                s2_wb_stb_o <=#Tp 1'b0;
              end
          end
      endcase
    end
end
 
// Generating Ack for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
begin
  if(m1_in_progress)
    begin
      if(`M1_ADDRESSED_S1) begin
        m1_wb_ack_o <= s1_wb_ack_i;
        m1_wb_dat_o <= s1_wb_dat_i;
      end
      else if(`M1_ADDRESSED_S2) begin
        m1_wb_ack_o <= s2_wb_ack_i;
        m1_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m1_wb_ack_o <= 0;
end
 
 
// Generating Ack for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
begin
  if(m2_in_progress)
    begin
      if(`M2_ADDRESSED_S1) begin
        m2_wb_ack_o <= s1_wb_ack_i;
        m2_wb_dat_o <= s1_wb_dat_i;
      end
      else if(`M2_ADDRESSED_S2) begin
        m2_wb_ack_o <= s2_wb_ack_i;
        m2_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m2_wb_ack_o <= 0;
end
 
 
// Generating Err for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
          m1_wb_cyc_i or m1_wb_stb_i)
begin
  if(m1_in_progress)  begin
    if(`M1_ADDRESSED_S1)
      m1_wb_err_o <= s1_wb_err_i;
    else if(`M1_ADDRESSED_S2)
      m1_wb_err_o <= s2_wb_err_i;
  end
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
    m1_wb_err_o <= 1'b1;
  else
    m1_wb_err_o <= 1'b0;
end
 
 
// Generating Err for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
          m2_wb_cyc_i or m2_wb_stb_i)
begin
  if(m2_in_progress)  begin
    if(`M2_ADDRESSED_S1)
      m2_wb_err_o <= s1_wb_err_i;
    else if(`M2_ADDRESSED_S2)
      m2_wb_err_o <= s2_wb_err_i;
  end
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
    m2_wb_err_o <= 1'b1;
  else
    m2_wb_err_o <= 1'b0;
end
 
 
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
 
 
// Activity monitor
integer cnt;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    cnt <=#Tp 0;
  else
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
    cnt <=#Tp 0;
  else
  if(s1_wb_cyc_o | s2_wb_cyc_o)
    cnt <=#Tp cnt+1;
end
 
always @ (posedge wb_clk_i)
begin
  if(cnt==1000) begin
    $display("(%0t) ERROR: WB activity ??? ", $time);
    if(s1_wb_cyc_o) begin
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    end
    else if(s1_wb_cyc_o) begin
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    end
 
    $stop;
  end
end
 
 
 
endmodule

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Blame information for rev 129

Line No.	Rev	Author	Line
1	129	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_cop.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`//`
45			`//`
46			`//`
47			`//`
48
49			`include "tb_eth_defines.v"
50			`include "timescale.v"
51
52			`module eth_cop`
53			`(`
54			`// WISHBONE common`
55			`wb_clk_i, wb_rst_i,`
56
57			`// WISHBONE MASTER 1`
58			`m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,`
59			`m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,`
60			`m1_wb_err_o,`
61
62			`// WISHBONE MASTER 2`
63			`m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,`
64			`m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,`
65			`m2_wb_err_o,`
66
67			`// WISHBONE slave 1`
68			`s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,`
69			`s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,`
70			`s1_wb_dat_o,`
71
72			`// WISHBONE slave 2`
73			`s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,`
74			`s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,`
75			`s2_wb_dat_o`
76			`);`
77
78			`parameter Tp=1;`
79
80			`// WISHBONE common`
81			`input wb_clk_i, wb_rst_i;`
82
83			`// WISHBONE MASTER 1`
84			`input [31:0] m1_wb_adr_i, m1_wb_dat_i;`
85			`input [3:0] m1_wb_sel_i;`
86			`input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;`
87			`output [31:0] m1_wb_dat_o;`
88			`output m1_wb_ack_o, m1_wb_err_o;`
89
90			`// WISHBONE MASTER 2`
91			`input [31:0] m2_wb_adr_i, m2_wb_dat_i;`
92			`input [3:0] m2_wb_sel_i;`
93			`input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;`
94			`output [31:0] m2_wb_dat_o;`
95			`output m2_wb_ack_o, m2_wb_err_o;`
96
97			`// WISHBONE slave 1`
98			`input [31:0] s1_wb_dat_i;`
99			`input s1_wb_ack_i, s1_wb_err_i;`
100			`output [31:0] s1_wb_adr_o, s1_wb_dat_o;`
101			`output [3:0] s1_wb_sel_o;`
102			`output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;`
103
104			`// WISHBONE slave 2`
105			`input [31:0] s2_wb_dat_i;`
106			`input s2_wb_ack_i, s2_wb_err_i;`
107			`output [31:0] s2_wb_adr_o, s2_wb_dat_o;`
108			`output [3:0] s2_wb_sel_o;`
109			`output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;`
110
111			`reg m1_in_progress;`
112			`reg m2_in_progress;`
113			`reg [31:0] s1_wb_adr_o;`
114			`reg [3:0] s1_wb_sel_o;`
115			`reg s1_wb_we_o;`
116			`reg [31:0] s1_wb_dat_o;`
117			`reg s1_wb_cyc_o;`
118			`reg s1_wb_stb_o;`
119			`reg [31:0] s2_wb_adr_o;`
120			`reg [3:0] s2_wb_sel_o;`
121			`reg s2_wb_we_o;`
122			`reg [31:0] s2_wb_dat_o;`
123			`reg s2_wb_cyc_o;`
124			`reg s2_wb_stb_o;`
125
126			`reg m1_wb_ack_o;`
127			`reg [31:0] m1_wb_dat_o;`
128			`reg m2_wb_ack_o;`
129			`reg [31:0] m2_wb_dat_o;`
130
131			`reg m1_wb_err_o;`
132			`reg m2_wb_err_o;`
133
134			`wire m_wb_access_finished;`
135			wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 \| `M1_ADDRESSED_S2);
136			wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 \| `M2_ADDRESSED_S2);
137
138			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
139			`begin`
140			`if(wb_rst_i)`
141			`begin`
142			`m1_in_progress <=#Tp 0;`
143			`m2_in_progress <=#Tp 0;`
144			`s1_wb_adr_o <=#Tp 0;`
145			`s1_wb_sel_o <=#Tp 0;`
146			`s1_wb_we_o <=#Tp 0;`
147			`s1_wb_dat_o <=#Tp 0;`
148			`s1_wb_cyc_o <=#Tp 0;`
149			`s1_wb_stb_o <=#Tp 0;`
150			`s2_wb_adr_o <=#Tp 0;`
151			`s2_wb_sel_o <=#Tp 0;`
152			`s2_wb_we_o <=#Tp 0;`
153			`s2_wb_dat_o <=#Tp 0;`
154			`s2_wb_cyc_o <=#Tp 0;`
155			`s2_wb_stb_o <=#Tp 0;`
156			`end`
157			`else`
158			`begin`
159			`case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case`
160			`5'b00_10_0, 5'b00_11_0 :`
161			`begin`
162			`m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m`
163			if(`M1_ADDRESSED_S1)
164			`begin`
165			`s1_wb_adr_o <=#Tp m1_wb_adr_i;`
166			`s1_wb_sel_o <=#Tp m1_wb_sel_i;`
167			`s1_wb_we_o <=#Tp m1_wb_we_i;`
168			`s1_wb_dat_o <=#Tp m1_wb_dat_i;`
169			`s1_wb_cyc_o <=#Tp 1'b1;`
170			`s1_wb_stb_o <=#Tp 1'b1;`
171			`end`
172			else if(`M1_ADDRESSED_S2)
173			`begin`
174			`s2_wb_adr_o <=#Tp m1_wb_adr_i;`
175			`s2_wb_sel_o <=#Tp m1_wb_sel_i;`
176			`s2_wb_we_o <=#Tp m1_wb_we_i;`
177			`s2_wb_dat_o <=#Tp m1_wb_dat_i;`
178			`s2_wb_cyc_o <=#Tp 1'b1;`
179			`s2_wb_stb_o <=#Tp 1'b1;`
180			`end`
181			`else`
182			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
183			`end`
184			`5'b00_01_0 :`
185			`begin`
186			`m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m`
187			if(`M2_ADDRESSED_S1)
188			`begin`
189			`s1_wb_adr_o <=#Tp m2_wb_adr_i;`
190			`s1_wb_sel_o <=#Tp m2_wb_sel_i;`
191			`s1_wb_we_o <=#Tp m2_wb_we_i;`
192			`s1_wb_dat_o <=#Tp m2_wb_dat_i;`
193			`s1_wb_cyc_o <=#Tp 1'b1;`
194			`s1_wb_stb_o <=#Tp 1'b1;`
195			`end`
196			else if(`M2_ADDRESSED_S2)
197			`begin`
198			`s2_wb_adr_o <=#Tp m2_wb_adr_i;`
199			`s2_wb_sel_o <=#Tp m2_wb_sel_i;`
200			`s2_wb_we_o <=#Tp m2_wb_we_i;`
201			`s2_wb_dat_o <=#Tp m2_wb_dat_i;`
202			`s2_wb_cyc_o <=#Tp 1'b1;`
203			`s2_wb_stb_o <=#Tp 1'b1;`
204			`end`
205			`else`
206			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
207			`end`
208			`5'b10_10_1, 5'b10_11_1 :`
209			`begin`
210			`m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.`
211			if(`M1_ADDRESSED_S1)
212			`begin`
213			`s1_wb_cyc_o <=#Tp 1'b0;`
214			`s1_wb_stb_o <=#Tp 1'b0;`
215			`end`
216			else if(`M1_ADDRESSED_S2)
217			`begin`
218			`s2_wb_cyc_o <=#Tp 1'b0;`
219			`s2_wb_stb_o <=#Tp 1'b0;`
220			`end`
221			`end`
222			`5'b01_01_1, 5'b01_11_1 :`
223			`begin`
224			`m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.`
225			if(`M2_ADDRESSED_S1)
226			`begin`
227			`s1_wb_cyc_o <=#Tp 1'b0;`
228			`s1_wb_stb_o <=#Tp 1'b0;`
229			`end`
230			else if(`M2_ADDRESSED_S2)
231			`begin`
232			`s2_wb_cyc_o <=#Tp 1'b0;`
233			`s2_wb_stb_o <=#Tp 1'b0;`
234			`end`
235			`end`
236			`endcase`
237			`end`
238			`end`
239
240			`// Generating Ack for master 1`
241			always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
242			`begin`
243			`if(m1_in_progress)`
244			`begin`
245			if(`M1_ADDRESSED_S1) begin
246			`m1_wb_ack_o <= s1_wb_ack_i;`
247			`m1_wb_dat_o <= s1_wb_dat_i;`
248			`end`
249			else if(`M1_ADDRESSED_S2) begin
250			`m1_wb_ack_o <= s2_wb_ack_i;`
251			`m1_wb_dat_o <= s2_wb_dat_i;`
252			`end`
253			`end`
254			`else`
255			`m1_wb_ack_o <= 0;`
256			`end`
257
258
259			`// Generating Ack for master 2`
260			always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
261			`begin`
262			`if(m2_in_progress)`
263			`begin`
264			if(`M2_ADDRESSED_S1) begin
265			`m2_wb_ack_o <= s1_wb_ack_i;`
266			`m2_wb_dat_o <= s1_wb_dat_i;`
267			`end`
268			else if(`M2_ADDRESSED_S2) begin
269			`m2_wb_ack_o <= s2_wb_ack_i;`
270			`m2_wb_dat_o <= s2_wb_dat_i;`
271			`end`
272			`end`
273			`else`
274			`m2_wb_ack_o <= 0;`
275			`end`
276
277
278			`// Generating Err for master 1`
279			always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
280			`m1_wb_cyc_i or m1_wb_stb_i)`
281			`begin`
282			`if(m1_in_progress) begin`
283			if(`M1_ADDRESSED_S1)
284			`m1_wb_err_o <= s1_wb_err_i;`
285			else if(`M1_ADDRESSED_S2)
286			`m1_wb_err_o <= s2_wb_err_i;`
287			`end`
288			else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
289			`m1_wb_err_o <= 1'b1;`
290			`else`
291			`m1_wb_err_o <= 1'b0;`
292			`end`
293
294
295			`// Generating Err for master 2`
296			always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
297			`m2_wb_cyc_i or m2_wb_stb_i)`
298			`begin`
299			`if(m2_in_progress) begin`
300			if(`M2_ADDRESSED_S1)
301			`m2_wb_err_o <= s1_wb_err_i;`
302			else if(`M2_ADDRESSED_S2)
303			`m2_wb_err_o <= s2_wb_err_i;`
304			`end`
305			else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
306			`m2_wb_err_o <= 1'b1;`
307			`else`
308			`m2_wb_err_o <= 1'b0;`
309			`end`
310
311
312			`assign m_wb_access_finished = m1_wb_ack_o \| m1_wb_err_o \| m2_wb_ack_o \| m2_wb_err_o;`
313
314
315			`// Activity monitor`
316			`integer cnt;`
317			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
318			`begin`
319			`if(wb_rst_i)`
320			`cnt <=#Tp 0;`
321			`else`
322			`if(s1_wb_ack_i \| s1_wb_err_i \| s2_wb_ack_i \| s2_wb_err_i)`
323			`cnt <=#Tp 0;`
324			`else`
325			`if(s1_wb_cyc_o \| s2_wb_cyc_o)`
326			`cnt <=#Tp cnt+1;`
327			`end`
328
329			`always @ (posedge wb_clk_i)`
330			`begin`
331			`if(cnt==1000) begin`
332			`$display("(%0t) ERROR: WB activity ??? ", $time);`
333			`if(s1_wb_cyc_o) begin`
334			`$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);`
335			`$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);`
336			`$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);`
337			`$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);`
338			`end`
339			`else if(s1_wb_cyc_o) begin`
340			`$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);`
341			`$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);`
342			`$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);`
343			`$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);`
344			`end`
345
346			`$stop;`
347			`end`
348			`end`
349
350
351
352			`endmodule`