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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Blame information for rev 129

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1 129 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_cop.v                                                   ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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`include "tb_eth_defines.v"
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`include "timescale.v"
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module eth_cop
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(
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  // WISHBONE common
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  wb_clk_i, wb_rst_i,
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  // WISHBONE MASTER 1
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  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
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  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
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  m1_wb_err_o,
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  // WISHBONE MASTER 2
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  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
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  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
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  m2_wb_err_o,
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  // WISHBONE slave 1
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        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
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        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
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        s1_wb_dat_o,
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  // WISHBONE slave 2
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        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
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        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
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        s2_wb_dat_o
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);
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parameter Tp=1;
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// WISHBONE common
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input wb_clk_i, wb_rst_i;
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// WISHBONE MASTER 1
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input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
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input   [3:0] m1_wb_sel_i;
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input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
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output [31:0] m1_wb_dat_o;
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output        m1_wb_ack_o, m1_wb_err_o;
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90
// WISHBONE MASTER 2
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input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
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input   [3:0] m2_wb_sel_i;
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input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
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output [31:0] m2_wb_dat_o;
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output        m2_wb_ack_o, m2_wb_err_o;
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// WISHBONE slave 1
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input  [31:0] s1_wb_dat_i;
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input         s1_wb_ack_i, s1_wb_err_i;
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output [31:0] s1_wb_adr_o, s1_wb_dat_o;
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output  [3:0] s1_wb_sel_o;
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output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
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104
// WISHBONE slave 2
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input  [31:0] s2_wb_dat_i;
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input         s2_wb_ack_i, s2_wb_err_i;
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output [31:0] s2_wb_adr_o, s2_wb_dat_o;
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output  [3:0] s2_wb_sel_o;
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output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
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111
reg           m1_in_progress;
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reg           m2_in_progress;
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reg    [31:0] s1_wb_adr_o;
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reg     [3:0] s1_wb_sel_o;
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reg           s1_wb_we_o;
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reg    [31:0] s1_wb_dat_o;
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reg           s1_wb_cyc_o;
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reg           s1_wb_stb_o;
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reg    [31:0] s2_wb_adr_o;
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reg     [3:0] s2_wb_sel_o;
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reg           s2_wb_we_o;
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reg    [31:0] s2_wb_dat_o;
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reg           s2_wb_cyc_o;
124
reg           s2_wb_stb_o;
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126
reg           m1_wb_ack_o;
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reg    [31:0] m1_wb_dat_o;
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reg           m2_wb_ack_o;
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reg    [31:0] m2_wb_dat_o;
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131
reg           m1_wb_err_o;
132
reg           m2_wb_err_o;
133
 
134
wire m_wb_access_finished;
135
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
136
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
137
 
138
always @ (posedge wb_clk_i or posedge wb_rst_i)
139
begin
140
  if(wb_rst_i)
141
    begin
142
      m1_in_progress <=#Tp 0;
143
      m2_in_progress <=#Tp 0;
144
      s1_wb_adr_o    <=#Tp 0;
145
      s1_wb_sel_o    <=#Tp 0;
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      s1_wb_we_o     <=#Tp 0;
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      s1_wb_dat_o    <=#Tp 0;
148
      s1_wb_cyc_o    <=#Tp 0;
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      s1_wb_stb_o    <=#Tp 0;
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      s2_wb_adr_o    <=#Tp 0;
151
      s2_wb_sel_o    <=#Tp 0;
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      s2_wb_we_o     <=#Tp 0;
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      s2_wb_dat_o    <=#Tp 0;
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      s2_wb_cyc_o    <=#Tp 0;
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      s2_wb_stb_o    <=#Tp 0;
156
    end
157
  else
158
    begin
159
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
160
        5'b00_10_0, 5'b00_11_0 :
161
          begin
162
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
163
            if(`M1_ADDRESSED_S1)
164
              begin
165
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
166
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
167
                s1_wb_we_o  <=#Tp m1_wb_we_i;
168
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
169
                s1_wb_cyc_o <=#Tp 1'b1;
170
                s1_wb_stb_o <=#Tp 1'b1;
171
              end
172
            else if(`M1_ADDRESSED_S2)
173
              begin
174
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
175
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
176
                s2_wb_we_o  <=#Tp m1_wb_we_i;
177
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
178
                s2_wb_cyc_o <=#Tp 1'b1;
179
                s2_wb_stb_o <=#Tp 1'b1;
180
              end
181
            else
182
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
183
          end
184
        5'b00_01_0 :
185
          begin
186
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
187
            if(`M2_ADDRESSED_S1)
188
              begin
189
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
190
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
191
                s1_wb_we_o  <=#Tp m2_wb_we_i;
192
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
193
                s1_wb_cyc_o <=#Tp 1'b1;
194
                s1_wb_stb_o <=#Tp 1'b1;
195
              end
196
            else if(`M2_ADDRESSED_S2)
197
              begin
198
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
199
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
200
                s2_wb_we_o  <=#Tp m2_wb_we_i;
201
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
202
                s2_wb_cyc_o <=#Tp 1'b1;
203
                s2_wb_stb_o <=#Tp 1'b1;
204
              end
205
            else
206
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
207
          end
208
        5'b10_10_1, 5'b10_11_1 :
209
          begin
210
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
211
            if(`M1_ADDRESSED_S1)
212
              begin
213
                s1_wb_cyc_o <=#Tp 1'b0;
214
                s1_wb_stb_o <=#Tp 1'b0;
215
              end
216
            else if(`M1_ADDRESSED_S2)
217
              begin
218
                s2_wb_cyc_o <=#Tp 1'b0;
219
                s2_wb_stb_o <=#Tp 1'b0;
220
              end
221
          end
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        5'b01_01_1, 5'b01_11_1 :
223
          begin
224
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
225
            if(`M2_ADDRESSED_S1)
226
              begin
227
                s1_wb_cyc_o <=#Tp 1'b0;
228
                s1_wb_stb_o <=#Tp 1'b0;
229
              end
230
            else if(`M2_ADDRESSED_S2)
231
              begin
232
                s2_wb_cyc_o <=#Tp 1'b0;
233
                s2_wb_stb_o <=#Tp 1'b0;
234
              end
235
          end
236
      endcase
237
    end
238
end
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240
// Generating Ack for master 1
241
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
242
begin
243
  if(m1_in_progress)
244
    begin
245
      if(`M1_ADDRESSED_S1) begin
246
        m1_wb_ack_o <= s1_wb_ack_i;
247
        m1_wb_dat_o <= s1_wb_dat_i;
248
      end
249
      else if(`M1_ADDRESSED_S2) begin
250
        m1_wb_ack_o <= s2_wb_ack_i;
251
        m1_wb_dat_o <= s2_wb_dat_i;
252
      end
253
    end
254
  else
255
    m1_wb_ack_o <= 0;
256
end
257
 
258
 
259
// Generating Ack for master 2
260
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
261
begin
262
  if(m2_in_progress)
263
    begin
264
      if(`M2_ADDRESSED_S1) begin
265
        m2_wb_ack_o <= s1_wb_ack_i;
266
        m2_wb_dat_o <= s1_wb_dat_i;
267
      end
268
      else if(`M2_ADDRESSED_S2) begin
269
        m2_wb_ack_o <= s2_wb_ack_i;
270
        m2_wb_dat_o <= s2_wb_dat_i;
271
      end
272
    end
273
  else
274
    m2_wb_ack_o <= 0;
275
end
276
 
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278
// Generating Err for master 1
279
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
280
          m1_wb_cyc_i or m1_wb_stb_i)
281
begin
282
  if(m1_in_progress)  begin
283
    if(`M1_ADDRESSED_S1)
284
      m1_wb_err_o <= s1_wb_err_i;
285
    else if(`M1_ADDRESSED_S2)
286
      m1_wb_err_o <= s2_wb_err_i;
287
  end
288
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
289
    m1_wb_err_o <= 1'b1;
290
  else
291
    m1_wb_err_o <= 1'b0;
292
end
293
 
294
 
295
// Generating Err for master 2
296
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
297
          m2_wb_cyc_i or m2_wb_stb_i)
298
begin
299
  if(m2_in_progress)  begin
300
    if(`M2_ADDRESSED_S1)
301
      m2_wb_err_o <= s1_wb_err_i;
302
    else if(`M2_ADDRESSED_S2)
303
      m2_wb_err_o <= s2_wb_err_i;
304
  end
305
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
306
    m2_wb_err_o <= 1'b1;
307
  else
308
    m2_wb_err_o <= 1'b0;
309
end
310
 
311
 
312
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
313
 
314
 
315
// Activity monitor
316
integer cnt;
317
always @ (posedge wb_clk_i or posedge wb_rst_i)
318
begin
319
  if(wb_rst_i)
320
    cnt <=#Tp 0;
321
  else
322
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
323
    cnt <=#Tp 0;
324
  else
325
  if(s1_wb_cyc_o | s2_wb_cyc_o)
326
    cnt <=#Tp cnt+1;
327
end
328
 
329
always @ (posedge wb_clk_i)
330
begin
331
  if(cnt==1000) begin
332
    $display("(%0t) ERROR: WB activity ??? ", $time);
333
    if(s1_wb_cyc_o) begin
334
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
335
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
336
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
337
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
338
    end
339
    else if(s1_wb_cyc_o) begin
340
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
341
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
342
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
343
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
344
    end
345
 
346
    $stop;
347
  end
348
end
349
 
350
 
351
 
352
endmodule

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