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1 129 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_cop.v                                                   ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
44 160 mohor
// Revision 1.1  2002/08/14 17:16:07  mohor
45
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
46
// interfaces:
47
// - Host connects to the master interface
48
// - Ethernet master (DMA) connects to the second master interface
49
// - Memory interface connects to the slave interface
50
// - Ethernet slave interface (access to registers and BDs) connects to second
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//   slave interface
52 129 mohor
//
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//
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//
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//
56 160 mohor
//
57 129 mohor
 
58
`include "tb_eth_defines.v"
59
`include "timescale.v"
60
 
61
module eth_cop
62
(
63
  // WISHBONE common
64
  wb_clk_i, wb_rst_i,
65
 
66
  // WISHBONE MASTER 1
67
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
68
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
69
  m1_wb_err_o,
70
 
71
  // WISHBONE MASTER 2
72
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
73
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
74
  m2_wb_err_o,
75
 
76
  // WISHBONE slave 1
77
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
78
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
79
        s1_wb_dat_o,
80
 
81
  // WISHBONE slave 2
82
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
83
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
84
        s2_wb_dat_o
85
);
86
 
87
parameter Tp=1;
88
 
89
// WISHBONE common
90
input wb_clk_i, wb_rst_i;
91
 
92
// WISHBONE MASTER 1
93
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
94
input   [3:0] m1_wb_sel_i;
95
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
96
output [31:0] m1_wb_dat_o;
97
output        m1_wb_ack_o, m1_wb_err_o;
98
 
99
// WISHBONE MASTER 2
100
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
101
input   [3:0] m2_wb_sel_i;
102
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
103
output [31:0] m2_wb_dat_o;
104
output        m2_wb_ack_o, m2_wb_err_o;
105
 
106
// WISHBONE slave 1
107
input  [31:0] s1_wb_dat_i;
108
input         s1_wb_ack_i, s1_wb_err_i;
109
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
110
output  [3:0] s1_wb_sel_o;
111
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
112
 
113
// WISHBONE slave 2
114
input  [31:0] s2_wb_dat_i;
115
input         s2_wb_ack_i, s2_wb_err_i;
116
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
117
output  [3:0] s2_wb_sel_o;
118
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
119
 
120
reg           m1_in_progress;
121
reg           m2_in_progress;
122
reg    [31:0] s1_wb_adr_o;
123
reg     [3:0] s1_wb_sel_o;
124
reg           s1_wb_we_o;
125
reg    [31:0] s1_wb_dat_o;
126
reg           s1_wb_cyc_o;
127
reg           s1_wb_stb_o;
128
reg    [31:0] s2_wb_adr_o;
129
reg     [3:0] s2_wb_sel_o;
130
reg           s2_wb_we_o;
131
reg    [31:0] s2_wb_dat_o;
132
reg           s2_wb_cyc_o;
133
reg           s2_wb_stb_o;
134
 
135
reg           m1_wb_ack_o;
136
reg    [31:0] m1_wb_dat_o;
137
reg           m2_wb_ack_o;
138
reg    [31:0] m2_wb_dat_o;
139
 
140
reg           m1_wb_err_o;
141
reg           m2_wb_err_o;
142
 
143
wire m_wb_access_finished;
144
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
145
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
146
 
147
always @ (posedge wb_clk_i or posedge wb_rst_i)
148
begin
149
  if(wb_rst_i)
150
    begin
151
      m1_in_progress <=#Tp 0;
152
      m2_in_progress <=#Tp 0;
153
      s1_wb_adr_o    <=#Tp 0;
154
      s1_wb_sel_o    <=#Tp 0;
155
      s1_wb_we_o     <=#Tp 0;
156
      s1_wb_dat_o    <=#Tp 0;
157
      s1_wb_cyc_o    <=#Tp 0;
158
      s1_wb_stb_o    <=#Tp 0;
159
      s2_wb_adr_o    <=#Tp 0;
160
      s2_wb_sel_o    <=#Tp 0;
161
      s2_wb_we_o     <=#Tp 0;
162
      s2_wb_dat_o    <=#Tp 0;
163
      s2_wb_cyc_o    <=#Tp 0;
164
      s2_wb_stb_o    <=#Tp 0;
165
    end
166
  else
167
    begin
168
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
169
        5'b00_10_0, 5'b00_11_0 :
170
          begin
171
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
172
            if(`M1_ADDRESSED_S1)
173
              begin
174
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
175
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
176
                s1_wb_we_o  <=#Tp m1_wb_we_i;
177
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
178
                s1_wb_cyc_o <=#Tp 1'b1;
179
                s1_wb_stb_o <=#Tp 1'b1;
180
              end
181
            else if(`M1_ADDRESSED_S2)
182
              begin
183
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
184
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
185
                s2_wb_we_o  <=#Tp m1_wb_we_i;
186
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
187
                s2_wb_cyc_o <=#Tp 1'b1;
188
                s2_wb_stb_o <=#Tp 1'b1;
189
              end
190
            else
191
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
192
          end
193
        5'b00_01_0 :
194
          begin
195
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
196
            if(`M2_ADDRESSED_S1)
197
              begin
198
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
199
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
200
                s1_wb_we_o  <=#Tp m2_wb_we_i;
201
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
202
                s1_wb_cyc_o <=#Tp 1'b1;
203
                s1_wb_stb_o <=#Tp 1'b1;
204
              end
205
            else if(`M2_ADDRESSED_S2)
206
              begin
207
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
208
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
209
                s2_wb_we_o  <=#Tp m2_wb_we_i;
210
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
211
                s2_wb_cyc_o <=#Tp 1'b1;
212
                s2_wb_stb_o <=#Tp 1'b1;
213
              end
214
            else
215
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
216
          end
217
        5'b10_10_1, 5'b10_11_1 :
218
          begin
219
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
220
            if(`M1_ADDRESSED_S1)
221
              begin
222
                s1_wb_cyc_o <=#Tp 1'b0;
223
                s1_wb_stb_o <=#Tp 1'b0;
224
              end
225
            else if(`M1_ADDRESSED_S2)
226
              begin
227
                s2_wb_cyc_o <=#Tp 1'b0;
228
                s2_wb_stb_o <=#Tp 1'b0;
229
              end
230
          end
231
        5'b01_01_1, 5'b01_11_1 :
232
          begin
233
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
234
            if(`M2_ADDRESSED_S1)
235
              begin
236
                s1_wb_cyc_o <=#Tp 1'b0;
237
                s1_wb_stb_o <=#Tp 1'b0;
238
              end
239
            else if(`M2_ADDRESSED_S2)
240
              begin
241
                s2_wb_cyc_o <=#Tp 1'b0;
242
                s2_wb_stb_o <=#Tp 1'b0;
243
              end
244
          end
245
      endcase
246
    end
247
end
248
 
249
// Generating Ack for master 1
250
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
251
begin
252
  if(m1_in_progress)
253
    begin
254
      if(`M1_ADDRESSED_S1) begin
255
        m1_wb_ack_o <= s1_wb_ack_i;
256
        m1_wb_dat_o <= s1_wb_dat_i;
257
      end
258
      else if(`M1_ADDRESSED_S2) begin
259
        m1_wb_ack_o <= s2_wb_ack_i;
260
        m1_wb_dat_o <= s2_wb_dat_i;
261
      end
262
    end
263
  else
264
    m1_wb_ack_o <= 0;
265
end
266
 
267
 
268
// Generating Ack for master 2
269
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
270
begin
271
  if(m2_in_progress)
272
    begin
273
      if(`M2_ADDRESSED_S1) begin
274
        m2_wb_ack_o <= s1_wb_ack_i;
275
        m2_wb_dat_o <= s1_wb_dat_i;
276
      end
277
      else if(`M2_ADDRESSED_S2) begin
278
        m2_wb_ack_o <= s2_wb_ack_i;
279
        m2_wb_dat_o <= s2_wb_dat_i;
280
      end
281
    end
282
  else
283
    m2_wb_ack_o <= 0;
284
end
285
 
286
 
287
// Generating Err for master 1
288
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
289
          m1_wb_cyc_i or m1_wb_stb_i)
290
begin
291
  if(m1_in_progress)  begin
292
    if(`M1_ADDRESSED_S1)
293
      m1_wb_err_o <= s1_wb_err_i;
294
    else if(`M1_ADDRESSED_S2)
295
      m1_wb_err_o <= s2_wb_err_i;
296
  end
297
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
298
    m1_wb_err_o <= 1'b1;
299
  else
300
    m1_wb_err_o <= 1'b0;
301
end
302
 
303
 
304
// Generating Err for master 2
305
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
306
          m2_wb_cyc_i or m2_wb_stb_i)
307
begin
308
  if(m2_in_progress)  begin
309
    if(`M2_ADDRESSED_S1)
310
      m2_wb_err_o <= s1_wb_err_i;
311
    else if(`M2_ADDRESSED_S2)
312
      m2_wb_err_o <= s2_wb_err_i;
313
  end
314
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
315
    m2_wb_err_o <= 1'b1;
316
  else
317
    m2_wb_err_o <= 1'b0;
318
end
319
 
320
 
321
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
322
 
323
 
324
// Activity monitor
325
integer cnt;
326
always @ (posedge wb_clk_i or posedge wb_rst_i)
327
begin
328
  if(wb_rst_i)
329
    cnt <=#Tp 0;
330
  else
331
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
332
    cnt <=#Tp 0;
333
  else
334
  if(s1_wb_cyc_o | s2_wb_cyc_o)
335
    cnt <=#Tp cnt+1;
336
end
337
 
338
always @ (posedge wb_clk_i)
339
begin
340
  if(cnt==1000) begin
341
    $display("(%0t) ERROR: WB activity ??? ", $time);
342
    if(s1_wb_cyc_o) begin
343
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
344
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
345
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
346
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
347
    end
348 160 mohor
    else if(s2_wb_cyc_o) begin
349 129 mohor
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
350
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
351
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
352
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
353
    end
354
 
355
    $stop;
356
  end
357
end
358
 
359
 
360 160 mohor
always @ (posedge wb_clk_i)
361
begin
362
  if(s1_wb_err_i & s1_wb_cyc_o) begin
363
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
364
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
365
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
366
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
367
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
368
    $stop;
369
  end
370
  if(s2_wb_err_i & s2_wb_cyc_o) begin
371
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
372
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
373
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
374
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
375
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
376
    $stop;
377
  end
378
end
379 129 mohor
 
380 160 mohor
 
381
 
382 129 mohor
endmodule

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