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1 129 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_cop.v                                                   ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
44 212 mohor
// Revision 1.2  2002/09/09 12:54:13  mohor
45
// error acknowledge cycle termination added to display.
46
//
47 160 mohor
// Revision 1.1  2002/08/14 17:16:07  mohor
48
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
49
// interfaces:
50
// - Host connects to the master interface
51
// - Ethernet master (DMA) connects to the second master interface
52
// - Memory interface connects to the slave interface
53
// - Ethernet slave interface (access to registers and BDs) connects to second
54
//   slave interface
55 129 mohor
//
56
//
57
//
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//
59 160 mohor
//
60 129 mohor
 
61
`include "tb_eth_defines.v"
62
`include "timescale.v"
63
 
64
module eth_cop
65
(
66
  // WISHBONE common
67
  wb_clk_i, wb_rst_i,
68
 
69
  // WISHBONE MASTER 1
70
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
71
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
72
  m1_wb_err_o,
73
 
74
  // WISHBONE MASTER 2
75
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
76
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
77
  m2_wb_err_o,
78
 
79
  // WISHBONE slave 1
80
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
81
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
82
        s1_wb_dat_o,
83
 
84
  // WISHBONE slave 2
85
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
86
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
87
        s2_wb_dat_o
88
);
89
 
90
parameter Tp=1;
91
 
92
// WISHBONE common
93
input wb_clk_i, wb_rst_i;
94
 
95
// WISHBONE MASTER 1
96
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
97
input   [3:0] m1_wb_sel_i;
98
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
99
output [31:0] m1_wb_dat_o;
100
output        m1_wb_ack_o, m1_wb_err_o;
101
 
102
// WISHBONE MASTER 2
103
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
104
input   [3:0] m2_wb_sel_i;
105
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
106
output [31:0] m2_wb_dat_o;
107
output        m2_wb_ack_o, m2_wb_err_o;
108
 
109
// WISHBONE slave 1
110
input  [31:0] s1_wb_dat_i;
111
input         s1_wb_ack_i, s1_wb_err_i;
112
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
113
output  [3:0] s1_wb_sel_o;
114
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
115
 
116
// WISHBONE slave 2
117
input  [31:0] s2_wb_dat_i;
118
input         s2_wb_ack_i, s2_wb_err_i;
119
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
120
output  [3:0] s2_wb_sel_o;
121
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
122
 
123
reg           m1_in_progress;
124
reg           m2_in_progress;
125
reg    [31:0] s1_wb_adr_o;
126
reg     [3:0] s1_wb_sel_o;
127
reg           s1_wb_we_o;
128
reg    [31:0] s1_wb_dat_o;
129
reg           s1_wb_cyc_o;
130
reg           s1_wb_stb_o;
131
reg    [31:0] s2_wb_adr_o;
132
reg     [3:0] s2_wb_sel_o;
133
reg           s2_wb_we_o;
134
reg    [31:0] s2_wb_dat_o;
135
reg           s2_wb_cyc_o;
136
reg           s2_wb_stb_o;
137
 
138
reg           m1_wb_ack_o;
139
reg    [31:0] m1_wb_dat_o;
140
reg           m2_wb_ack_o;
141
reg    [31:0] m2_wb_dat_o;
142
 
143
reg           m1_wb_err_o;
144
reg           m2_wb_err_o;
145
 
146
wire m_wb_access_finished;
147
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
148
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
149
 
150
always @ (posedge wb_clk_i or posedge wb_rst_i)
151
begin
152
  if(wb_rst_i)
153
    begin
154
      m1_in_progress <=#Tp 0;
155
      m2_in_progress <=#Tp 0;
156
      s1_wb_adr_o    <=#Tp 0;
157
      s1_wb_sel_o    <=#Tp 0;
158
      s1_wb_we_o     <=#Tp 0;
159
      s1_wb_dat_o    <=#Tp 0;
160
      s1_wb_cyc_o    <=#Tp 0;
161
      s1_wb_stb_o    <=#Tp 0;
162
      s2_wb_adr_o    <=#Tp 0;
163
      s2_wb_sel_o    <=#Tp 0;
164
      s2_wb_we_o     <=#Tp 0;
165
      s2_wb_dat_o    <=#Tp 0;
166
      s2_wb_cyc_o    <=#Tp 0;
167
      s2_wb_stb_o    <=#Tp 0;
168
    end
169
  else
170
    begin
171
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
172
        5'b00_10_0, 5'b00_11_0 :
173
          begin
174
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
175
            if(`M1_ADDRESSED_S1)
176
              begin
177
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
178
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
179
                s1_wb_we_o  <=#Tp m1_wb_we_i;
180
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
181
                s1_wb_cyc_o <=#Tp 1'b1;
182
                s1_wb_stb_o <=#Tp 1'b1;
183
              end
184
            else if(`M1_ADDRESSED_S2)
185
              begin
186
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
187
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
188
                s2_wb_we_o  <=#Tp m1_wb_we_i;
189
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
190
                s2_wb_cyc_o <=#Tp 1'b1;
191
                s2_wb_stb_o <=#Tp 1'b1;
192
              end
193
            else
194
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
195
          end
196
        5'b00_01_0 :
197
          begin
198
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
199
            if(`M2_ADDRESSED_S1)
200
              begin
201
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
202
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
203
                s1_wb_we_o  <=#Tp m2_wb_we_i;
204
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
205
                s1_wb_cyc_o <=#Tp 1'b1;
206
                s1_wb_stb_o <=#Tp 1'b1;
207
              end
208
            else if(`M2_ADDRESSED_S2)
209
              begin
210
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
211
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
212
                s2_wb_we_o  <=#Tp m2_wb_we_i;
213
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
214
                s2_wb_cyc_o <=#Tp 1'b1;
215
                s2_wb_stb_o <=#Tp 1'b1;
216
              end
217
            else
218
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
219
          end
220
        5'b10_10_1, 5'b10_11_1 :
221
          begin
222
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
223
            if(`M1_ADDRESSED_S1)
224
              begin
225
                s1_wb_cyc_o <=#Tp 1'b0;
226
                s1_wb_stb_o <=#Tp 1'b0;
227
              end
228
            else if(`M1_ADDRESSED_S2)
229
              begin
230
                s2_wb_cyc_o <=#Tp 1'b0;
231
                s2_wb_stb_o <=#Tp 1'b0;
232
              end
233
          end
234
        5'b01_01_1, 5'b01_11_1 :
235
          begin
236
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
237
            if(`M2_ADDRESSED_S1)
238
              begin
239
                s1_wb_cyc_o <=#Tp 1'b0;
240
                s1_wb_stb_o <=#Tp 1'b0;
241
              end
242
            else if(`M2_ADDRESSED_S2)
243
              begin
244
                s2_wb_cyc_o <=#Tp 1'b0;
245
                s2_wb_stb_o <=#Tp 1'b0;
246
              end
247
          end
248
      endcase
249
    end
250
end
251
 
252
// Generating Ack for master 1
253
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
254
begin
255
  if(m1_in_progress)
256
    begin
257
      if(`M1_ADDRESSED_S1) begin
258
        m1_wb_ack_o <= s1_wb_ack_i;
259
        m1_wb_dat_o <= s1_wb_dat_i;
260
      end
261
      else if(`M1_ADDRESSED_S2) begin
262
        m1_wb_ack_o <= s2_wb_ack_i;
263
        m1_wb_dat_o <= s2_wb_dat_i;
264
      end
265
    end
266
  else
267
    m1_wb_ack_o <= 0;
268
end
269
 
270
 
271
// Generating Ack for master 2
272
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
273
begin
274
  if(m2_in_progress)
275
    begin
276
      if(`M2_ADDRESSED_S1) begin
277
        m2_wb_ack_o <= s1_wb_ack_i;
278
        m2_wb_dat_o <= s1_wb_dat_i;
279
      end
280
      else if(`M2_ADDRESSED_S2) begin
281
        m2_wb_ack_o <= s2_wb_ack_i;
282
        m2_wb_dat_o <= s2_wb_dat_i;
283
      end
284
    end
285
  else
286
    m2_wb_ack_o <= 0;
287
end
288
 
289
 
290
// Generating Err for master 1
291
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
292
          m1_wb_cyc_i or m1_wb_stb_i)
293
begin
294
  if(m1_in_progress)  begin
295
    if(`M1_ADDRESSED_S1)
296
      m1_wb_err_o <= s1_wb_err_i;
297
    else if(`M1_ADDRESSED_S2)
298
      m1_wb_err_o <= s2_wb_err_i;
299
  end
300
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
301
    m1_wb_err_o <= 1'b1;
302
  else
303
    m1_wb_err_o <= 1'b0;
304
end
305
 
306
 
307
// Generating Err for master 2
308
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
309
          m2_wb_cyc_i or m2_wb_stb_i)
310
begin
311
  if(m2_in_progress)  begin
312
    if(`M2_ADDRESSED_S1)
313
      m2_wb_err_o <= s1_wb_err_i;
314
    else if(`M2_ADDRESSED_S2)
315
      m2_wb_err_o <= s2_wb_err_i;
316
  end
317
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
318
    m2_wb_err_o <= 1'b1;
319
  else
320
    m2_wb_err_o <= 1'b0;
321
end
322
 
323
 
324
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
325
 
326
 
327
// Activity monitor
328
integer cnt;
329
always @ (posedge wb_clk_i or posedge wb_rst_i)
330
begin
331
  if(wb_rst_i)
332
    cnt <=#Tp 0;
333
  else
334
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
335
    cnt <=#Tp 0;
336
  else
337
  if(s1_wb_cyc_o | s2_wb_cyc_o)
338
    cnt <=#Tp cnt+1;
339
end
340
 
341
always @ (posedge wb_clk_i)
342
begin
343
  if(cnt==1000) begin
344 212 mohor
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
345 129 mohor
    if(s1_wb_cyc_o) begin
346
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
347
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
348
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
349
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
350
    end
351 160 mohor
    else if(s2_wb_cyc_o) begin
352 129 mohor
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
353
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
354
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
355
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
356
    end
357
 
358
    $stop;
359
  end
360
end
361
 
362
 
363 160 mohor
always @ (posedge wb_clk_i)
364
begin
365
  if(s1_wb_err_i & s1_wb_cyc_o) begin
366
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
367
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
368
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
369
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
370
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
371
    $stop;
372
  end
373
  if(s2_wb_err_i & s2_wb_cyc_o) begin
374
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
375
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
376
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
377
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
378
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
379
    $stop;
380
  end
381
end
382 129 mohor
 
383 160 mohor
 
384
 
385 129 mohor
endmodule

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