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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Blame information for rev 346

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_macstatus.v                                             ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
11 168 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
16 168 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
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//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.16  2005/02/21 10:42:11  igorm
45
// Defer indication fixed.
46
//
47 325 igorm
// Revision 1.15  2003/01/30 13:28:19  tadejm
48
// Defer indication changed.
49
//
50 276 tadejm
// Revision 1.14  2002/11/22 01:57:06  mohor
51
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
52
// synchronized.
53
//
54 261 mohor
// Revision 1.13  2002/11/13 22:30:58  tadejm
55
// Late collision is reported only when not in the full duplex.
56
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
57
// of the received byte cnt).
58
//
59 242 tadejm
// Revision 1.12  2002/09/12 14:50:16  mohor
60
// CarrierSenseLost bug fixed when operating in full duplex mode.
61
//
62 168 mohor
// Revision 1.11  2002/09/04 18:38:03  mohor
63
// CarrierSenseLost status is not set when working in loopback mode.
64
//
65 146 mohor
// Revision 1.10  2002/07/25 18:17:46  mohor
66
// InvalidSymbol generation changed.
67
//
68 126 mohor
// Revision 1.9  2002/04/22 13:51:44  mohor
69
// Short frame and ReceivedLengthOK were not detected correctly.
70
//
71 101 mohor
// Revision 1.8  2002/02/18 10:40:17  mohor
72
// Small fixes.
73
//
74 70 mohor
// Revision 1.7  2002/02/15 17:07:39  mohor
75
// Status was not written correctly when frames were discarted because of
76
// address mismatch.
77
//
78 64 mohor
// Revision 1.6  2002/02/11 09:18:21  mohor
79
// Tx status is written back to the BD.
80
//
81 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
82
// Rx status is written back to the BD.
83
//
84 42 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
85
// Link in the header changed.
86
//
87 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
88
// eth_timescale.v changed to timescale.v This is done because of the
89
// simulation of the few cores in a one joined project.
90
//
91 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
92
// Few little NCSIM warnings fixed.
93
//
94 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
95
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
96
// Include files fixed to contain no path.
97
// File names and module names changed ta have a eth_ prologue in the name.
98
// File eth_timescale.v is used to define timescale
99
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
100
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
101
// and Mdo_OE. The bidirectional signal must be created on the top level. This
102
// is done due to the ASIC tools.
103
//
104 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
105
// Directory structure changed. Files checked and joind together.
106
//
107
//
108
//
109
//
110
//
111
 
112 22 mohor
`include "timescale.v"
113 15 mohor
 
114
 
115
module eth_macstatus(
116 42 mohor
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
117 15 mohor
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
118 261 mohor
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
119 42 mohor
                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
120
                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
121 43 mohor
                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
122 325 igorm
                      RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
123 168 mohor
                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
124
                      r_FullD
125 15 mohor
                    );
126
 
127
 
128
 
129
parameter Tp = 1;
130
 
131
 
132
input         MRxClk;
133
input         Reset;
134
input         RxCrcError;
135
input         MRxErr;
136
input         MRxDV;
137
 
138
input         RxStateSFD;
139
input   [1:0] RxStateData;
140
input         RxStatePreamble;
141
input         RxStateIdle;
142
input         Transmitting;
143
input  [15:0] RxByteCnt;
144
input         RxByteCntEq0;
145
input         RxByteCntGreat2;
146
input         RxByteCntMaxFrame;
147 42 mohor
input   [3:0] MRxD;
148
input         Collision;
149
input   [5:0] CollValid;
150
input         r_RecSmall;
151
input  [15:0] r_MinFL;
152
input  [15:0] r_MaxFL;
153
input         r_HugEn;
154 43 mohor
input         StartTxDone;
155
input         StartTxAbort;
156
input   [3:0] RetryCnt;
157
input         MTxClk;
158
input         MaxCollisionOccured;
159
input         LateCollision;
160 276 tadejm
input         DeferIndication;
161 43 mohor
input         TxStartFrm;
162
input         StatePreamble;
163
input   [1:0] StateData;
164
input         CarrierSense;
165
input         TxUsedData;
166 146 mohor
input         Loopback;
167 168 mohor
input         r_FullD;
168 15 mohor
 
169 43 mohor
 
170 15 mohor
output        ReceivedLengthOK;
171
output        ReceiveEnd;
172
output        ReceivedPacketGood;
173 42 mohor
output        InvalidSymbol;
174
output        LatchedCrcError;
175
output        RxLateCollision;
176
output        ShortFrame;
177
output        DribbleNibble;
178
output        ReceivedPacketTooBig;
179
output        LoadRxStatus;
180 43 mohor
output  [3:0] RetryCntLatched;
181
output        RetryLimit;
182
output        LateCollLatched;
183
output        DeferLatched;
184 325 igorm
input         RstDeferLatched;
185 43 mohor
output        CarrierSenseLost;
186 126 mohor
output        LatchedMRxErr;
187 15 mohor
 
188 43 mohor
 
189 15 mohor
reg           ReceiveEnd;
190
 
191
reg           LatchedCrcError;
192
reg           LatchedMRxErr;
193 42 mohor
reg           LoadRxStatus;
194
reg           InvalidSymbol;
195 43 mohor
reg     [3:0] RetryCntLatched;
196
reg           RetryLimit;
197
reg           LateCollLatched;
198
reg           DeferLatched;
199
reg           CarrierSenseLost;
200 15 mohor
 
201
wire          TakeSample;
202 42 mohor
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
203 15 mohor
 
204
// Crc error
205
always @ (posedge MRxClk or posedge Reset)
206
begin
207
  if(Reset)
208
    LatchedCrcError <=#Tp 1'b0;
209
  else
210 42 mohor
  if(RxStateSFD)
211
    LatchedCrcError <=#Tp 1'b0;
212
  else
213
  if(RxStateData[0])
214
    LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
215 15 mohor
end
216
 
217
 
218
// LatchedMRxErr
219
always @ (posedge MRxClk or posedge Reset)
220
begin
221
  if(Reset)
222
    LatchedMRxErr <=#Tp 1'b0;
223
  else
224 18 mohor
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
225 15 mohor
    LatchedMRxErr <=#Tp 1'b1;
226 126 mohor
  else
227
    LatchedMRxErr <=#Tp 1'b0;
228 15 mohor
end
229
 
230
 
231
// ReceivedPacketGood
232 126 mohor
assign ReceivedPacketGood = ~LatchedCrcError;
233 15 mohor
 
234
 
235
// ReceivedLengthOK
236 101 mohor
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
237 15 mohor
 
238
 
239
 
240 42 mohor
 
241
 
242
// Time to take a sample
243 242 tadejm
//assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
244
assign TakeSample = (|RxStateData)   & (~MRxDV)                    |
245
                      RxStateData[0] &   MRxDV & RxByteCntMaxFrame;
246 42 mohor
 
247
 
248
// LoadRxStatus
249 15 mohor
always @ (posedge MRxClk or posedge Reset)
250
begin
251
  if(Reset)
252 42 mohor
    LoadRxStatus <=#Tp 1'b0;
253 15 mohor
  else
254 42 mohor
    LoadRxStatus <=#Tp TakeSample;
255 15 mohor
end
256
 
257
 
258
 
259 42 mohor
// ReceiveEnd
260
always @ (posedge MRxClk or posedge Reset)
261
begin
262
  if(Reset)
263
    ReceiveEnd  <=#Tp 1'b0;
264
  else
265
    ReceiveEnd  <=#Tp LoadRxStatus;
266
end
267 15 mohor
 
268
 
269 42 mohor
// Invalid Symbol received during 100Mbps mode
270 126 mohor
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
271 42 mohor
 
272
 
273
// InvalidSymbol
274 15 mohor
always @ (posedge MRxClk or posedge Reset)
275
begin
276
  if(Reset)
277 42 mohor
    InvalidSymbol <=#Tp 1'b0;
278 15 mohor
  else
279 42 mohor
  if(LoadRxStatus & ~SetInvalidSymbol)
280
    InvalidSymbol <=#Tp 1'b0;
281
  else
282
  if(SetInvalidSymbol)
283
    InvalidSymbol <=#Tp 1'b1;
284 15 mohor
end
285
 
286
 
287 42 mohor
// Late Collision
288 15 mohor
 
289 42 mohor
reg RxLateCollision;
290
reg RxColWindow;
291
// Collision Window
292 15 mohor
always @ (posedge MRxClk or posedge Reset)
293
begin
294
  if(Reset)
295 42 mohor
    RxLateCollision <=#Tp 1'b0;
296 15 mohor
  else
297 42 mohor
  if(LoadRxStatus)
298
    RxLateCollision <=#Tp 1'b0;
299
  else
300 242 tadejm
  if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
301 42 mohor
    RxLateCollision <=#Tp 1'b1;
302 15 mohor
end
303
 
304 42 mohor
// Collision Window
305
always @ (posedge MRxClk or posedge Reset)
306
begin
307
  if(Reset)
308
    RxColWindow <=#Tp 1'b1;
309
  else
310
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
311
    RxColWindow <=#Tp 1'b0;
312
  else
313
  if(RxStateIdle)
314
    RxColWindow <=#Tp 1'b1;
315
end
316 15 mohor
 
317 42 mohor
 
318
// ShortFrame
319
reg ShortFrame;
320
always @ (posedge MRxClk or posedge Reset)
321
begin
322
  if(Reset)
323
    ShortFrame <=#Tp 1'b0;
324
  else
325
  if(LoadRxStatus)
326
    ShortFrame <=#Tp 1'b0;
327
  else
328
  if(TakeSample)
329 101 mohor
    ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
330 42 mohor
end
331
 
332
 
333
// DribbleNibble
334
reg DribbleNibble;
335
always @ (posedge MRxClk or posedge Reset)
336
begin
337
  if(Reset)
338
    DribbleNibble <=#Tp 1'b0;
339
  else
340
  if(RxStateSFD)
341
    DribbleNibble <=#Tp 1'b0;
342
  else
343
  if(~MRxDV & RxStateData[1])
344
    DribbleNibble <=#Tp 1'b1;
345
end
346
 
347
 
348
reg ReceivedPacketTooBig;
349
always @ (posedge MRxClk or posedge Reset)
350
begin
351
  if(Reset)
352
    ReceivedPacketTooBig <=#Tp 1'b0;
353
  else
354
  if(LoadRxStatus)
355
    ReceivedPacketTooBig <=#Tp 1'b0;
356
  else
357
  if(TakeSample)
358
    ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
359
end
360
 
361 43 mohor
 
362
 
363
// Latched Retry counter for tx status
364
always @ (posedge MTxClk or posedge Reset)
365
begin
366
  if(Reset)
367
    RetryCntLatched <=#Tp 4'h0;
368
  else
369
  if(StartTxDone | StartTxAbort)
370
    RetryCntLatched <=#Tp RetryCnt;
371
end
372
 
373
 
374
// Latched Retransmission limit
375
always @ (posedge MTxClk or posedge Reset)
376
begin
377
  if(Reset)
378 333 igorm
    RetryLimit <=#Tp 1'h0;
379 43 mohor
  else
380
  if(StartTxDone | StartTxAbort)
381
    RetryLimit <=#Tp MaxCollisionOccured;
382
end
383
 
384
 
385
// Latched Late Collision
386
always @ (posedge MTxClk or posedge Reset)
387
begin
388
  if(Reset)
389
    LateCollLatched <=#Tp 1'b0;
390
  else
391
  if(StartTxDone | StartTxAbort)
392
    LateCollLatched <=#Tp LateCollision;
393
end
394
 
395
 
396
 
397
// Latched Defer state
398
always @ (posedge MTxClk or posedge Reset)
399
begin
400
  if(Reset)
401
    DeferLatched <=#Tp 1'b0;
402
  else
403 325 igorm
  if(DeferIndication)
404 43 mohor
    DeferLatched <=#Tp 1'b1;
405
  else
406 325 igorm
  if(RstDeferLatched)
407 43 mohor
    DeferLatched <=#Tp 1'b0;
408
end
409
 
410
 
411
// CarrierSenseLost
412
always @ (posedge MTxClk or posedge Reset)
413
begin
414
  if(Reset)
415
    CarrierSenseLost <=#Tp 1'b0;
416
  else
417 168 mohor
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
418 43 mohor
    CarrierSenseLost <=#Tp 1'b1;
419
  else
420
  if(TxStartFrm)
421
    CarrierSenseLost <=#Tp 1'b0;
422
end
423
 
424
 
425 15 mohor
endmodule

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