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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_outputcontrol.v] - Blame information for rev 346

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_outputcontrol.v                                         ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
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// Revision 1.2  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.3  2001/06/01 22:28:56  mohor
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// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
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//
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//
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`include "timescale.v"
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module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
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parameter Tp = 1;
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input         Clk;                // Host Clock
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input         Reset;              // General Reset
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input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
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input         NoPre;              // No Preamble (no 32-bit preamble)
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input         InProgress;         // Operation in progress
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input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
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input   [6:0] BitCounter;         // Bit Counter
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input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
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output        Mdo;                // MII Management Data Output
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output        MdoEn;              // MII Management Data Output Enable
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wire          SerialEn;
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reg           MdoEn_2d;
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reg           MdoEn_d;
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reg           MdoEn;
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reg           Mdo_2d;
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reg           Mdo_d;
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reg           Mdo;                // MII Management Data Output
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// Generation of the Serial Enable signal (enables the serialization of the data)
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assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
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                | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
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// Generation of the MdoEn signal
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always @ (posedge Clk or posedge Reset)
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begin
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  if(Reset)
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    begin
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      MdoEn_2d <= #Tp 1'b0;
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      MdoEn_d <= #Tp 1'b0;
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      MdoEn <= #Tp 1'b0;
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    end
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  else
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    begin
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      if(MdcEn_n)
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        begin
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          MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
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          MdoEn_d <= #Tp MdoEn_2d;
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          MdoEn <= #Tp MdoEn_d;
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        end
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    end
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end
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// Generation of the Mdo signal.
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always @ (posedge Clk or posedge Reset)
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begin
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  if(Reset)
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    begin
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      Mdo_2d <= #Tp 1'b0;
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      Mdo_d <= #Tp 1'b0;
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      Mdo <= #Tp 1'b0;
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    end
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  else
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    begin
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      if(MdcEn_n)
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        begin
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          Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
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          Mdo_d <= #Tp ShiftedBit | Mdo_2d;
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          Mdo <= #Tp Mdo_d;
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        end
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    end
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end
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endmodule

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