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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_random.v] - Blame information for rev 352

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_random.v                                                ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
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// Revision 1.2  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.3  2001/06/19 18:16:40  mohor
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// TxClk changed to MTxClk (as discribed in the documentation).
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// Crc changed so only one file can be used instead of two.
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//
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// Revision 1.2  2001/06/19 10:38:07  mohor
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// Minor changes in header.
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//
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// Revision 1.1  2001/06/19 10:27:57  mohor
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// TxEthMAC initial release.
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//
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//
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//
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//
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`include "timescale.v"
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module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
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                   RandomEq0, RandomEqByteCnt);
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input MTxClk;
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input Reset;
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input StateJam;
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input StateJam_q;
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input [3:0] RetryCnt;
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input [15:0] NibCnt;
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input [9:0] ByteCnt;
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output RandomEq0;
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output RandomEqByteCnt;
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wire Feedback;
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reg [9:0] x;
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wire [9:0] Random;
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reg  [9:0] RandomLatched;
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always @ (posedge MTxClk or posedge Reset)
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begin
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  if(Reset)
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    x[9:0] <=  0;
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  else
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    x[9:0] <=  {x[8:0], Feedback};
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end
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assign Feedback = ~(x[2] ^ x[9]);
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assign Random [0] = x[0];
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assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
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assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
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assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
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assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
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assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
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assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
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assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
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assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
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assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
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always @ (posedge MTxClk or posedge Reset)
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begin
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  if(Reset)
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    RandomLatched <=  10'h000;
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  else
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    begin
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      if(StateJam & StateJam_q)
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        RandomLatched <=  Random;
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    end
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end
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// Random Number == 0      IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
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assign RandomEq0 = RandomLatched == 10'h0;
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assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
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endmodule

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