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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Blame information for rev 353

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_receivecontrol.v                                        ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 272 tadejm
// Revision 1.4  2002/11/22 01:57:06  mohor
45
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
46
// synchronized.
47
//
48 261 mohor
// Revision 1.3  2002/01/23 10:28:16  mohor
49
// Link in the header changed.
50
//
51 37 mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
52
// eth_timescale.v changed to timescale.v This is done because of the
53
// simulation of the few cores in a one joined project.
54
//
55 22 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
56
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
57
// Include files fixed to contain no path.
58
// File names and module names changed ta have a eth_ prologue in the name.
59
// File eth_timescale.v is used to define timescale
60
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
61
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
62
// and Mdo_OE. The bidirectional signal must be created on the top level. This
63
// is done due to the ASIC tools.
64
//
65 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
66
// Directory structure changed. Files checked and joind together.
67
//
68
// Revision 1.1  2001/07/03 12:51:54  mohor
69
// Initial release of the MAC Control module.
70
//
71
//
72
//
73
//
74
//
75
 
76
 
77 22 mohor
`include "timescale.v"
78 15 mohor
 
79
 
80
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
81 261 mohor
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
82 15 mohor
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
83 261 mohor
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
84 272 tadejm
                           RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
85 15 mohor
                          );
86
 
87
 
88
input       MTxClk;
89
input       MRxClk;
90
input       TxReset;
91
input       RxReset;
92
input [7:0] RxData;
93
input       RxValid;
94
input       RxStartFrm;
95
input       RxEndFrm;
96
input       RxFlow;
97
input       ReceiveEnd;
98
input [47:0]MAC;
99
input       DlyCrcEn;
100
input       TxDoneIn;
101
input       TxAbortIn;
102
input       TxStartFrmOut;
103
input       ReceivedLengthOK;
104
input       ReceivedPacketGood;
105
input       TxUsedDataOutDetected;
106 272 tadejm
input       RxStatusWriteLatched_sync2;
107
input       r_PassAll;
108 15 mohor
 
109
output      Pause;
110
output      ReceivedPauseFrm;
111 261 mohor
output      AddressOK;
112
output      SetPauseTimer;
113 15 mohor
 
114 272 tadejm
 
115 15 mohor
reg         Pause;
116
reg         AddressOK;                // Multicast or unicast address detected
117
reg         TypeLengthOK;             // Type/Length field contains 0x8808
118
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
119
reg         OpCodeOK;                 // PAUSE opcode detected (0x0001)
120
reg  [2:0]  DlyCrcCnt;
121
reg  [4:0]  ByteCnt;
122
reg [15:0]  AssembledTimerValue;
123
reg [15:0]  LatchedTimerValue;
124
reg         ReceivedPauseFrm;
125
reg         ReceivedPauseFrmWAddr;
126
reg         PauseTimerEq0_sync1;
127
reg         PauseTimerEq0_sync2;
128
reg [15:0]  PauseTimer;
129
reg         Divider2;
130
reg  [5:0]  SlotTimer;
131
 
132
wire [47:0] ReservedMulticast;        // 0x0180C2000001
133
wire [15:0] TypeLength;               // 0x8808
134
wire        ResetByteCnt;             // 
135
wire        IncrementByteCnt;         // 
136
wire        ByteCntEq0;               // ByteCnt = 0
137
wire        ByteCntEq1;               // ByteCnt = 1
138
wire        ByteCntEq2;               // ByteCnt = 2
139
wire        ByteCntEq3;               // ByteCnt = 3
140
wire        ByteCntEq4;               // ByteCnt = 4
141
wire        ByteCntEq5;               // ByteCnt = 5
142
wire        ByteCntEq12;              // ByteCnt = 12
143
wire        ByteCntEq13;              // ByteCnt = 13
144
wire        ByteCntEq14;              // ByteCnt = 14
145
wire        ByteCntEq15;              // ByteCnt = 15
146
wire        ByteCntEq16;              // ByteCnt = 16
147
wire        ByteCntEq17;              // ByteCnt = 17
148
wire        ByteCntEq18;              // ByteCnt = 18
149
wire        DecrementPauseTimer;      // 
150
wire        PauseTimerEq0;            // 
151
wire        ResetSlotTimer;           // 
152
wire        IncrementSlotTimer;       // 
153
wire        SlotFinished;             // 
154
 
155
 
156
 
157
// Reserved multicast address and Type/Length for PAUSE control
158
assign ReservedMulticast = 48'h0180C2000001;
159
assign TypeLength = 16'h8808;
160
 
161
 
162
// Address Detection (Multicast or unicast)
163
always @ (posedge MRxClk or posedge RxReset)
164
begin
165
  if(RxReset)
166 352 olof
    AddressOK <=  1'b0;
167 15 mohor
  else
168
  if(DetectionWindow & ByteCntEq0)
169 352 olof
    AddressOK <=   RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
170 15 mohor
  else
171
  if(DetectionWindow & ByteCntEq1)
172 352 olof
    AddressOK <=  (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
173 15 mohor
  else
174
  if(DetectionWindow & ByteCntEq2)
175 352 olof
    AddressOK <=  (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
176 15 mohor
  else
177
  if(DetectionWindow & ByteCntEq3)
178 352 olof
    AddressOK <=  (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
179 15 mohor
  else
180
  if(DetectionWindow & ByteCntEq4)
181 352 olof
    AddressOK <=  (RxData[7:0] == ReservedMulticast[15:8]  | RxData[7:0] == MAC[15:8])  & AddressOK;
182 15 mohor
  else
183
  if(DetectionWindow & ByteCntEq5)
184 352 olof
    AddressOK <=  (RxData[7:0] == ReservedMulticast[7:0]   | RxData[7:0] == MAC[7:0])   & AddressOK;
185 15 mohor
  else
186
  if(ReceiveEnd)
187 352 olof
    AddressOK <=  1'b0;
188 15 mohor
end
189
 
190
 
191
 
192
// TypeLengthOK (Type/Length Control frame detected)
193
always @ (posedge MRxClk or posedge RxReset )
194
begin
195
  if(RxReset)
196 352 olof
    TypeLengthOK <=  1'b0;
197 15 mohor
  else
198
  if(DetectionWindow & ByteCntEq12)
199 352 olof
    TypeLengthOK <=  ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
200 15 mohor
  else
201
  if(DetectionWindow & ByteCntEq13)
202 352 olof
    TypeLengthOK <=  ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
203 15 mohor
  else
204
  if(ReceiveEnd)
205 352 olof
    TypeLengthOK <=  1'b0;
206 15 mohor
end
207
 
208
 
209
 
210
// Latch Control Frame Opcode
211
always @ (posedge MRxClk or posedge RxReset )
212
begin
213
  if(RxReset)
214 352 olof
    OpCodeOK <=  1'b0;
215 15 mohor
  else
216 272 tadejm
  if(ByteCntEq16)
217 352 olof
    OpCodeOK <=  1'b0;
218 15 mohor
  else
219
    begin
220
      if(DetectionWindow & ByteCntEq14)
221 352 olof
        OpCodeOK <=  ByteCntEq14 & RxData[7:0] == 8'h00;
222 15 mohor
 
223
      if(DetectionWindow & ByteCntEq15)
224 352 olof
        OpCodeOK <=  ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
225 15 mohor
    end
226
end
227
 
228
 
229
// ReceivedPauseFrmWAddr (+Address Check)
230
always @ (posedge MRxClk or posedge RxReset )
231
begin
232
  if(RxReset)
233 352 olof
    ReceivedPauseFrmWAddr <=  1'b0;
234 15 mohor
  else
235
  if(ReceiveEnd)
236 352 olof
    ReceivedPauseFrmWAddr <=  1'b0;
237 15 mohor
  else
238
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
239 352 olof
    ReceivedPauseFrmWAddr <=  1'b1;
240 15 mohor
end
241
 
242
 
243
 
244
// Assembling 16-bit timer value from two 8-bit data
245
always @ (posedge MRxClk or posedge RxReset )
246
begin
247
  if(RxReset)
248 352 olof
    AssembledTimerValue[15:0] <=  16'h0;
249 15 mohor
  else
250
  if(RxStartFrm)
251 352 olof
    AssembledTimerValue[15:0] <=  16'h0;
252 15 mohor
  else
253
    begin
254
      if(DetectionWindow & ByteCntEq16)
255 352 olof
        AssembledTimerValue[15:8] <=  RxData[7:0];
256 15 mohor
      if(DetectionWindow & ByteCntEq17)
257 352 olof
        AssembledTimerValue[7:0] <=  RxData[7:0];
258 15 mohor
    end
259
end
260
 
261
 
262
// Detection window (while PAUSE detection is possible)
263
always @ (posedge MRxClk or posedge RxReset )
264
begin
265
  if(RxReset)
266 352 olof
    DetectionWindow <=  1'b1;
267 15 mohor
  else
268
  if(ByteCntEq18)
269 352 olof
    DetectionWindow <=  1'b0;
270 15 mohor
  else
271
  if(ReceiveEnd)
272 352 olof
    DetectionWindow <=  1'b1;
273 15 mohor
end
274
 
275
 
276
 
277
// Latching Timer Value
278
always @ (posedge MRxClk or posedge RxReset )
279
begin
280
  if(RxReset)
281 352 olof
    LatchedTimerValue[15:0] <=  16'h0;
282 15 mohor
  else
283 261 mohor
  if(DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
284 352 olof
    LatchedTimerValue[15:0] <=  AssembledTimerValue[15:0];
285 15 mohor
  else
286
  if(ReceiveEnd)
287 352 olof
    LatchedTimerValue[15:0] <=  16'h0;
288 15 mohor
end
289
 
290
 
291
 
292
// Delayed CEC counter
293
always @ (posedge MRxClk or posedge RxReset)
294
begin
295
  if(RxReset)
296 352 olof
    DlyCrcCnt <=  3'h0;
297 15 mohor
  else
298
  if(RxValid & RxEndFrm)
299 352 olof
    DlyCrcCnt <=  3'h0;
300 15 mohor
  else
301
  if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
302 353 olof
    DlyCrcCnt <=  DlyCrcCnt + 3'd1;
303 15 mohor
end
304
 
305
 
306
assign ResetByteCnt = RxEndFrm;
307
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
308
 
309
 
310
// Byte counter
311
always @ (posedge MRxClk or posedge RxReset)
312
begin
313
  if(RxReset)
314 352 olof
    ByteCnt[4:0] <=  5'h0;
315 15 mohor
  else
316
  if(ResetByteCnt)
317 352 olof
    ByteCnt[4:0] <=  5'h0;
318 15 mohor
  else
319
  if(IncrementByteCnt)
320 353 olof
    ByteCnt[4:0] <=  ByteCnt[4:0] + 5'd1;
321 15 mohor
end
322
 
323
 
324
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
325
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
326
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
327
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
328
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
329
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
330
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
331
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
332
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
333
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
334
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
335
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
336
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
337
 
338
 
339
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
340
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
341
 
342
 
343
// PauseTimer[15:0]
344
always @ (posedge MRxClk or posedge RxReset)
345
begin
346
  if(RxReset)
347 352 olof
    PauseTimer[15:0] <=  16'h0;
348 15 mohor
  else
349
  if(SetPauseTimer)
350 352 olof
    PauseTimer[15:0] <=  LatchedTimerValue[15:0];
351 15 mohor
  else
352
  if(DecrementPauseTimer)
353 353 olof
    PauseTimer[15:0] <=  PauseTimer[15:0] - 16'd1;
354 15 mohor
end
355
 
356
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
357
 
358
 
359
 
360
// Synchronization of the pause timer
361
always @ (posedge MTxClk or posedge TxReset)
362
begin
363
  if(TxReset)
364
    begin
365 352 olof
      PauseTimerEq0_sync1 <=  1'b1;
366
      PauseTimerEq0_sync2 <=  1'b1;
367 15 mohor
    end
368
  else
369
    begin
370 352 olof
      PauseTimerEq0_sync1 <=  PauseTimerEq0;
371
      PauseTimerEq0_sync2 <=  PauseTimerEq0_sync1;
372 15 mohor
    end
373
end
374
 
375
 
376
// Pause signal generation
377
always @ (posedge MTxClk or posedge TxReset)
378
begin
379
  if(TxReset)
380 352 olof
    Pause <=  1'b0;
381 15 mohor
  else
382
  if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
383 352 olof
    Pause <=  RxFlow & ~PauseTimerEq0_sync2;
384 15 mohor
end
385
 
386
 
387
// Divider2 is used for incrementing the Slot timer every other clock
388
always @ (posedge MRxClk or posedge RxReset)
389
begin
390
  if(RxReset)
391 352 olof
    Divider2 <=  1'b0;
392 15 mohor
  else
393
  if(|PauseTimer[15:0] & RxFlow)
394 352 olof
    Divider2 <=  ~Divider2;
395 15 mohor
  else
396 352 olof
    Divider2 <=  1'b0;
397 15 mohor
end
398
 
399
 
400
assign ResetSlotTimer = RxReset;
401
assign IncrementSlotTimer =  Pause & RxFlow & Divider2;
402
 
403
 
404
// SlotTimer
405
always @ (posedge MRxClk or posedge RxReset)
406
begin
407
  if(RxReset)
408 352 olof
    SlotTimer[5:0] <=  6'h0;
409 15 mohor
  else
410
  if(ResetSlotTimer)
411 352 olof
    SlotTimer[5:0] <=  6'h0;
412 15 mohor
  else
413
  if(IncrementSlotTimer)
414 353 olof
    SlotTimer[5:0] <=  SlotTimer[5:0] + 6'd1;
415 15 mohor
end
416
 
417
 
418
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer;  // Slot is 512 bits (64 bytes)
419
 
420
 
421
 
422
// Pause Frame received
423
always @ (posedge MRxClk or posedge RxReset)
424
begin
425
  if(RxReset)
426 352 olof
    ReceivedPauseFrm <= 1'b0;
427 15 mohor
  else
428 272 tadejm
  if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
429 352 olof
    ReceivedPauseFrm <= 1'b0;
430 272 tadejm
  else
431 15 mohor
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
432 352 olof
    ReceivedPauseFrm <= 1'b1;
433 15 mohor
end
434
 
435
 
436
endmodule

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