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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 140

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
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////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
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////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
45
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
46
// changed from bit position 10 to 9.
47
//
48 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
49
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
50
//
51 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
52
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
53
// or not.
54
//
55 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
56
// Reset values are passed to registers through parameters
57
//
58 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
59
// Define missmatch fixed.
60
//
61 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
62
// Registered trimmed. Unused registers removed.
63
//
64 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
65
// File format fixed a bit.
66
//
67 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
68
// Modified for Address Checking,
69
// addition of eth_addrcheck.v
70
//
71
// Revision 1.8  2002/02/12 17:01:19  mohor
72
// HASH0 and HASH1 registers added. 
73
 
74 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
75
// Link in the header changed.
76
//
77 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
78
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
79
// instead of the number of RX descriptors).
80
//
81 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
82
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
83
//
84 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
85
// eth_timescale.v changed to timescale.v This is done because of the
86
// simulation of the few cores in a one joined project.
87
//
88 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
89
// Status signals changed, Adress decoding changed, interrupt controller
90
// added.
91
//
92 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
93
// Defines changed (All precede with ETH_). Small changes because some
94
// tools generate warnings when two operands are together. Synchronization
95
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
96
// demands).
97
//
98 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
99
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
100
// Include files fixed to contain no path.
101
// File names and module names changed ta have a eth_ prologue in the name.
102
// File eth_timescale.v is used to define timescale
103
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
104
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
105
// and Mdo_OE. The bidirectional signal must be created on the top level. This
106
// is done due to the ASIC tools.
107
//
108 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
109
// Unconnected signals are now connected.
110
//
111
// Revision 1.1  2001/07/30 21:23:42  mohor
112
// Directory structure changed. Files checked and joind together.
113
//
114
//
115
//
116
//
117
//
118
//
119
 
120
`include "eth_defines.v"
121 22 mohor
`include "timescale.v"
122 15 mohor
 
123
 
124 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
125 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
126
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
127 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
128 74 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
129 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
130 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
131
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
132
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
133
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
134 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
135 56 mohor
                      r_HASH0, r_HASH1
136 15 mohor
                    );
137
 
138
parameter Tp = 1;
139
 
140
input [31:0] DataIn;
141 46 mohor
input [7:0] Address;
142 15 mohor
 
143
input Rw;
144
input Cs;
145
input Clk;
146
input Reset;
147
 
148
input WCtrlDataStart;
149
input RStatStart;
150
 
151
input UpdateMIIRX_DATAReg;
152
input [15:0] Prsd;
153
 
154
output [31:0] DataOut;
155
reg    [31:0] DataOut;
156
 
157
output r_RecSmall;
158
output r_Pad;
159
output r_HugEn;
160
output r_CrcEn;
161
output r_DlyCrcEn;
162
output r_Rst;
163
output r_FullD;
164
output r_ExDfrEn;
165
output r_NoBckof;
166
output r_LoopBck;
167
output r_IFG;
168
output r_Pro;
169
output r_Iam;
170
output r_Bro;
171
output r_NoPre;
172
output r_TxEn;
173
output r_RxEn;
174 52 billditt
output [31:0] r_HASH0;
175
output [31:0] r_HASH1;
176 15 mohor
 
177 21 mohor
input TxB_IRQ;
178
input TxE_IRQ;
179
input RxB_IRQ;
180 74 mohor
input RxE_IRQ;
181 21 mohor
input Busy_IRQ;
182 74 mohor
input TxC_IRQ;
183
input RxC_IRQ;
184 15 mohor
 
185
output [6:0] r_IPGT;
186
 
187
output [6:0] r_IPGR1;
188
 
189
output [6:0] r_IPGR2;
190
 
191
output [15:0] r_MinFL;
192
output [15:0] r_MaxFL;
193
 
194
output [3:0] r_MaxRet;
195
output [5:0] r_CollValid;
196
 
197
output r_TxFlow;
198
output r_RxFlow;
199
output r_PassAll;
200
 
201
output r_MiiMRst;
202
output r_MiiNoPre;
203
output [7:0] r_ClkDiv;
204
 
205
output r_WCtrlData;
206
output r_RStat;
207
output r_ScanStat;
208
 
209
output [4:0] r_RGAD;
210
output [4:0] r_FIAD;
211
 
212 21 mohor
output [15:0]r_CtrlData;
213 15 mohor
 
214
 
215
input NValid_stat;
216
input Busy_stat;
217
input LinkFail;
218
 
219 21 mohor
output [47:0]r_MAC;
220 34 mohor
output [7:0] r_TxBDNum;
221
output       TX_BD_NUM_Wr;
222 21 mohor
output       int_o;
223 15 mohor
 
224 21 mohor
reg          irq_txb;
225
reg          irq_txe;
226
reg          irq_rxb;
227 74 mohor
reg          irq_rxe;
228 21 mohor
reg          irq_busy;
229 74 mohor
reg          irq_txc;
230
reg          irq_rxc;
231 15 mohor
 
232
wire Write = Cs &  Rw;
233
wire Read  = Cs & ~Rw;
234
 
235 21 mohor
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
236
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
237
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
238
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
239
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
240
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
241
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
242
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
243
 
244
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
245
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
246
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
247
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
248
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
249
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
250
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
251
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
252 52 billditt
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR   )  & Write;
253
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR   )  & Write;
254 34 mohor
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
255 15 mohor
 
256
 
257
 
258
wire [31:0] MODEROut;
259
wire [31:0] INT_SOURCEOut;
260
wire [31:0] INT_MASKOut;
261
wire [31:0] IPGTOut;
262
wire [31:0] IPGR1Out;
263
wire [31:0] IPGR2Out;
264
wire [31:0] PACKETLENOut;
265
wire [31:0] COLLCONFOut;
266
wire [31:0] CTRLMODEROut;
267
wire [31:0] MIIMODEROut;
268
wire [31:0] MIICOMMANDOut;
269
wire [31:0] MIIADDRESSOut;
270
wire [31:0] MIITX_DATAOut;
271
wire [31:0] MIIRX_DATAOut;
272
wire [31:0] MIISTATUSOut;
273
wire [31:0] MAC_ADDR0Out;
274
wire [31:0] MAC_ADDR1Out;
275 34 mohor
wire [31:0] TX_BD_NUMOut;
276 52 billditt
wire [31:0] HASH0Out;
277
wire [31:0] HASH1Out;
278 15 mohor
 
279 46 mohor
 
280 139 mohor
// MODER Register
281
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF)        MODER
282
  (
283
   .DataIn    (DataIn[`ETH_MODER_WIDTH-1:0]),
284
   .DataOut   (MODEROut[`ETH_MODER_WIDTH-1:0]),
285
   .Write     (MODER_Wr),
286
   .Clk       (Clk),
287
   .Reset     (Reset),
288
   .SyncReset (0)
289
  );
290
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
291 15 mohor
 
292 139 mohor
// INT_MASK Register
293
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF)  INT_MASK
294
  (
295
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
296
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
297
   .Write     (INT_MASK_Wr),
298
   .Clk       (Clk),
299
   .Reset     (Reset),
300
   .SyncReset (0)
301
  );
302
assign INT_MASKOut[31:ETH_INT_MASK_WIDTH] = 0;
303 52 billditt
 
304 139 mohor
// IPGT Register
305
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF)          IPGT
306
  (
307
   .DataIn    (DataIn[`ETH_IPGT_WIDTH-1:0]),
308
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
309
   .Write     (IPGT_Wr),
310
   .Clk       (Clk),
311
   .Reset     (Reset),
312
   .SyncReset (0)
313
  );
314
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
315 52 billditt
 
316 139 mohor
// IPGR1 Register
317
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF)        IPGR1
318
  (
319
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH-1:0]),
320
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
321
   .Write     (IPGR1_Wr),
322
   .Clk       (Clk),
323
   .Reset     (Reset),
324
   .SyncReset (0)
325
  );
326
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
327 15 mohor
 
328 139 mohor
// IPGR2 Register
329
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF)        IPGR2
330
  (
331
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH-1:0]),
332
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
333
   .Write     (IPGR2_Wr),
334
   .Clk       (Clk),
335
   .Reset     (Reset),
336
   .SyncReset (0)
337
  );
338
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
339 15 mohor
 
340 139 mohor
// PACKETLEN Register
341
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
342
  (
343
   .DataIn    (DataIn),
344
   .DataOut   (PACKETLENOut),
345
   .Write     (PACKETLEN_Wr),
346
   .Clk       (Clk),
347
   .Reset     (Reset),
348
   .SyncReset (0)
349
  );
350 15 mohor
 
351 139 mohor
// COLLCONF Register
352
eth_register #(6, `ETH_COLLCONF0_DEF)                   COLLCONF0
353
  (
354
   .DataIn    (DataIn[5:0]),
355
   .DataOut   (COLLCONFOut[5:0]),
356
   .Write     (COLLCONF_Wr),
357
   .Clk       (Clk),
358
   .Reset     (Reset),
359
   .SyncReset (0)
360
  );
361 68 mohor
assign COLLCONFOut[15:6] = 0;
362 139 mohor
 
363
eth_register #(4, `ETH_COLLCONF1_DEF)                   COLLCONF1
364
  (
365
   .DataIn    (DataIn[19:16]),
366
   .DataOut   (COLLCONFOut[19:16]),
367
   .Write     (COLLCONF_Wr),
368
   .Clk       (Clk),
369
   .Reset     (Reset),
370
   .SyncReset (0)
371
  );
372 68 mohor
assign COLLCONFOut[31:20] = 0;
373 15 mohor
 
374 139 mohor
// TX_BD_NUM Register
375
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
376
  (
377
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
378
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
379
   .Write     (TX_BD_NUM_Wr),
380
   .Clk       (Clk),
381
   .Reset     (Reset),
382
   .SyncReset (0)
383
  );
384
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
385 15 mohor
 
386 139 mohor
// CTRLMODER Register
387
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF)  CTRLMODER2
388
  (
389
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
390
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
391
   .Write     (CTRLMODER_Wr),
392
   .Clk       (Clk),
393
   .Reset     (Reset),
394
   .SyncReset (0)
395
  );
396
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
397 15 mohor
 
398 139 mohor
// MIIMODER Register
399
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF)    MIIMODER
400
  (
401
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
402
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
403
   .Write     (MIIMODER_Wr),
404
   .Clk       (Clk),
405
   .Reset     (Reset),
406
   .SyncReset (0)
407
  );
408
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
409 68 mohor
 
410 139 mohor
// MIICOMMAND Register
411
eth_register #(1, 0)                                      MIICOMMAND0
412
  (
413
   .DataIn    (DataIn[0]),
414
   .DataOut   (MIICOMMANDOut[0]),
415
   .Write     (MIICOMMAND_Wr),
416
   .Clk       (Clk),
417
   .Reset     (Reset),
418
   .SyncReset (0)
419
  );
420
 
421
eth_register #(1, 0)                                      MIICOMMAND1
422
  (
423
   .DataIn    (DataIn[1]),
424
   .DataOut   (MIICOMMANDOut[1]),
425
   .Write     (MIICOMMAND_Wr),
426
   .Clk       (Clk),
427
   .Reset     (Reset),
428
   .SyncReset (RStatStart)
429
  );
430
 
431
eth_register #(1, 0)                                      MIICOMMAND2
432
  (
433
   .DataIn    (DataIn[2]),
434
   .DataOut   (MIICOMMANDOut[2]),
435
   .Write     (MIICOMMAND_Wr),
436
   .Clk       (Clk),
437
   .Reset     (Reset),
438
   .SyncReset (WCtrlDataStart)
439
  );
440 15 mohor
assign MIICOMMANDOut[31:3] = 29'h0;
441
 
442 139 mohor
// MIIADDRESSRegister
443
eth_register #(5, `ETH_MIIADDRESS0_DEF)                   MIIADDRESS0
444
  (
445
   .DataIn    (DataIn[4:0]),
446
   .DataOut   (MIIADDRESSOut[4:0]),
447
   .Write     (MIIADDRESS_Wr),
448
   .Clk       (Clk),
449
   .Reset     (Reset),
450
   .SyncReset (0)
451
  );
452 68 mohor
assign MIIADDRESSOut[7:5] = 0;
453 139 mohor
 
454
eth_register #(5, `ETH_MIIADDRESS1_DEF)                   MIIADDRESS1
455
  (
456
   .DataIn    (DataIn[12:8]),
457
   .DataOut   (MIIADDRESSOut[12:8]),
458
   .Write     (MIIADDRESS_Wr),
459
   .Clk       (Clk),
460
   .Reset     (Reset),
461
   .SyncReset (0)
462
  );
463 68 mohor
assign MIIADDRESSOut[31:13] = 0;
464 15 mohor
 
465 139 mohor
// MIITX_DATA Register
466
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
467
  (
468
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
469 140 mohor
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
470 139 mohor
   .Write     (MIITX_DATA_Wr),
471
   .Clk       (Clk),
472
   .Reset     (Reset),
473
   .SyncReset (0)
474
  );
475
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
476 15 mohor
 
477 139 mohor
// MIIRX_DATA Register
478
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
479
  (
480
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
481
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
482
   .Write     (MIIRX_DATA_Wr),
483
   .Clk       (Clk),
484
   .Reset     (Reset),
485
   .SyncReset (0)
486
  );
487
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
488 15 mohor
 
489 139 mohor
// MAC_ADDR0 Register
490
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF)  MAC_ADDR0
491
  (
492
   .DataIn    (DataIn),
493
   .DataOut   (MAC_ADDR0Out),
494
   .Write     (MAC_ADDR0_Wr),
495
   .Clk       (Clk),
496
   .Reset     (Reset),
497
   .SyncReset (0)
498
  );
499 68 mohor
 
500 139 mohor
// MAC_ADDR1 Register
501
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF)  MAC_ADDR1
502
  (
503
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
504
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
505
   .Write     (MAC_ADDR1_Wr),
506
   .Clk       (Clk),
507
   .Reset     (Reset),
508
   .SyncReset (0)
509
  );
510
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
511 68 mohor
 
512 139 mohor
// RXHASH0 Register
513
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF)          RXHASH0
514
  (
515
   .DataIn    (DataIn),
516
   .DataOut   (HASH0Out),
517
   .Write     (HASH0_Wr),
518
   .Clk       (Clk),
519
   .Reset     (Reset),
520
   .SyncReset (0)
521
  );
522 68 mohor
 
523 139 mohor
// RXHASH1 Register
524
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF)          RXHASH1
525
  (
526
   .DataIn    (DataIn),
527
   .DataOut   (HASH1Out),
528
   .Write     (HASH1_Wr),
529
   .Clk       (Clk),
530
   .Reset     (Reset),
531
   .SyncReset (0)
532
  );
533 68 mohor
 
534 15 mohor
 
535 139 mohor
// Reading data from registers
536
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
537
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
538
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
539
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
540
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
541
          HASH0Out      or HASH1Out
542
         )
543 15 mohor
begin
544
  if(Read)  // read
545
    begin
546
      case(Address)
547 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
548
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
549
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
550
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
551
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
552
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
553
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
554
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
555
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
556
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
557
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
558
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
559
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
560
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
561
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
562
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
563
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
564 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
565 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
566
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
567 15 mohor
        default:             DataOut<=32'h0;
568
      endcase
569
    end
570
  else
571
    DataOut<=32'h0;
572
end
573
 
574
 
575
assign r_RecSmall         = MODEROut[16];
576
assign r_Pad              = MODEROut[15];
577
assign r_HugEn            = MODEROut[14];
578
assign r_CrcEn            = MODEROut[13];
579
assign r_DlyCrcEn         = MODEROut[12];
580
assign r_Rst              = MODEROut[11];
581
assign r_FullD            = MODEROut[10];
582
assign r_ExDfrEn          = MODEROut[9];
583
assign r_NoBckof          = MODEROut[8];
584
assign r_LoopBck          = MODEROut[7];
585
assign r_IFG              = MODEROut[6];
586
assign r_Pro              = MODEROut[5];
587
assign r_Iam              = MODEROut[4];
588
assign r_Bro              = MODEROut[3];
589
assign r_NoPre            = MODEROut[2];
590
assign r_TxEn             = MODEROut[1];
591
assign r_RxEn             = MODEROut[0];
592
 
593
assign r_IPGT[6:0]        = IPGTOut[6:0];
594
 
595
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
596
 
597
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
598
 
599
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
600
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
601
 
602 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
603
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
604 15 mohor
 
605
assign r_TxFlow           = CTRLMODEROut[2];
606
assign r_RxFlow           = CTRLMODEROut[1];
607
assign r_PassAll          = CTRLMODEROut[0];
608
 
609 139 mohor
assign r_MiiMRst          = MIIMODEROut[9];
610 15 mohor
assign r_MiiNoPre         = MIIMODEROut[8];
611
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
612
 
613
assign r_WCtrlData        = MIICOMMANDOut[2];
614
assign r_RStat            = MIICOMMANDOut[1];
615
assign r_ScanStat         = MIICOMMANDOut[0];
616
 
617
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
618
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
619
 
620
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
621
 
622 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
623
assign MIISTATUSOut[2]    = NValid_stat         ;
624
assign MIISTATUSOut[1]    = Busy_stat           ;
625
assign MIISTATUSOut[0]    = LinkFail            ;
626 15 mohor
 
627
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
628
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
629 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
630
assign r_HASH0[31:0]      = HASH0Out;
631 15 mohor
 
632 34 mohor
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
633 15 mohor
 
634
 
635 21 mohor
// Interrupt generation
636
always @ (posedge Clk or posedge Reset)
637
begin
638
  if(Reset)
639
    irq_txb <= 1'b0;
640
  else
641 102 mohor
  if(TxB_IRQ)
642 21 mohor
    irq_txb <= #Tp 1'b1;
643
  else
644
  if(INT_SOURCE_Wr & DataIn[0])
645
    irq_txb <= #Tp 1'b0;
646
end
647
 
648
always @ (posedge Clk or posedge Reset)
649
begin
650
  if(Reset)
651
    irq_txe <= 1'b0;
652
  else
653 102 mohor
  if(TxE_IRQ)
654 21 mohor
    irq_txe <= #Tp 1'b1;
655
  else
656
  if(INT_SOURCE_Wr & DataIn[1])
657
    irq_txe <= #Tp 1'b0;
658
end
659
 
660
always @ (posedge Clk or posedge Reset)
661
begin
662
  if(Reset)
663
    irq_rxb <= 1'b0;
664
  else
665 102 mohor
  if(RxB_IRQ)
666 21 mohor
    irq_rxb <= #Tp 1'b1;
667
  else
668
  if(INT_SOURCE_Wr & DataIn[2])
669
    irq_rxb <= #Tp 1'b0;
670
end
671
 
672
always @ (posedge Clk or posedge Reset)
673
begin
674
  if(Reset)
675 74 mohor
    irq_rxe <= 1'b0;
676 21 mohor
  else
677 102 mohor
  if(RxE_IRQ)
678 74 mohor
    irq_rxe <= #Tp 1'b1;
679 21 mohor
  else
680
  if(INT_SOURCE_Wr & DataIn[3])
681 74 mohor
    irq_rxe <= #Tp 1'b0;
682 21 mohor
end
683
 
684
always @ (posedge Clk or posedge Reset)
685
begin
686
  if(Reset)
687
    irq_busy <= 1'b0;
688
  else
689 102 mohor
  if(Busy_IRQ)
690 21 mohor
    irq_busy <= #Tp 1'b1;
691
  else
692
  if(INT_SOURCE_Wr & DataIn[4])
693
    irq_busy <= #Tp 1'b0;
694
end
695
 
696 74 mohor
always @ (posedge Clk or posedge Reset)
697
begin
698
  if(Reset)
699
    irq_txc <= 1'b0;
700
  else
701 102 mohor
  if(TxC_IRQ)
702 74 mohor
    irq_txc <= #Tp 1'b1;
703
  else
704
  if(INT_SOURCE_Wr & DataIn[5])
705
    irq_txc <= #Tp 1'b0;
706
end
707
 
708
always @ (posedge Clk or posedge Reset)
709
begin
710
  if(Reset)
711
    irq_rxc <= 1'b0;
712
  else
713 102 mohor
  if(RxC_IRQ)
714 74 mohor
    irq_rxc <= #Tp 1'b1;
715
  else
716
  if(INT_SOURCE_Wr & DataIn[6])
717
    irq_rxc <= #Tp 1'b0;
718
end
719
 
720 21 mohor
// Generating interrupt signal
721 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
722
               irq_txe  & INT_MASKOut[1] |
723
               irq_rxb  & INT_MASKOut[2] |
724
               irq_rxe  & INT_MASKOut[3] |
725
               irq_busy & INT_MASKOut[4] |
726
               irq_txc  & INT_MASKOut[5] |
727
               irq_rxc  & INT_MASKOut[6] ;
728 21 mohor
 
729
// For reading interrupt status
730 139 mohor
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
731 21 mohor
 
732
 
733
 
734 15 mohor
endmodule

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