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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 354

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.28  2004/04/26 15:26:23  igorm
45
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
46
//   previous update of the core.
47
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
48
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
49
//   register. (thanks to Mathias and Torbjorn)
50
// - Multicast reception was fixed. Thanks to Ulrich Gries
51
//
52 321 igorm
// Revision 1.27  2004/04/26 11:42:17  igorm
53
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
54
//
55 320 igorm
// Revision 1.26  2003/11/12 18:24:59  tadejm
56
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
57
//
58 304 tadejm
// Revision 1.25  2003/04/18 16:26:25  mohor
59
// RxBDAddress was updated also when value to r_TxBDNum was written with
60
// greater value than allowed.
61
//
62 283 mohor
// Revision 1.24  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66 261 mohor
// Revision 1.23  2002/11/19 18:13:49  mohor
67
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
68
//
69 253 mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
70
// r_Rst signal does not reset any module any more and is removed from the design.
71
//
72 244 mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
73
// Ethernet debug registers removed.
74
//
75 164 mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
76
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
77
// the control frames connected.
78
//
79 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
80
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
81
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
82
//
83 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
84
// Syntax error fixed.
85
//
86 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
87
// Syntax error fixed.
88
//
89 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
90
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
91
// changed from bit position 10 to 9.
92
//
93 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
94
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
95
//
96 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
97
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
98
// or not.
99
//
100 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
101
// Reset values are passed to registers through parameters
102
//
103 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
104
// Define missmatch fixed.
105
//
106 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
107
// Registered trimmed. Unused registers removed.
108
//
109 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
110
// File format fixed a bit.
111
//
112 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
113
// Modified for Address Checking,
114
// addition of eth_addrcheck.v
115
//
116
// Revision 1.8  2002/02/12 17:01:19  mohor
117
// HASH0 and HASH1 registers added. 
118
 
119 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
120
// Link in the header changed.
121
//
122 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
123
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
124
// instead of the number of RX descriptors).
125
//
126 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
127
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
128
//
129 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
130
// eth_timescale.v changed to timescale.v This is done because of the
131
// simulation of the few cores in a one joined project.
132
//
133 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
134
// Status signals changed, Adress decoding changed, interrupt controller
135
// added.
136
//
137 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
138
// Defines changed (All precede with ETH_). Small changes because some
139
// tools generate warnings when two operands are together. Synchronization
140
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
141
// demands).
142
//
143 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
144
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
145
// Include files fixed to contain no path.
146
// File names and module names changed ta have a eth_ prologue in the name.
147
// File eth_timescale.v is used to define timescale
148
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
149
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
150
// and Mdo_OE. The bidirectional signal must be created on the top level. This
151
// is done due to the ASIC tools.
152
//
153 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
154
// Unconnected signals are now connected.
155
//
156
// Revision 1.1  2001/07/30 21:23:42  mohor
157
// Directory structure changed. Files checked and joind together.
158
//
159
//
160
//
161
//
162
//
163
//
164
 
165
`include "eth_defines.v"
166 22 mohor
`include "timescale.v"
167 15 mohor
 
168
 
169 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
170 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
171 244 mohor
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
172 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
173 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
174 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
175 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
176 253 mohor
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
177 15 mohor
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
178
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
179 321 igorm
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
180 354 olof
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
181 261 mohor
                      StartTxDone, TxClk, RxClk, SetPauseTimer
182 15 mohor
                    );
183
 
184
input [31:0] DataIn;
185 46 mohor
input [7:0] Address;
186 15 mohor
 
187
input Rw;
188 304 tadejm
input [3:0] Cs;
189 15 mohor
input Clk;
190
input Reset;
191
 
192
input WCtrlDataStart;
193
input RStatStart;
194
 
195
input UpdateMIIRX_DATAReg;
196
input [15:0] Prsd;
197
 
198
output [31:0] DataOut;
199
reg    [31:0] DataOut;
200
 
201
output r_RecSmall;
202
output r_Pad;
203
output r_HugEn;
204
output r_CrcEn;
205
output r_DlyCrcEn;
206
output r_FullD;
207
output r_ExDfrEn;
208
output r_NoBckof;
209
output r_LoopBck;
210
output r_IFG;
211
output r_Pro;
212
output r_Iam;
213
output r_Bro;
214
output r_NoPre;
215
output r_TxEn;
216
output r_RxEn;
217 52 billditt
output [31:0] r_HASH0;
218
output [31:0] r_HASH1;
219 15 mohor
 
220 21 mohor
input TxB_IRQ;
221
input TxE_IRQ;
222
input RxB_IRQ;
223 74 mohor
input RxE_IRQ;
224 21 mohor
input Busy_IRQ;
225 15 mohor
 
226
output [6:0] r_IPGT;
227
 
228
output [6:0] r_IPGR1;
229
 
230
output [6:0] r_IPGR2;
231
 
232
output [15:0] r_MinFL;
233
output [15:0] r_MaxFL;
234
 
235
output [3:0] r_MaxRet;
236
output [5:0] r_CollValid;
237
 
238
output r_TxFlow;
239
output r_RxFlow;
240
output r_PassAll;
241
 
242
output r_MiiNoPre;
243
output [7:0] r_ClkDiv;
244
 
245
output r_WCtrlData;
246
output r_RStat;
247
output r_ScanStat;
248
 
249
output [4:0] r_RGAD;
250
output [4:0] r_FIAD;
251
 
252 21 mohor
output [15:0]r_CtrlData;
253 15 mohor
 
254
 
255
input NValid_stat;
256
input Busy_stat;
257
input LinkFail;
258
 
259 21 mohor
output [47:0]r_MAC;
260 34 mohor
output [7:0] r_TxBDNum;
261 21 mohor
output       int_o;
262 147 mohor
output [15:0]r_TxPauseTV;
263
output       r_TxPauseRq;
264
input        RstTxPauseRq;
265
input        TxCtrlEndFrm;
266
input        StartTxDone;
267
input        TxClk;
268
input        RxClk;
269 261 mohor
input        SetPauseTimer;
270 15 mohor
 
271 21 mohor
reg          irq_txb;
272
reg          irq_txe;
273
reg          irq_rxb;
274 74 mohor
reg          irq_rxe;
275 21 mohor
reg          irq_busy;
276 74 mohor
reg          irq_txc;
277
reg          irq_rxc;
278 15 mohor
 
279 147 mohor
reg SetTxCIrq_txclk;
280
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
281
reg SetTxCIrq;
282
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
283
 
284
reg SetRxCIrq_rxclk;
285
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
286
reg SetRxCIrq;
287 261 mohor
reg ResetRxCIrq_sync1;
288
reg ResetRxCIrq_sync2;
289
reg ResetRxCIrq_sync3;
290 147 mohor
 
291 304 tadejm
wire [3:0] Write =   Cs  & {4{Rw}};
292
wire       Read  = (|Cs) &   ~Rw;
293 15 mohor
 
294 320 igorm
wire MODER_Sel      = (Address == `ETH_MODER_ADR       );
295
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR  );
296
wire INT_MASK_Sel   = (Address == `ETH_INT_MASK_ADR    );
297
wire IPGT_Sel       = (Address == `ETH_IPGT_ADR        );
298
wire IPGR1_Sel      = (Address == `ETH_IPGR1_ADR       );
299
wire IPGR2_Sel      = (Address == `ETH_IPGR2_ADR       );
300
wire PACKETLEN_Sel  = (Address == `ETH_PACKETLEN_ADR   );
301
wire COLLCONF_Sel   = (Address == `ETH_COLLCONF_ADR    );
302 21 mohor
 
303 320 igorm
wire CTRLMODER_Sel  = (Address == `ETH_CTRLMODER_ADR   );
304
wire MIIMODER_Sel   = (Address == `ETH_MIIMODER_ADR    );
305
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR  );
306
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR  );
307
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR  );
308
wire MAC_ADDR0_Sel  = (Address == `ETH_MAC_ADDR0_ADR   );
309
wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
310
wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
311
wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
312
wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
313
wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
314
wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
315 15 mohor
 
316
 
317 320 igorm
wire [2:0] MODER_Wr;
318
wire [0:0] INT_SOURCE_Wr;
319
wire [0:0] INT_MASK_Wr;
320
wire [0:0] IPGT_Wr;
321
wire [0:0] IPGR1_Wr;
322
wire [0:0] IPGR2_Wr;
323
wire [3:0] PACKETLEN_Wr;
324
wire [2:0] COLLCONF_Wr;
325
wire [0:0] CTRLMODER_Wr;
326
wire [1:0] MIIMODER_Wr;
327
wire [0:0] MIICOMMAND_Wr;
328
wire [1:0] MIIADDRESS_Wr;
329
wire [1:0] MIITX_DATA_Wr;
330
wire       MIIRX_DATA_Wr;
331
wire [3:0] MAC_ADDR0_Wr;
332
wire [1:0] MAC_ADDR1_Wr;
333
wire [3:0] HASH0_Wr;
334
wire [3:0] HASH1_Wr;
335
wire [2:0] TXCTRL_Wr;
336 321 igorm
wire [0:0] TX_BD_NUM_Wr;
337 15 mohor
 
338 320 igorm
assign MODER_Wr[0]       = Write[0]  & MODER_Sel;
339
assign MODER_Wr[1]       = Write[1]  & MODER_Sel;
340
assign MODER_Wr[2]       = Write[2]  & MODER_Sel;
341
assign INT_SOURCE_Wr[0]  = Write[0]  & INT_SOURCE_Sel;
342
assign INT_MASK_Wr[0]    = Write[0]  & INT_MASK_Sel;
343
assign IPGT_Wr[0]        = Write[0]  & IPGT_Sel;
344
assign IPGR1_Wr[0]       = Write[0]  & IPGR1_Sel;
345
assign IPGR2_Wr[0]       = Write[0]  & IPGR2_Sel;
346
assign PACKETLEN_Wr[0]   = Write[0]  & PACKETLEN_Sel;
347
assign PACKETLEN_Wr[1]   = Write[1]  & PACKETLEN_Sel;
348
assign PACKETLEN_Wr[2]   = Write[2]  & PACKETLEN_Sel;
349
assign PACKETLEN_Wr[3]   = Write[3]  & PACKETLEN_Sel;
350
assign COLLCONF_Wr[0]    = Write[0]  & COLLCONF_Sel;
351
assign COLLCONF_Wr[1]    = 1'b0;  // Not used
352
assign COLLCONF_Wr[2]    = Write[2]  & COLLCONF_Sel;
353
 
354
assign CTRLMODER_Wr[0]   = Write[0]  & CTRLMODER_Sel;
355
assign MIIMODER_Wr[0]    = Write[0]  & MIIMODER_Sel;
356
assign MIIMODER_Wr[1]    = Write[1]  & MIIMODER_Sel;
357
assign MIICOMMAND_Wr[0]  = Write[0]  & MIICOMMAND_Sel;
358
assign MIIADDRESS_Wr[0]  = Write[0]  & MIIADDRESS_Sel;
359
assign MIIADDRESS_Wr[1]  = Write[1]  & MIIADDRESS_Sel;
360
assign MIITX_DATA_Wr[0]  = Write[0]  & MIITX_DATA_Sel;
361
assign MIITX_DATA_Wr[1]  = Write[1]  & MIITX_DATA_Sel;
362
assign MIIRX_DATA_Wr     = UpdateMIIRX_DATAReg;
363
assign MAC_ADDR0_Wr[0]   = Write[0]  & MAC_ADDR0_Sel;
364
assign MAC_ADDR0_Wr[1]   = Write[1]  & MAC_ADDR0_Sel;
365
assign MAC_ADDR0_Wr[2]   = Write[2]  & MAC_ADDR0_Sel;
366
assign MAC_ADDR0_Wr[3]   = Write[3]  & MAC_ADDR0_Sel;
367
assign MAC_ADDR1_Wr[0]   = Write[0]  & MAC_ADDR1_Sel;
368
assign MAC_ADDR1_Wr[1]   = Write[1]  & MAC_ADDR1_Sel;
369
assign HASH0_Wr[0]       = Write[0]  & HASH0_Sel;
370
assign HASH0_Wr[1]       = Write[1]  & HASH0_Sel;
371
assign HASH0_Wr[2]       = Write[2]  & HASH0_Sel;
372
assign HASH0_Wr[3]       = Write[3]  & HASH0_Sel;
373
assign HASH1_Wr[0]       = Write[0]  & HASH1_Sel;
374
assign HASH1_Wr[1]       = Write[1]  & HASH1_Sel;
375
assign HASH1_Wr[2]       = Write[2]  & HASH1_Sel;
376
assign HASH1_Wr[3]       = Write[3]  & HASH1_Sel;
377
assign TXCTRL_Wr[0]      = Write[0]  & TXCTRL_Sel;
378
assign TXCTRL_Wr[1]      = Write[1]  & TXCTRL_Sel;
379
assign TXCTRL_Wr[2]      = Write[2]  & TXCTRL_Sel;
380 321 igorm
assign TX_BD_NUM_Wr[0]   = Write[0]  & TX_BD_NUM_Sel & (DataIn<='h80);
381 320 igorm
 
382
 
383
 
384 15 mohor
wire [31:0] MODEROut;
385
wire [31:0] INT_SOURCEOut;
386
wire [31:0] INT_MASKOut;
387
wire [31:0] IPGTOut;
388
wire [31:0] IPGR1Out;
389
wire [31:0] IPGR2Out;
390
wire [31:0] PACKETLENOut;
391
wire [31:0] COLLCONFOut;
392
wire [31:0] CTRLMODEROut;
393
wire [31:0] MIIMODEROut;
394
wire [31:0] MIICOMMANDOut;
395
wire [31:0] MIIADDRESSOut;
396
wire [31:0] MIITX_DATAOut;
397
wire [31:0] MIIRX_DATAOut;
398
wire [31:0] MIISTATUSOut;
399
wire [31:0] MAC_ADDR0Out;
400
wire [31:0] MAC_ADDR1Out;
401 34 mohor
wire [31:0] TX_BD_NUMOut;
402 52 billditt
wire [31:0] HASH0Out;
403
wire [31:0] HASH1Out;
404 147 mohor
wire [31:0] TXCTRLOut;
405 15 mohor
 
406 139 mohor
// MODER Register
407 304 tadejm
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
408 139 mohor
  (
409 304 tadejm
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
410
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
411 320 igorm
   .Write     (MODER_Wr[0]),
412 139 mohor
   .Clk       (Clk),
413
   .Reset     (Reset),
414 141 mohor
   .SyncReset (1'b0)
415 139 mohor
  );
416 304 tadejm
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1)        MODER_1
417
  (
418
   .DataIn    (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
419
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
420 320 igorm
   .Write     (MODER_Wr[1]),
421 304 tadejm
   .Clk       (Clk),
422
   .Reset     (Reset),
423
   .SyncReset (1'b0)
424
  );
425
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2)        MODER_2
426
  (
427
   .DataIn    (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
428
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
429 320 igorm
   .Write     (MODER_Wr[2]),
430 304 tadejm
   .Clk       (Clk),
431
   .Reset     (Reset),
432
   .SyncReset (1'b0)
433
  );
434
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
435 15 mohor
 
436 139 mohor
// INT_MASK Register
437 304 tadejm
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0)  INT_MASK_0
438 139 mohor
  (
439 304 tadejm
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
440
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
441 320 igorm
   .Write     (INT_MASK_Wr[0]),
442 139 mohor
   .Clk       (Clk),
443
   .Reset     (Reset),
444 141 mohor
   .SyncReset (1'b0)
445 139 mohor
  );
446 304 tadejm
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
447 52 billditt
 
448 139 mohor
// IPGT Register
449 304 tadejm
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0)          IPGT_0
450 139 mohor
  (
451 304 tadejm
   .DataIn    (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
452
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
453 320 igorm
   .Write     (IPGT_Wr[0]),
454 139 mohor
   .Clk       (Clk),
455
   .Reset     (Reset),
456 141 mohor
   .SyncReset (1'b0)
457 139 mohor
  );
458 304 tadejm
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
459 52 billditt
 
460 139 mohor
// IPGR1 Register
461 304 tadejm
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0)        IPGR1_0
462 139 mohor
  (
463 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
464
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
465 320 igorm
   .Write     (IPGR1_Wr[0]),
466 139 mohor
   .Clk       (Clk),
467
   .Reset     (Reset),
468 141 mohor
   .SyncReset (1'b0)
469 139 mohor
  );
470 304 tadejm
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
471 15 mohor
 
472 139 mohor
// IPGR2 Register
473 304 tadejm
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0)        IPGR2_0
474 139 mohor
  (
475 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
476
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
477 320 igorm
   .Write     (IPGR2_Wr[0]),
478 139 mohor
   .Clk       (Clk),
479
   .Reset     (Reset),
480 141 mohor
   .SyncReset (1'b0)
481 139 mohor
  );
482 304 tadejm
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
483 15 mohor
 
484 139 mohor
// PACKETLEN Register
485 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
486 139 mohor
  (
487 304 tadejm
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
488
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
489 320 igorm
   .Write     (PACKETLEN_Wr[0]),
490 139 mohor
   .Clk       (Clk),
491
   .Reset     (Reset),
492 141 mohor
   .SyncReset (1'b0)
493 139 mohor
  );
494 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
495
  (
496
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
497
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
498 320 igorm
   .Write     (PACKETLEN_Wr[1]),
499 304 tadejm
   .Clk       (Clk),
500
   .Reset     (Reset),
501
   .SyncReset (1'b0)
502
  );
503
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
504
  (
505
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
506
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
507 320 igorm
   .Write     (PACKETLEN_Wr[2]),
508 304 tadejm
   .Clk       (Clk),
509
   .Reset     (Reset),
510
   .SyncReset (1'b0)
511
  );
512
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
513
  (
514
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
515
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
516 320 igorm
   .Write     (PACKETLEN_Wr[3]),
517 304 tadejm
   .Clk       (Clk),
518
   .Reset     (Reset),
519
   .SyncReset (1'b0)
520
  );
521 15 mohor
 
522 139 mohor
// COLLCONF Register
523 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0)   COLLCONF_0
524 139 mohor
  (
525 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
526
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
527 320 igorm
   .Write     (COLLCONF_Wr[0]),
528 139 mohor
   .Clk       (Clk),
529
   .Reset     (Reset),
530 141 mohor
   .SyncReset (1'b0)
531 139 mohor
  );
532 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2)   COLLCONF_2
533 139 mohor
  (
534 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
535
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
536 320 igorm
   .Write     (COLLCONF_Wr[2]),
537 139 mohor
   .Clk       (Clk),
538
   .Reset     (Reset),
539 141 mohor
   .SyncReset (1'b0)
540 139 mohor
  );
541 304 tadejm
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
542
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
543 15 mohor
 
544 139 mohor
// TX_BD_NUM Register
545 304 tadejm
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
546 139 mohor
  (
547 304 tadejm
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
548
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
549 321 igorm
   .Write     (TX_BD_NUM_Wr[0]),
550 139 mohor
   .Clk       (Clk),
551
   .Reset     (Reset),
552 141 mohor
   .SyncReset (1'b0)
553 139 mohor
  );
554 304 tadejm
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
555 15 mohor
 
556 139 mohor
// CTRLMODER Register
557 304 tadejm
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0)  CTRLMODER_0
558 139 mohor
  (
559 304 tadejm
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
560
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
561 320 igorm
   .Write     (CTRLMODER_Wr[0]),
562 139 mohor
   .Clk       (Clk),
563
   .Reset     (Reset),
564 141 mohor
   .SyncReset (1'b0)
565 139 mohor
  );
566 304 tadejm
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
567 15 mohor
 
568 139 mohor
// MIIMODER Register
569 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0)    MIIMODER_0
570 139 mohor
  (
571 304 tadejm
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
572
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
573 320 igorm
   .Write     (MIIMODER_Wr[0]),
574 139 mohor
   .Clk       (Clk),
575
   .Reset     (Reset),
576 141 mohor
   .SyncReset (1'b0)
577 139 mohor
  );
578 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1)    MIIMODER_1
579
  (
580
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
581
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
582 320 igorm
   .Write     (MIIMODER_Wr[1]),
583 304 tadejm
   .Clk       (Clk),
584
   .Reset     (Reset),
585
   .SyncReset (1'b0)
586
  );
587
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
588 68 mohor
 
589 139 mohor
// MIICOMMAND Register
590
eth_register #(1, 0)                                      MIICOMMAND0
591
  (
592
   .DataIn    (DataIn[0]),
593
   .DataOut   (MIICOMMANDOut[0]),
594 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
595 139 mohor
   .Clk       (Clk),
596
   .Reset     (Reset),
597 141 mohor
   .SyncReset (1'b0)
598 139 mohor
  );
599
eth_register #(1, 0)                                      MIICOMMAND1
600
  (
601
   .DataIn    (DataIn[1]),
602
   .DataOut   (MIICOMMANDOut[1]),
603 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
604 139 mohor
   .Clk       (Clk),
605
   .Reset     (Reset),
606
   .SyncReset (RStatStart)
607
  );
608
eth_register #(1, 0)                                      MIICOMMAND2
609
  (
610
   .DataIn    (DataIn[2]),
611
   .DataOut   (MIICOMMANDOut[2]),
612 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
613 139 mohor
   .Clk       (Clk),
614
   .Reset     (Reset),
615
   .SyncReset (WCtrlDataStart)
616
  );
617 304 tadejm
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
618 15 mohor
 
619 139 mohor
// MIIADDRESSRegister
620 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
621 139 mohor
  (
622 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
623
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
624 320 igorm
   .Write     (MIIADDRESS_Wr[0]),
625 139 mohor
   .Clk       (Clk),
626
   .Reset     (Reset),
627 141 mohor
   .SyncReset (1'b0)
628 139 mohor
  );
629 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
630 139 mohor
  (
631 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
632
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
633 320 igorm
   .Write     (MIIADDRESS_Wr[1]),
634 139 mohor
   .Clk       (Clk),
635
   .Reset     (Reset),
636 141 mohor
   .SyncReset (1'b0)
637 139 mohor
  );
638 304 tadejm
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
639
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
640 15 mohor
 
641 139 mohor
// MIITX_DATA Register
642 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
643 139 mohor
  (
644 304 tadejm
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
645
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
646 320 igorm
   .Write     (MIITX_DATA_Wr[0]),
647 139 mohor
   .Clk       (Clk),
648
   .Reset     (Reset),
649 141 mohor
   .SyncReset (1'b0)
650 139 mohor
  );
651 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
652
  (
653
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
654
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
655 320 igorm
   .Write     (MIITX_DATA_Wr[1]),
656 304 tadejm
   .Clk       (Clk),
657
   .Reset     (Reset),
658
   .SyncReset (1'b0)
659
  );
660
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
661 15 mohor
 
662 139 mohor
// MIIRX_DATA Register
663
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
664
  (
665
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
666
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
667 304 tadejm
   .Write     (MIIRX_DATA_Wr), // not written from WB
668 139 mohor
   .Clk       (Clk),
669
   .Reset     (Reset),
670 141 mohor
   .SyncReset (1'b0)
671 139 mohor
  );
672
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
673 15 mohor
 
674 139 mohor
// MAC_ADDR0 Register
675 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  MAC_ADDR0_0
676 139 mohor
  (
677 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
678
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
679 320 igorm
   .Write     (MAC_ADDR0_Wr[0]),
680 139 mohor
   .Clk       (Clk),
681
   .Reset     (Reset),
682 141 mohor
   .SyncReset (1'b0)
683 139 mohor
  );
684 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  MAC_ADDR0_1
685
  (
686
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
687
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
688 320 igorm
   .Write     (MAC_ADDR0_Wr[1]),
689 304 tadejm
   .Clk       (Clk),
690
   .Reset     (Reset),
691
   .SyncReset (1'b0)
692
  );
693
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  MAC_ADDR0_2
694
  (
695
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
696
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
697 320 igorm
   .Write     (MAC_ADDR0_Wr[2]),
698 304 tadejm
   .Clk       (Clk),
699
   .Reset     (Reset),
700
   .SyncReset (1'b0)
701
  );
702
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  MAC_ADDR0_3
703
  (
704
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
705
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
706 320 igorm
   .Write     (MAC_ADDR0_Wr[3]),
707 304 tadejm
   .Clk       (Clk),
708
   .Reset     (Reset),
709
   .SyncReset (1'b0)
710
  );
711 68 mohor
 
712 139 mohor
// MAC_ADDR1 Register
713 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  MAC_ADDR1_0
714 139 mohor
  (
715 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
716
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
717 320 igorm
   .Write     (MAC_ADDR1_Wr[0]),
718 139 mohor
   .Clk       (Clk),
719
   .Reset     (Reset),
720 141 mohor
   .SyncReset (1'b0)
721 139 mohor
  );
722 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  MAC_ADDR1_1
723
  (
724
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
725
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
726 320 igorm
   .Write     (MAC_ADDR1_Wr[1]),
727 304 tadejm
   .Clk       (Clk),
728
   .Reset     (Reset),
729
   .SyncReset (1'b0)
730
  );
731
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
732 68 mohor
 
733 139 mohor
// RXHASH0 Register
734 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0)          RXHASH0_0
735 139 mohor
  (
736 304 tadejm
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
737
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
738 320 igorm
   .Write     (HASH0_Wr[0]),
739 139 mohor
   .Clk       (Clk),
740
   .Reset     (Reset),
741 141 mohor
   .SyncReset (1'b0)
742 139 mohor
  );
743 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1)          RXHASH0_1
744
  (
745
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
746
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
747 320 igorm
   .Write     (HASH0_Wr[1]),
748 304 tadejm
   .Clk       (Clk),
749
   .Reset     (Reset),
750
   .SyncReset (1'b0)
751
  );
752
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2)          RXHASH0_2
753
  (
754
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
755
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
756 320 igorm
   .Write     (HASH0_Wr[2]),
757 304 tadejm
   .Clk       (Clk),
758
   .Reset     (Reset),
759
   .SyncReset (1'b0)
760
  );
761
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3)          RXHASH0_3
762
  (
763
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
764
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
765 320 igorm
   .Write     (HASH0_Wr[3]),
766 304 tadejm
   .Clk       (Clk),
767
   .Reset     (Reset),
768
   .SyncReset (1'b0)
769
  );
770 68 mohor
 
771 139 mohor
// RXHASH1 Register
772 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0)          RXHASH1_0
773 139 mohor
  (
774 304 tadejm
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
775
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
776 320 igorm
   .Write     (HASH1_Wr[0]),
777 139 mohor
   .Clk       (Clk),
778
   .Reset     (Reset),
779 141 mohor
   .SyncReset (1'b0)
780 139 mohor
  );
781 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1)          RXHASH1_1
782
  (
783
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
784
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
785 320 igorm
   .Write     (HASH1_Wr[1]),
786 304 tadejm
   .Clk       (Clk),
787
   .Reset     (Reset),
788
   .SyncReset (1'b0)
789
  );
790
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2
791
  (
792
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
793
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
794 320 igorm
   .Write     (HASH1_Wr[2]),
795 304 tadejm
   .Clk       (Clk),
796
   .Reset     (Reset),
797
   .SyncReset (1'b0)
798
  );
799
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3
800
  (
801
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
802
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
803 320 igorm
   .Write     (HASH1_Wr[3]),
804 304 tadejm
   .Clk       (Clk),
805
   .Reset     (Reset),
806
   .SyncReset (1'b0)
807
  );
808 68 mohor
 
809 147 mohor
// TXCTRL Register
810 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0
811 147 mohor
  (
812 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
813
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
814 320 igorm
   .Write     (TXCTRL_Wr[0]),
815 147 mohor
   .Clk       (Clk),
816
   .Reset     (Reset),
817
   .SyncReset (1'b0)
818
  );
819 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1
820 147 mohor
  (
821 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
822
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
823 320 igorm
   .Write     (TXCTRL_Wr[1]),
824 147 mohor
   .Clk       (Clk),
825
   .Reset     (Reset),
826 304 tadejm
   .SyncReset (1'b0)
827
  );
828
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset
829
  (
830
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
831
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
832 320 igorm
   .Write     (TXCTRL_Wr[2]),
833 304 tadejm
   .Clk       (Clk),
834
   .Reset     (Reset),
835 147 mohor
   .SyncReset (RstTxPauseRq)
836
  );
837 304 tadejm
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
838 147 mohor
 
839
 
840
 
841 139 mohor
// Reading data from registers
842
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
843
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
844
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
845
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
846
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
847 333 igorm
          HASH0Out      or HASH1Out       or TXCTRLOut
848 139 mohor
         )
849 15 mohor
begin
850
  if(Read)  // read
851
    begin
852
      case(Address)
853 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
854
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
855
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
856
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
857
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
858
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
859
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
860
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
861
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
862
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
863
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
864
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
865
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
866
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
867
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
868
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
869
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
870 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
871 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
872
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
873 147 mohor
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
874
 
875 15 mohor
        default:             DataOut<=32'h0;
876
      endcase
877
    end
878
  else
879
    DataOut<=32'h0;
880
end
881
 
882
 
883
assign r_RecSmall         = MODEROut[16];
884
assign r_Pad              = MODEROut[15];
885
assign r_HugEn            = MODEROut[14];
886
assign r_CrcEn            = MODEROut[13];
887
assign r_DlyCrcEn         = MODEROut[12];
888 244 mohor
// assign r_Rst           = MODEROut[11];   This signal is not used any more
889 15 mohor
assign r_FullD            = MODEROut[10];
890
assign r_ExDfrEn          = MODEROut[9];
891
assign r_NoBckof          = MODEROut[8];
892
assign r_LoopBck          = MODEROut[7];
893
assign r_IFG              = MODEROut[6];
894
assign r_Pro              = MODEROut[5];
895
assign r_Iam              = MODEROut[4];
896
assign r_Bro              = MODEROut[3];
897
assign r_NoPre            = MODEROut[2];
898 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
899
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
900 15 mohor
 
901
assign r_IPGT[6:0]        = IPGTOut[6:0];
902
 
903
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
904
 
905
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
906
 
907
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
908
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
909
 
910 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
911
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
912 15 mohor
 
913
assign r_TxFlow           = CTRLMODEROut[2];
914
assign r_RxFlow           = CTRLMODEROut[1];
915
assign r_PassAll          = CTRLMODEROut[0];
916
 
917
assign r_MiiNoPre         = MIIMODEROut[8];
918
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
919
 
920
assign r_WCtrlData        = MIICOMMANDOut[2];
921
assign r_RStat            = MIICOMMANDOut[1];
922
assign r_ScanStat         = MIICOMMANDOut[0];
923
 
924
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
925
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
926
 
927
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
928
 
929 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
930
assign MIISTATUSOut[2]    = NValid_stat         ;
931
assign MIISTATUSOut[1]    = Busy_stat           ;
932
assign MIISTATUSOut[0]    = LinkFail            ;
933 15 mohor
 
934
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
935
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
936 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
937
assign r_HASH0[31:0]      = HASH0Out;
938 15 mohor
 
939 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
940 15 mohor
 
941 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
942
assign r_TxPauseRq        = TXCTRLOut[16];
943 15 mohor
 
944 147 mohor
 
945
// Synchronizing TxC Interrupt
946
always @ (posedge TxClk or posedge Reset)
947
begin
948
  if(Reset)
949 352 olof
    SetTxCIrq_txclk <= 1'b0;
950 147 mohor
  else
951
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
952 352 olof
    SetTxCIrq_txclk <= 1'b1;
953 147 mohor
  else
954
  if(ResetTxCIrq_sync2)
955 352 olof
    SetTxCIrq_txclk <= 1'b0;
956 147 mohor
end
957
 
958
 
959
always @ (posedge Clk or posedge Reset)
960
begin
961
  if(Reset)
962 352 olof
    SetTxCIrq_sync1 <= 1'b0;
963 147 mohor
  else
964 352 olof
    SetTxCIrq_sync1 <= SetTxCIrq_txclk;
965 147 mohor
end
966
 
967
always @ (posedge Clk or posedge Reset)
968
begin
969
  if(Reset)
970 352 olof
    SetTxCIrq_sync2 <= 1'b0;
971 147 mohor
  else
972 352 olof
    SetTxCIrq_sync2 <= SetTxCIrq_sync1;
973 147 mohor
end
974
 
975
always @ (posedge Clk or posedge Reset)
976
begin
977
  if(Reset)
978 352 olof
    SetTxCIrq_sync3 <= 1'b0;
979 147 mohor
  else
980 352 olof
    SetTxCIrq_sync3 <= SetTxCIrq_sync2;
981 147 mohor
end
982
 
983
always @ (posedge Clk or posedge Reset)
984
begin
985
  if(Reset)
986 352 olof
    SetTxCIrq <= 1'b0;
987 147 mohor
  else
988 352 olof
    SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
989 147 mohor
end
990
 
991
always @ (posedge TxClk or posedge Reset)
992
begin
993
  if(Reset)
994 352 olof
    ResetTxCIrq_sync1 <= 1'b0;
995 147 mohor
  else
996 352 olof
    ResetTxCIrq_sync1 <= SetTxCIrq_sync2;
997 147 mohor
end
998
 
999
always @ (posedge TxClk or posedge Reset)
1000
begin
1001
  if(Reset)
1002 352 olof
    ResetTxCIrq_sync2 <= 1'b0;
1003 147 mohor
  else
1004 352 olof
    ResetTxCIrq_sync2 <= SetTxCIrq_sync1;
1005 147 mohor
end
1006
 
1007
 
1008
// Synchronizing RxC Interrupt
1009
always @ (posedge RxClk or posedge Reset)
1010
begin
1011
  if(Reset)
1012 352 olof
    SetRxCIrq_rxclk <= 1'b0;
1013 147 mohor
  else
1014 261 mohor
  if(SetPauseTimer & r_RxFlow)
1015 352 olof
    SetRxCIrq_rxclk <= 1'b1;
1016 147 mohor
  else
1017 261 mohor
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
1018 352 olof
    SetRxCIrq_rxclk <= 1'b0;
1019 147 mohor
end
1020
 
1021
 
1022
always @ (posedge Clk or posedge Reset)
1023
begin
1024
  if(Reset)
1025 352 olof
    SetRxCIrq_sync1 <= 1'b0;
1026 147 mohor
  else
1027 352 olof
    SetRxCIrq_sync1 <= SetRxCIrq_rxclk;
1028 147 mohor
end
1029
 
1030
always @ (posedge Clk or posedge Reset)
1031
begin
1032
  if(Reset)
1033 352 olof
    SetRxCIrq_sync2 <= 1'b0;
1034 147 mohor
  else
1035 352 olof
    SetRxCIrq_sync2 <= SetRxCIrq_sync1;
1036 147 mohor
end
1037
 
1038
always @ (posedge Clk or posedge Reset)
1039
begin
1040
  if(Reset)
1041 352 olof
    SetRxCIrq_sync3 <= 1'b0;
1042 147 mohor
  else
1043 352 olof
    SetRxCIrq_sync3 <= SetRxCIrq_sync2;
1044 147 mohor
end
1045
 
1046
always @ (posedge Clk or posedge Reset)
1047
begin
1048
  if(Reset)
1049 352 olof
    SetRxCIrq <= 1'b0;
1050 147 mohor
  else
1051 352 olof
    SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
1052 147 mohor
end
1053
 
1054
always @ (posedge RxClk or posedge Reset)
1055
begin
1056
  if(Reset)
1057 352 olof
    ResetRxCIrq_sync1 <= 1'b0;
1058 147 mohor
  else
1059 352 olof
    ResetRxCIrq_sync1 <= SetRxCIrq_sync2;
1060 147 mohor
end
1061
 
1062 261 mohor
always @ (posedge RxClk or posedge Reset)
1063 147 mohor
begin
1064
  if(Reset)
1065 352 olof
    ResetRxCIrq_sync2 <= 1'b0;
1066 147 mohor
  else
1067 352 olof
    ResetRxCIrq_sync2 <= ResetRxCIrq_sync1;
1068 147 mohor
end
1069
 
1070 261 mohor
always @ (posedge RxClk or posedge Reset)
1071
begin
1072
  if(Reset)
1073 352 olof
    ResetRxCIrq_sync3 <= 1'b0;
1074 261 mohor
  else
1075 352 olof
    ResetRxCIrq_sync3 <= ResetRxCIrq_sync2;
1076 261 mohor
end
1077 147 mohor
 
1078
 
1079
 
1080 21 mohor
// Interrupt generation
1081
always @ (posedge Clk or posedge Reset)
1082
begin
1083
  if(Reset)
1084
    irq_txb <= 1'b0;
1085
  else
1086 102 mohor
  if(TxB_IRQ)
1087 352 olof
    irq_txb <=  1'b1;
1088 21 mohor
  else
1089 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[0])
1090 352 olof
    irq_txb <=  1'b0;
1091 21 mohor
end
1092
 
1093
always @ (posedge Clk or posedge Reset)
1094
begin
1095
  if(Reset)
1096
    irq_txe <= 1'b0;
1097
  else
1098 102 mohor
  if(TxE_IRQ)
1099 352 olof
    irq_txe <=  1'b1;
1100 21 mohor
  else
1101 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[1])
1102 352 olof
    irq_txe <=  1'b0;
1103 21 mohor
end
1104
 
1105
always @ (posedge Clk or posedge Reset)
1106
begin
1107
  if(Reset)
1108
    irq_rxb <= 1'b0;
1109
  else
1110 102 mohor
  if(RxB_IRQ)
1111 352 olof
    irq_rxb <=  1'b1;
1112 21 mohor
  else
1113 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[2])
1114 352 olof
    irq_rxb <=  1'b0;
1115 21 mohor
end
1116
 
1117
always @ (posedge Clk or posedge Reset)
1118
begin
1119
  if(Reset)
1120 74 mohor
    irq_rxe <= 1'b0;
1121 21 mohor
  else
1122 102 mohor
  if(RxE_IRQ)
1123 352 olof
    irq_rxe <=  1'b1;
1124 21 mohor
  else
1125 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[3])
1126 352 olof
    irq_rxe <=  1'b0;
1127 21 mohor
end
1128
 
1129
always @ (posedge Clk or posedge Reset)
1130
begin
1131
  if(Reset)
1132
    irq_busy <= 1'b0;
1133
  else
1134 102 mohor
  if(Busy_IRQ)
1135 352 olof
    irq_busy <=  1'b1;
1136 21 mohor
  else
1137 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[4])
1138 352 olof
    irq_busy <=  1'b0;
1139 21 mohor
end
1140
 
1141 74 mohor
always @ (posedge Clk or posedge Reset)
1142
begin
1143
  if(Reset)
1144
    irq_txc <= 1'b0;
1145
  else
1146 147 mohor
  if(SetTxCIrq)
1147 352 olof
    irq_txc <=  1'b1;
1148 74 mohor
  else
1149 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[5])
1150 352 olof
    irq_txc <=  1'b0;
1151 74 mohor
end
1152
 
1153
always @ (posedge Clk or posedge Reset)
1154
begin
1155
  if(Reset)
1156
    irq_rxc <= 1'b0;
1157
  else
1158 147 mohor
  if(SetRxCIrq)
1159 352 olof
    irq_rxc <=  1'b1;
1160 74 mohor
  else
1161 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[6])
1162 352 olof
    irq_rxc <=  1'b0;
1163 74 mohor
end
1164
 
1165 21 mohor
// Generating interrupt signal
1166 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
1167
               irq_txe  & INT_MASKOut[1] |
1168
               irq_rxb  & INT_MASKOut[2] |
1169
               irq_rxe  & INT_MASKOut[3] |
1170
               irq_busy & INT_MASKOut[4] |
1171
               irq_txc  & INT_MASKOut[5] |
1172
               irq_rxc  & INT_MASKOut[6] ;
1173 21 mohor
 
1174
// For reading interrupt status
1175 304 tadejm
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
1176 21 mohor
 
1177
 
1178
 
1179 15 mohor
endmodule

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